ATMEL AT24C164-10SU-2.7 Two-wire serial eeprom 16k (2048 x 8) Datasheet

Features
• Low Voltage and Standard Voltage Operation
•
•
•
•
•
•
•
•
•
•
•
•
•
•
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
Internally Organized 2048 x 8 (16K)
Two-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
Write Protect Pin for Hardware Data Protection
Cascadable Feature Allows for Extended Densities
16-Byte Page Write Mode
Partial Page Writes Are Allowed
Self-Timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Automotive Grade, Extended Temperature and Lead-free/Halogen-free
Devices Available
8-lead PDIP and 8-lead JEDEC SOIC Packages
Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Two-Wire Serial
EEPROM
16K (2048 x 8)
AT24C164(1)
Note:
Description
The AT24C164 provides 16,384 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 2048 words of 8 bits each. The device’s
cascadable feature allows up to eight devices to share a common two-wire bus. The
device is optimized for use in many industrial and commercial applications where low
power and low voltage operation are essential. The AT24C164 is available in space
saving 8-lead PDIP and 8-lead JEDEC SOIC packages and is accessed via a twowire serial interface. In addition, this device is available in 2.7V (2.7V to 5.5V) and
1.8V (1.8V to 5.5V) versions.
8-lead SOIC
Table 1. Pin Configurations
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
1. Not recommended for a
new design; Please
refer to AT24C16B
datasheet. For cascadability features of the
AT24C164
(A0-A2),
please move to the
AT24C32C
device
which allows up to eight
devices that may be
addressed on a single
bus system.
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead PDIP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Rev. 0105J–SEEPR–12/06
1
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Figure 1. Block Diagram
WP
2
AT24C164
0105J–SEEPR–12/06
AT24C164
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE SELECT (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that
may be hardwired or actively driven to VDD or VSS. These inputs allow the selection for
one of eight possible devices sharing a common bus. The AT24C164 can be made
compatible with the AT24C16 by tying A2, A1 and A0 to VSS. Device addressing is discussed in detail in the device addressing section.
WRITE PROTECT (WP): The write protect input, when tied low to GND, allows normal
write operations. When WP is tied to VCC, all write operations are inhibited.
Memory Organization
The AT24C164 is internally organized with 256 pages of 8 bytes each. Random word
addressing requires an 11 bit data word address.
3
0105J–SEEPR–12/06
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol
Test Condition
CI/O
CIN
Note:
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Max
Units
1.8
5.5
V
Supply Voltage
2.5
5.5
V
VCC3
Supply Voltage
2.7
5.5
V
VCC4
Supply Voltage
4.5
5.5
V
ICC
Standby Current VCC = 5.0V
READ at 100 kHz
0.4
1.0
mA
ICC
Standby Current VCC = 5.0V
WRITE at 100 kHz
2.0
3.0
mA
ISB1
Standby Current VCC = 1.8V
VIN = VCC or VSS
0.6
3.0
µA
ISB2
Standby Current VCC = 2.5V
VIN = VCC or VSS
1.4
4.0
µA
ISB3
Standby Current VCC = 2.7V
VIN = VCC or VSS
1.6
4.0
µA
ISB4
Standby Current VCC = 5.0V
VIN = VCC or VSS
8.0
18.0
µA
ILI
Input Leakage Current
VIN = VCC or VSS
0.10
3.0
µA
ILO
Output Leakage Current
VOUT = VCC or VSS
0.05
3.0
µA
VIL(1)
Input Low Level
–0.6
VCC x 0.3
V
VIH(1)
Input High Level
VCC x 0.7
VCC + 0.5
V
VOL2
Output Low Level VCC = 3.0V
IOL = 2.1 mA
0.4
V
VOL1
Output Low Level VCC = 1.8V
IOL = 0.15 mA
0.2
V
Note:
4
Test Condition
Min
Typ
1. VIL min and VIH max are reference only and are not tested.
AT24C164
0105J–SEEPR–12/06
AT24C164
Table 4. AC Characteristics
Applicable over recommended operating range from TA = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
2.7-, 2.5-, 1.8-volt
Symbol
Parameter
Min
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
tHIGH
Clock Pulse Width High
Max
5.0-volt
Min
100
Max
Units
400
kHz
4.7
1.2
µs
4.0
0.6
µs
(1)
tI
Noise Suppression Time
100
tAA
Clock Low to Data Out Valid
0.1
tBUF
Time the bus must be free before a new transmission can
start(1)
4.7
1.2
µs
tHD.STA
Start Hold Time
4.0
0.6
µs
tSU.STA
Start Set-up Time
4.7
0.6
µs
tHD.DAT
Data In Hold Time
0
0
µs
tSU.DAT
Data In Set-up Time
200
100
ns
(1)
4.5
0.1
50
ns
0.9
µs
tR
Inputs Rise Time
1.0
0.3
µs
tF
Inputs Fall Time(1)
300
300
ns
tSU.STO
Stop Set-up Time
4.7
0.6
µs
tDH
Data Out Hold Time
100
50
ns
tWR
Write Cycle Time
Endurance(1)
5.0V, 25°C, Page Mode
Note:
10
1M
10
1M
ms
Write
cycles
1. These parameters are characterized and is not 100% tested.
5
0105J–SEEPR–12/06
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C164 features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, the
AT24C164 can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
6
AT24C164
0105J–SEEPR–12/06
AT24C164
Figure 2. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Figure 3. Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn
(1)
twr
STOP
CONDITION
Note:
START
CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
7
0105J–SEEPR–12/06
Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
8
AT24C164
0105J–SEEPR–12/06
AT24C164
Device Addressing
The AT24C164 requires an 8-bit device address word following a start condition to
enable the chip for read or write operations (see Figure 7 on page 10). The most significant bit must be a one followed by the A2, A1 and A0 device select bits (the A1 bit must
be the compliment of the A1 input pin signal). The next 3 bits are used for memory block
addressing and select one of the eight 256 x 8 memory blocks. These bits should be
considered the three most significant bits of the data word address. The eighth bit of the
device address is the read/write select bit. A read operation is selected if this bit is high
or a write operation is selected if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the chip will return to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR , to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (see Figure 8 on page 11).
PAGE WRITE: The AT24C164 is capable of a 16-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition
after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt
of the first data word, the microcontroller can transmit up to fifteen more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller
must terminate the page write sequence with a stop condition (see Figure 9 on page
11).
The data word address lower 4 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than sixteen data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero allowing the read or write sequence to continue.
9
0105J–SEEPR–12/06
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page to the first
byte of the first page. The address “roll over” during write is from the last byte of the current page to first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (see Figure 10 on page 11).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (see Figure 11 on page 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12 on page 12).
Figure 7. Device Address
10
AT24C164
0105J–SEEPR–12/06
AT24C164
Figure 8. Byte Write
Figure 9. Page Write
Figure 10. Current Address Read
Figure 11. Random Read
11
0105J–SEEPR–12/06
Figure 12. Sequential Read
12
AT24C164
0105J–SEEPR–12/06
AT24C164
Ordering Information(1)
Ordering Code
Package
Operation Range
AT24C164-10PU-2.7(2)
AT24C164-10PU-1.8(2)
AT24C164-10SU-2.7(2)
AT24C164-10SU-1.8(2)
8P3
8P3
8S1
8S1
Lead-free/Halogen-free
Industrial Temperature
(–40°C to 85°C)
AT24C164-W2.7-11(3)
AT24C164-W1.8-11(3)
Die Sale
Die Sale
Industrial Temperature
(–40°C to 85°C)
Notes:
1. Not recommended for new design; Please refer to AT24C16B datasheet. For 2.7V devices used in the 4.5V to 5.5V range,
please refer to performance values in the AC and DC characteristics tables.
2. “U” designates Green package + RoHS compliant.
3. Available in waffle pack and wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
Options
–2.7
Low-Voltage (2.7V to 5.5V)
–1.8
Low-Voltage (1.8V to 5.5V)
13
0105J–SEEPR–12/06
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
b2
b3
b
4 PLCS
Side View
L
SYMBOL
NOM
MAX
NOTE
2
A
–
–
0.210
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
3
D1
0.005
–
–
3
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
e
0.100 BSC
eA
0.300 BSC
L
Notes:
MIN
0.115
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
AT24C164
0105J–SEEPR–12/06
AT24C164
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.00
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
∅
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
R
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1
REV.
B
15
0105J–SEEPR–12/06
Revision History
16
Doc. Rev.
Comments
0105J
Added note to 1st page; ‘Not recommended for new design; please refer to
AT24C16B datasheet. For cascadability features of the AT24C164 (A0-A2),
please move to the AT24C32C device which allows up to eight devices that
may be addressed on a single bus system.’
AT24C164
0105J–SEEPR–12/06
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0105J–SEEPR–12/06
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