AD AD9051BRS 10-bit, 60 msps a/d converter Datasheet

a
FEATURES
60 MSPS Sampling Rate
9.3 Effective Number of Bits at fIN = 10.3 MHz
250 mW Total Power at 60 MSPS
Selectable Input Bandwidth of 50 MHz or 130 MHz
On-Chip T/H and Voltage Reference
Single +5 V Supply Voltage
+5 V or +3 V Logic I/O Compatible
Input Range and Output Coding Options Available
APPLICATIONS
Medical Imaging
Digital Communications
Professional Video
Instrumentation
Set-Top Box
GENERAL DESCRIPTION
The AD9051 is a complete 10-bit monolithic sampling analogto-digital converter (ADC) with an onboard track-and-hold and
reference. The unit is designed for low cost, high performance
applications and requires only +5 V and an encode clock to
achieve 60 MSPS sample rates with 10-bit resolution.
10-Bit, 60 MSPS
A/D Converter
AD9051
FUNCTIONAL BLOCK DIAGRAM
BWSEL
+5V
GND
IN
OUT
+5V
AD9051
AINB
T/H
AIN
SUM
AMP
ENCODE
TIMING
REFERENCE
CIRCUITS
ADC
DAC
DECODE
LOGIC
10
ADC
A +2.5 V reference is included onboard, or the user can provide
an external reference voltage for gain control or matching of
multiple devices. Fabricated on a state-of-the-art BiCMOS
process, the AD9051 is packaged in a space saving surface
mount package (SSOP) and is specified over the industrial temperature range (–40°C to +85°C).
The encode clock is TTL compatible and the digital outputs are
CMOS; both can operate with +5 V/+3 V logic. The two-step
architecture used in the AD9051 is optimized to provide the
best dynamic performance available while maintaining low
power consumption.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
(VD = +5 V, VDD = +3 V; external reference = 2.50 V; ENCODE = 60 MSPS
AD9051–SPECIFICATIONS unless otherwise noted)
Parameter
Temp
Test
Level
Min
RESOLUTION
AD9051BRS
Typ
Max
AD9051BRS-2V
Min
Typ
Max
10
DC ACCURACY
Differential Nonlinearity
10
Bits
+25°C
Full
+25°C
Full
+25°C
+25°C
Full
Full
I
V
I
V
I
I
VI
V
ANALOG INPUT
Input Voltage Range 2
Input Offset Voltage
Input Resistance
Input Capacitance
Analog Bandwidth (BW SEL +V D/NC)3
+25°C
+25°C
+25°C
+25°C
+25°C
V
I
I
V
V
BANDGAP REFERENCE
Output Voltage (I O @ 200 µA)
Temperature Coefficient
Power Supply Sensitivity
Reference Input Current (V IN = 2.50 V)
Full
Full
Full
Full
VI
V
V
VI
2.4
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate 4
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Valid Time (t V)5
Output Propagation Delay (t PD)5
Full
Full
+25°C
+25°C
Full
Full
VI
IV
V
V
VI
VI
60
+25°C
+25°C
V
V
+25°C
+25°C
+25°C
V
I
V
8.93
9.6
9.3
9.1
+25°C
+25°C
+25°C
V
I
V
55
+25°C
+25°C
+25°C
V
I
V
56
+25°C
+25°C
+25°C
V
I
V
–74
–73
–67
–60
–68
–64
–60
–58
dBc
dBc
dBc
+25°C
+25°C
+25°C
V
I
V
–74
–70
–65
–60
–69
–65
–60
–60
dBc
dBc
dBc
+25°C
+25°C
+25°C
V
V
V
–65
0.1
0.5
Integral Nonlinearity
No Missing Codes
Gain Error1
Gain Tempco1
0.75
1.50
0.90
0.75
1.50
0.90
␣ ␣ ␣ ␣ ␣ GUARANTEED
± 0.3
± 2.5
± 5.0
± 10
Units
–14
4.0
1.25
5.0
6.0
5
50/130
2.5
± 33
6.2
2.0
0.75
1.50
0.90
0.75
1.50
0.90
␣ ␣ ␣ ␣ ␣ GUARANTEED
± 0.3
± 3.0
± 5.5
± 10
26
–14
4.0
2.6
2.4
25
2.0
5.0
6.0
5
50/130
2.5
± 33
6.2
2.0
26
2.6
25
60
2.0
2.5
5
5.0
5.5
10
4.0
2.0
2.5
5
5.0
5.5
10
4.0
LSB
LSB
LSB
LSB
␣␣␣
% FS
% FS
ppm/°C
V p-p
LSB
kΩ
pF
MHz
V
ppm/°C
mV/V
µA
MSPS
MSPS
ns
ps, rms
ns
ns
6
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
ENOBS
fIN = 1.20 MHz
fIN = 10.3 MHz
fIN = 29.0 MHz
Signal-to-Noise Ratio (SINAD)
fIN = 1.20 MHz
fIN = 10.3 MHz
fIN = 29.0 MHz
Signal-to-Noise Ratio (Without Harmonics)
fIN = 1.20 MHz
fIN = 10.3 MHz
fIN = 29.0 MHz
2nd Harmonic Distortion
fIN = 1.20 MHz
fIN = 10.3 MHz
fIN = 29.0 MHz
3rd Harmonic Distortion
fIN = 1.20 MHz
fIN = 10.3 MHz
fIN = 29.0 MHz
Two-Tone Intermodulation
Distortion (IMD)
Differential Phase
Differential Gain
10
10
–2–
10
10
ns
ns
8.93
9.6
9.3
9.1
ENOB
ENOB
ENOB
58.5
57
55
54
57.5
56
54
dB
dB
dB
59
58
56.5
56
59
58
56.5
dB
dB
dB
–65
0.1
0.5
dBc
Degrees
%
REV. A
AD9051
Parameter
Temp
Test
Level
ENCODE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Encode Pulsewidth High (t EH)
Encode Pulsewidth Low (t EL)
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
V
IV
IV
Full
Full
Full
Full
VI
VI
VI
VI
DIGITAL OUTPUTS
Logic “1” Voltage (5.0 VDD)
Logic “0” Voltage (5.0 VDD)
Logic “1” Voltage (3.0 VDD)
Logic “0” Voltage (3.0 VDD)
Output Coding7
POWER SUPPLY
VD, VDD Supply Current
Power Dissipation8
Power Supply Rejection Ratio
(PSRR)9
Min
AD9051BRS
Typ
Max
2.0
AD9051BRS-2V
Min
Typ
Max
2.0
0.8
1
1
0.8
1
1
7.5
7.5
7.5
7.5
7.5
7.5
4.95
4.95
0.05
2.95
0.05
2.95
Offset Binary
V
V
µA
µA
pF
ns
ns
V
V
V
V
0.05
0.05
Units
Offset Binary
Full
Full
VI
VI
50
250
63
315
50
250
63
315
mA
mW
+25°C
I
±2
± 10
±7
± 15
mV/V
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).
2
Contact factory or authorized sales agent for information concerning the availability of expanded input voltage range devices.
3
3 dB bandwidth with full-power input signal.
4
Minimum conversion rate at which all data sheet specifications remain stable.
5
tV and tPD are measured from the threshold crossing of the ENCODE input to valid TTL levels 0.5 V and 2.4 V of the digital outputs with V DD = 3.0 V. The output
ac load during test is 5 pF.
6
SNR/harmonics tested with an analog input voltage of –0.5 dBfs. All tests performed at 60 MSPS.
7
Contact factory or authorized sales agent for information concerning the availability of alternative output coding and input range devices.
8
Power dissipation is measured under the following conditions: analog input = –FS at 60 MSPS ENCODE.
9
A change in input offset voltage with respect to a change in V D.
Specifications subject to change without notice.
REV. A
–3–
AD9051
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
Test Level
VD, VDD␣ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . +150°C
I.
100% production tested.
II. 100% production tested at +25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
VI. 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature range.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Options
AD9051BRS
AD9051BRS-2V
AD9051/PCB
AD9051-2V/PCB
–40°C to +85°C
–40°C to +85°C
+25°C
+25°C
28-Lead Shrink Small Outline Package (SSOP)
28-Lead Shrink Small Outline Package (SSOP)
RS-28
RS-28
Evaluation Board
Evaluation Board
Table I. Digital Coding (Single-Ended Input with AIN, AINB Bypassed to GND)
Analog Input
Voltage Level
OR
(Out of Range)
Digital Output
MSB␣ .␣ .␣ .␣ ␣ LSB
3.126 (3.50)*
2.5
1.874 (1.50)*
Positive Full Scale + 1 LSB
Midscale
Negative Full Scale – 1 LSB
1
0
1
1111111111
0111111111
0000000000
*(BRS-2V Version)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9051 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A
AD9051
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Function
1, 6, 7, 12, 21, 23
2, 8, 11
3
4
5
9
10
13
GND
VD
VREFOUT
VREFIN
BWSEL
AINB
AIN
ENCODE
14
OR
15
16–19
20, 22
24–27
28
D9 (MSB)
D8–D5
VDD
D4–D1
D0 (LSB)
Ground.
Analog +5 V power supply.
Internal bandgap voltage reference (nominally +2.5 V).
Input to reference amplifier. Voltage reference for ADC is connected here.
Bandwidth Select. NC = 130 MHz nominal. +VD = 50 MHz nominal.
Complementary analog input pin (Analog input bar).
Analog input pin.
Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding)
on rising edge of encode signal.
Out of range signal. Logic “0” when analog input is in nominal range. Logic “1” when
analog input is out of nominal range.
Most significant bit of ADC output.
Digital output bits of ADC.
Digital output power supply (only used by digital outputs).
Digital output bits of ADC.
Least significant bit of ADC output.
PIN CONFIGURATION
N
N+1
N+2
N+3
N+4
N+5
AIN
GND 1
28 D0 (LSB)
VD 2
27 D1
VREFOUT 3
26 D2
VREFIN 4
25 D3
BWSEL 5
24 D4
GND 6
GND 7
tA
ENCODE
tPD
DIGITAL
OUTPUTS
23 GND
AD9051
N–5
N–4
N–3
N–2
N–1
AIN 10
19 D5
VD 11
18 D6
GND 12
17 D7
ENCODE 13
16 D8
Figure 1. Timing Diagram
VD
VD
12kV
12kV
AINB (PIN 9)
15 D9 (MSB)
AIN (PIN 10)
12kV
INPUT
BUFFER
ENCODE
(PIN 13)
12kV
Analog Input
VDD (PINS 20, 22)
+3V TO +5V
Encode
VD
VREFOUT
(PIN 3)
D0–D9, OR
Output Stage
Figure 2. Equivalent Circuits
REV. A
N
22 VDD
TOP VIEW
VD 8 (Not to Scale) 21 GND
20 VDD
AINB 9
OR 14
t EH t EL
–5–
VREF
AD9051–Typical Performance Characteristics
255
0
250
–1
DISSIPATION – mW
245
BWSEL DISABLED
ADC GAIN – dB
240
235
230
225
–2
–3
BWSEL ENABLED
–4
220
–5
215
210
1
5
20
15
25
30
35
40
45
CLOCK RATE – MSPS
50
55
–6
60
1
40
52
80
118
141
ANALOG INPUT FREQUENCY – MHz
201
Figure 6. ADC Gain vs. AIN Frequency
Figure 3. Power Dissipation vs. Clock Rate
59
60
AIN = 10.3MHz
59
58.5
SNR @ 40MSPS
ENCODE = 40MSPS
58
58
SINAD @ 40MSPS
57.5
56
SNR – dB
SNR/SINAD – dB
57
55
SINAD @ 60MSPS
54
ENCODE = 60MSPS
57
56.5
SNR @ 60MSPS
53
56
52
55.5
51
50
0
10
20
30
40
50
60
FREQUENCY – MHz
70
80
55
–40
90
–20
0
25
45
TEMPERATURE – 8C
65
85
Figure 7. SNR vs. Temperature
Figure 4. SNR/SINAD vs. AIN Frequency
–50
60
–55
59
AIN = 10.3MHz
2ND @ 60MSPS
–60
58
3RD @ 40MSPS
57
–65
SNR – dB
dB
–70
2ND @ 40MSPS
–75
3RD @ 60MSPS
–80
56
55
54
–85
53
–90
52
–95
51
–100
50
0
10
20
30
40
50
60
FREQUENCY – MHz
70
80
90
5
Figure 5. Harmonics vs. AIN Frequency
10
20
30
40
ENCODE – MSPS
50
60
70
Figure 8. SNR vs. Clock Rate
–6–
REV. A
AD9051
0
0
–10
AIN = 10.3MHz
ENCODE = 40 MSPS
SNR = 58.6dB
SINAD = 57.69dB
–20
–30
–30
–40
–40
dB
dB
–20
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
2.5
5.0
AIN = 15.2MHz
ENCODE = 60 MSPS
SNR = 58.29dB
SINAD = 57.23dB
–10
7.5
10
12.5
FREQUENCY – MHz
15
17.5
20
0
Figure 9. FFT Plot 40 MSPS, 10.3 MHz
AIN = 15.2MHz
ENCODE = 40 MSPS
SNR = 58.47dB
SINAD = 57.04dB
–20
dB
11.3
15.0
18.8
FREQUENCY – MHz
22.5
26.3
30
0
–10
–20
–30
–30
–40
–40
dB
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
0
2.5
5.0
7.5
10
12.5
FREQUENCY – MHz
15
17.5
–100
20
0
3.8
7.5
11.3
15.0
18.8
FREQUENCY – MHz
22.5
26.3
30
Figure 13. FFT Plot 60 MSPS, 21.7 MHz
Figure 10. FFT Plot 40 MSPS, 15.2 MHz
0
0
AIN = 10.3MHz
ENCODE = 60 MSPS
SNR = 58.15dB
SINAD = 57.25dB
–10
–20
–20
–30
–40
–40
dB
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
0
3.8
7.5
11.3
15.0
18.8
FREQUENCY – MHz
22.5
26.3
AIN1 = 9.5MHz, –7dBFS
AIN2 = 9.9MHz, –7dBFS
IMD = –65dBc
ENCODE = 60 MSPS
–10
–30
–100
AIN = 21.7MHz
ENCODE = 60 MSPS
SNR = 57.76dB
SINAD = 56.27dB
–10
–50
dB
7.5
Figure 12. FFT Plot 60 MSPS, 15.2 MHz
0
–100
30
Figure 11. FFT Plot 60 MSPS, 10.3 MHz
REV. A
3.8
0
3.8
7.5
11.3
15.0
18.8
FREQUENCY – MHz
22.5
Figure 14. Two-Tone IMD
–7–
26.3
30
AD9051
1.2
6.5
3V RISING
6
0.8
5.5
tPD – ns
% GAIN ERROR
1.0
0.6
5V FALLING
5
3V FALLING
0.4
5V RISING
4.5
0.2
0
0
10
20
30
40
ENCODE – MSPS
4
–40
60
50
Figure 15. Gain vs. Clock Rate
–20
0
25
45
TEMPERATURE – 8C
85
65
Figure 18. tPD vs. Temperature +3 V/+5 V
16
2.51
14
2.50
2.49
12
REF VOLTAGE
OFFSET – mV
2.48
10
8
6
4
2.46
2.45
2.44
2
0
VOUT
2.47
2.43
0
10
20
30
40
ENCODE – MSPS
2.42
60
50
Figure 16. Offset vs. Clock Rate
0.1 0.25 0.4 0.55 0.7 0.85 1 1.15 1.3 1.45 1.6 1.75 1.9 2.0
SOURCE CURRENT – mA
Figure 19. Reference Load Regulation
60
80
58
70
56
60
SNR @ 40MSPS
54
% OCCURANCE
SNR – dB
SNR @ 60MSPS
52
50
48
50
40
30
46
20
44
10
42
40
25
0
30
35
40
55
45
50
DUTY CYCLE – %
60
65
70
75
512
Figure 17. SNR vs. Duty Cycle
513
514
515
CODE
516
517
518
Figure 20. Midscale Histogram (Inputs Tied)
–8–
REV. A
AD9051
THEORY OF OPERATION
140V
Refer to the block diagram on the front page.
+5V
The AD9051 employs a subranging architecture with digital
error correction. This combination of design techniques ensures
true 10-bit accuracy at the digital outputs of the converter.
VIN
–0.625V
TO
+0.625V
10
AD9631
AD9051
9
At the input, the analog signal is buffered by a high speed differential buffer and applied to a track-and-hold (T/H) that holds
the analog value present when the unit is strobed with an
ENCODE command. The conversion process begins on the
rising edge of this pulse. The two stage architecture completes a
coarse and then a fine conversion of the T/H output signal.
0.1mF
+5V
1kV
AD820
1kV
0.1mF
Figure 21. Single Supply, Single-Ended, DC-Coupled ␣ ␣
AD9051
Error correction and decode logic correct and align data from
the two conversions and present the result as a 10-bit parallel
digital word. Output data are strobed on the rising edge of the
ENCODE command. The subranging architecture results in five
pipeline delays for the output data. Refer to the AD9051 Timing
Diagram.
140V
+5V
+5V
140V
0.1mF
VIN
–0.625V
TO
+0.625V
USING THE AD9051
3 V System
10
AD9051
AD9631
–5V
The digital input and outputs of the AD9051 can be easily
configured to directly interface to 3 V logic systems. The encode
input (Pin 13) is TTL compatible with a logic threshold of
1.5 V. This input is actually a CMOS stage (refer to Equivalent
Encode Input Stage) with a TTL threshold, allowing operation
with TTL, CMOS and 3 V CMOS logic families. Using 3 V
CMOS logic allows the user to drive the encode directly without
the need to translate to +5 V. This saves the user power and
board space. As with all high speed data converters, the clock
signal must be clean and jitter free to prevent the degradation of
dynamic performance.
9
0.1mF
Figure 22. Single-Ended, Capacitively-Coupled AD9051
140V
+5V
+5V
140V
VIN
–0.625V
TO
+0.625V
0.1mF
AD9631
T1-1T
Analog Input
The analog input of the AD9051 is a differential input buffer
(refer to AD9051 Equivalent Analog Input). The differential
inputs are internally biased at +2.5 V, obviating the need for
external biasing. Excellent performance is achieved whether the
analog inputs are driven single-endedly or differentially (for best
dynamic performance, impedances at AIN and AINB should
match).
AD9051
9
Figure 23. Differentially Driven AD9051 Using Transformer Coupling
The AD830 provides a unique method of providing dc level
shift for the analog input. Using the AD830 allows a great deal
of flexibility for adjusting offset and gain. Figure 24 shows the
AD830 configured to drive the AD9051. The offset is provided
by the internal biasing of the AD9051 differential input (Pin 9).
For more information regarding the AD830, see the AD830
data sheet.
VIN
–0.625V
TO
+0.625V
+15V
1
2
3 AD830
4
–5V
Figure 21 shows typical connections for the analog inputs when
using the AD9051 in a dc coupled system with single-ended
signals. All components are powered from a single +5 V supply.
The AD820 is used to offset the ground referenced input signal
to the level required by the AD9051.
10
50V
–5V
The AD9051 outputs can also directly interface to 3 V logic
systems. The digital outputs are standard CMOS stages (refer to
AD9051 Output Stage) with isolated supply pins (Pins 20, 22
VDD). By varying the voltage on the VDD pins, the digital output
levels vary respectively. By connecting Pins 20 and 22 to the
3 V logic supply, the AD9051 will supply 3 V output levels.
Care should be taken to filter and isolate the output supply of
the AD9051 as noise could be coupled into the ADC, limiting
performance.
+5V
7
10
AD9051
9
0.1mF
Figure 24. Level-Shifting with the AD830
AC coupling of the analog inputs of the AD9051 is easily accomplished. Figure 22 shows capacitive coupling of a single-ended
signal while Figure 23 shows transformer coupling differentially
into the AD9051.
␣␣
REV. A
+5V
140V
–9–
AD9051
Overdrive of the Analog Input
The input range can be adjusted by varying the reference voltage applied to the AD9051. No appreciable degradation in
performance occurs when the reference is adjusted ± 5%. The
full-scale range of the ADC tracks reference voltage changes
linearly.
Special care was taken in the design of the analog input section
of the AD9051 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is +1.875 V
to 3.125 V (1.25 V p-p centered at 2.5 V). Out-of-range comparators detect when the analog input signal is out of this range
and the input buffer is clamped. The digital outputs are locked
at their maximum or minimum value (i.e., all “0” or all “1”).
This precludes the digital outputs changing to an invalid value
when the analog input is out of range.
EVALUATION BOARD
The AD9051 evaluation board is a convenient and easy way to
evaluate the performance of the AD9051.
Analog Input
The input is protected to one volt outside the power supply
rails. For nominal power (+5 V and ground), the analog input
will not be damaged with signals from +5.5 V to –0.5 V.
The evaluation board requires a 1.25 V p-p input. The signal is
buffered by an AD9631 op amp in the unity gain configuration.
The signal is then ac coupled before entering the AD9051
where a dc offset is internally generated. Leave E3 unconnected
to E4 for usage with the AD9631. To evaluate performance
without this buffer, remove the AD9631 and connect E3 to E4.
Keep E1 connected to E2 for use in the low bandwidth mode
(50 MHz). Removing this connector will enable high bandwidth mode (130 MHz). Low bandwidth is the recommended
mode of operation in order to minimize any high frequency
noise coupling into the input of the AD9051.
Timing
The performance of the AD9051 is very insensitive to the duty
cycle of the clock. Pulsewidth variations of as much as ± 15%
for encode rates of 40 MSPS and ± 10% for encode rates of
60 MSPS will cause no degradation in performance. (See Figure 17, SNR vs. Duty Cycle.)
The AD9051 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the encode command (refer to Figure 1, Timing Diagram). The length of the output data lines
and loads placed on them should be minimized to reduce transients within the AD9051; these transients can detract from the
converter’s dynamic performance.
Encode
The evaluation board is driven with a TTL or CMOS clock
into a clock buffer of ac type CMOS logic. This buffer will
drive the encode to the AD9051, the data latches, and a “data
ready.”
Data Out
Power Dissipation
The digital data is captured by a pair 74ACQ574 latches. Any
unused connector pins should be grounded to the device that is
capturing data from the evaluation board. This minimizes any
grounding loops that may degrade performance. A separate
power plane is provided for supplying the latches, clock buffer,
and digital outputs of the AD9051. This supply can be 3 V or
5 V.
The power dissipation specification in the parameter table is
measured under the following conditions: encode is 60 MSPS,
analog input is –FS.
As shown in Figure 3, the actual power dissipation varies based
on these conditions. For instance, reducing the clock rate will
reduce power as expected for CMOS-type devices. The loading
determines the power dissipated in the output stages.
The analog input frequency and amplitude in conjunction with
the clock rate determine the switching rate of the output data
bits. Power dissipation increases as more data bits switch at
faster rates. For instance, if the input is a dc signal that is out of
range, no output bits will switch. This minimizes power in the
output stages, but is not realistic from a usage standpoint.
The dissipation in the output stages can be minimized by interfacing the outputs to 3 V logic (refer to Using the AD9051, 3 V
System). The lower output swings minimize power consumption as follows: (1/2 CLOAD × VDD2 × Update Rate).
Voltage Reference
A stable and accurate +2.5 V voltage reference is built into the
AD9051 (Pin 3, VREFOUT). In normal operation the internal
reference is used by strapping together Pins 3 and 4 of the
AD9051. The internal reference has 500 µA of extra drive current that can be used for other circuits.
Some applications may require greater accuracy, improved
temperature performance, or adjustment of the gain of the
AD9051, which cannot be obtained by using the internal reference. For these applications, an external +2.5 V reference can
be used to connect to Pin 4 of the AD9051. The VREFIN
requires 2 µA of drive current.
Layout
The AD9051 is not layout sensitive if some important guidelines are met. The evaluation board layout provides an example where these guidelines have been followed to optimize
performance.
• Provide a solid ground plane connecting both analog and
digital sections. Cuts in this plane near the AD9051 should
be kept to a minimum.
• Excellent bypassing is essential. All capacitors should be
placed as close as possible to the AD9051. No vias should
be used to connect capacitors to the AD9051 as this may
create a parasitic inductance that can reduce bypassing
effectiveness.
The AD9051 evaluation board is provided as a design example
for customers of Analog Devices. ADI makes no warranties
express, statutory, or implied regarding merchantability of
fitness for a particular purpose.
–10–
REV. A
AD9051
REV. A
Figure 25. Evaluation Board Top Layer
Figure 27. Evaluation Board Bottom Layer
Figure 26. Evaluation Board Ground Layer
Figure 28. Silkscreen
–11–
AD9051
+5VA
GND
VDD
–5V
C17
0.1mF
C10
0.1mF
C11
0.1mF
C14
1mF
C13
0.1mF
VDD
C15
1mF
74ACQ574
AD9051
1
GND
GND
P6
1
+5VA
2
GND
3
–5V
4
GND
5
VDD
2
+5VA
2
3
4
C5
R1
25V 0.1mF
C3
0.1mF
3
VREFOUT
D2 26
4
VREFIN
D3 25
5
BWSEL
D4 24
6
7
8
9
10
2
U2
GND2
GND5 23
7
GND3
VDD1 22
VDD
GND6 21
GND
9
R2
C6
25V 0.1mF
C7
0.1mF
GND
10 AIN
D5 19
11 +5A3
D6 18
U3
3
14 OR
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q5
D6
Q6
D7
Q7
GND
VDD
1
2
D7 17
4
5
D8 16
6
7
(MSB) D9 15
6
10
OUT_EN
GND
16
P1
15
1
14
2
13
3
12
4
11
5
6
8
9
10
11
VCC
D0
Q0
D1
Q1
D2
Q2
D3
D4
U5
Q3
Q4
D5
Q5
D6
Q6
D7
GND
74AC00
Q7
CLOCK
12
20
13
19
14
18
15
17
16
16
17
15
18
14
19
13
20
12
11
GND
GND
8
21
22
23
24
25
74AC00
12
13
U3
11
74AC00
Figure 29. Evaluation Board Schematic
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SSOP
(RS-28)
15
1
14
0.212 (5.38)
0.205 (5.21)
28
PRINTED IN U.S.A.
0.407 (10.34)
0.397 (10.08)
0.311 (7.9)
0.301 (7.64)
VDD
17
74ACQ574
9
U3
CLOCK
18
VDD
4
5
10
Q4
D5
19
C16
0.1mF
8
9
U4
20
7
74AC00
U3
VCC
GND
3
13 ENCODE
1
R6
50V
C9
0.1mF
VDD2 20
AINB
12 GND4
AD9631
J1
+5A2
C8
0.1mF
GND
+5VA
6
2
GND
6
8
+5VA
R3
140V
3
4
D1 27
+5VA1
U1
E3 E4
R5
50V
3
E2 E1
+5VA
5
GND
J1
(LSB) D0 28
GND1
5
C2
0.1mF
1
GND
R4
140V
1
C1
0.1mF
2
OUT_EN
C3321a–0–11/98
C12
1mF
0.078 (1.98) PIN 1
0.068 (1.73)
0.008 (0.203) 0.0256
(0.65)
0.002 (0.050) BSC
0.07 (1.79)
0.066 (1.67)
8°
0.015 (0.38)
0°
SEATING 0.009 (0.229)
0.010 (0.25)
PLANE
0.005 (0.127)
–12–
0.03 (0.762)
0.022 (0.558)
REV. A