ams AS1157 Single/dual lvds receiver Datasheet

A S 11 5 3 / 5 5 / 5 7 / 5 8
D a ta S he e t
S i n g l e / D u a l LV D S R e c e i v e r s
1 General Description
2 Key Features
The AS1153/55/57/58 are Single/Dual flow-through
LVDS (low-voltage differential signaling) receivers which
accept LVDS differential inputs and convert them to
LVCMOS outputs. The receivers are perfect for lowpower low-noise applications requiring high signaling
rates and reduced EMI emissions.
!
Flow-Through Pinout
!
Guaranteed 260Mbps Data Rate
!
300ps Pulse Skew (Max)
The devices are guaranteed to receive data at speeds
up to 260Mbps (130MHz) over controlled impedance
media of approximately 100Ω. Supported transmission
media are PCB traces, backplanes, and cables.
!
Conform to ANSI TIA/EIA-644 LVDS Standards
!
Single +3.3V Supply
!
Operating Temperature Range: -40 to +85ºC
!
Failsafe Circuit
!
Integrated Termination (AS1157/58)
!
8-pin SOIC Package
The AS1155/58 are single LVDS receivers, and the
AS1153/57 are dual LVDS receivers.
The AS1157/58 features integrated parallel termination
resistors (nominally 107Ω), which eliminate the requirement for discrete termination resistors, and reduce stub
lengths. The AS1153/55 uses high impedance inputs
and requires an external termination resistor when used
in a point-to-point connection.
The integrated Failsafe feature sets the output high if the
inputs are open, undriven and terminated, or undriven
and shorted.
All inputs conform to the ANSI TIA/EIA- 644 LVDS standards. Flow-through pinout simplifies PC board layout
and reduces crosstalk by separating the LVDS inputs
and LVCMOS outputs.
The devices are available in a 8-pin SOIC package.
3 Applications
Digital Copiers, Laser Printers, Cellular Phone Base Stations, Add/Drop Muxes, Digital Cross-Connects,
DSLAMs, Network Switches/Routers, Backplane Interconnect, Clock Distribution Computers, Intelligent Instruments, Controllers, Critical Microprocessors and
Microcontrollers, Power Monitoring, and Portable/Battery-Powered Equipment.
Figure 1. Block Diagrams
AS1155/58
AS1153/57
IN1-
VCC
IN1-
VCC
IN1+
OUT1
IN1+
OUT1
N/C
N/C
IN2+
OUT2
N/C
GND
IN2-
GND
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AS1153/55
Data Sheet - P i n o u t a n d P a c k a g i n g
4 Pinout and Packaging
Pin Assignments
Figure 2. AS1153/55 and AS1157/58 Pin Assignments (Top View)
IN1-
1
IN1+
2
8
VCC
IN1-
1
7
OUT1
IN1+
2
N/C
VCC
7
OUT1
AS1153/57
AS1155/58
N/C
8
3
6
N/C
IN2+ 3
6
OUT2
4
5
GND
IN2-
5
GND
4
Pin Descriptions
Table 1. AS1153/55 and AS1157/58 Pin Descriptions
Pin Number
Pin Name
Description
AS1155/58
AS1153/57
1
1
IN1-
Inverting Differential Receiver Input
2
2
IN1+
Noninverting Differential Receiver Input
3
IN2+
Noninverting Differential Receiver Input
4
IN2-
Inverting Differential Receiver Input
5
GND
Ground
6
OUT2
LVCMOS/LVTTL Receiver Output
7
7
OUT1
LVCMOS/LVTTL Receiver Output
8
8
VCC
Power-Supply Input. Bypass VCC to GND with 0.1µF and
0.001µF ceramic capacitors.
N/C
Not connected
5
3, 4, 6
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AS1153/55
Data Sheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Min
Max
Units
VCC to GND
-0.3
+5.0
V
INx+, INx- to GND
-0.3
+5.0
V
OUTx to GND
-0.3
VCC + 0.3
V
128
ºC/W
+150
ºC
+150
ºC
+85
ºC
Thermal Resistance ΘJA
Storage Temperature Range
-65
Maximum Junction Temperature
Operating Temperature Range
-40
Package Body Temperature
ESD Protection
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-4
Notes
Typical 4-layer application
+260
ºC
The reflow peak soldering
temperature (body temperature)
specified is in compliance with
IPC/JEDEC J-STD-020C
“Moisture/ Reflow Sensitivity
Classification for Non-Hermetic
Solid State Surface Mount
Devices”.
+4
kV
Human Body Model, INx+, INx-
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AS1153/55
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
DC Electrical Characteristics
VCC = +3.0 to +3.6V, Differential Input Voltage |VID| = +0.1 to +1.0V, Common-Mode Voltage VCM = |VID/2| to
2.4V - |VID/2|,TAMB = -40 to +85ºC. Typical values are at VCC = +3.3V, TAMB = +25ºC (unless otherwise specified).
Table 3. DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
100
mV
LVDS Inputs (INx+, INx-)
Differential Input High
Threshold
VTH
Differential Input Low
Threshold
VTL
1
-100
Input Current
(AS1153/55)
IINx+,
IINx-
Differential Input
Resistance (AS1157/58)
RDIFF
Differential Input
Resistance (AS1153/55)
RDIFF
2
mV
0.1V ≤ |VID| ≤ 0.6V
-20
20
µA
0.6V ≤ |VID| ≤ 1.0V
-25
25
µA
VCC = 3.6V or 0, Figure 18 on page 9
90
107
132
Ω
VCC = 3.6V or 0, Figure 18 on page 9
40
100
IOH = 4.0mA
(AS1153/
55)
Open, undriven short, or
undriven 100Ω parallel
termination
2.7
3.2
VID = +100mV
2.7
3.2
IOH = 4.0mA
(AS1157/
58)
Open or undriven short
2.7
3.2
VID = +100mV
2.7
3.2
kΩ
LVCMOS/LVTTL Outputs (OUTx)
Output High Voltage
(Table 5)
VOH
Output Low Voltage
VOL
IOL = +4.0mA, VID = -100mV
Output Short-Circuit
3
Current
IOS
VID = 100mV, VOUTx = 0
0.1
V
0.25
15
V
mA
Supply
Supply Current
ICC
AS1153/55/57/58, Inputs open
0.6
2
mA
AS1155/58, |VID| = 200mV
2.5
4.5
mA
AS1153/57, |VID| = 200mV
4.5
8
mA
1. Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced
to ground except VTH, VTL, and VID.
2. 2xRIN = RDIFF
3. Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
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AS1153/55
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
AC Electrical Characteristics
VCC = +3.0 to +3.6V, CLOAD = 10pF, Differential Input Voltage |VID| = 0.2 to 1.0V, Common-Mode Voltage VCM = |VID/2|
to 2.4V -|VID/2|, Input Rise and Fall Time = 1ns (20 to 80%), Input Frequency = 100MHz, TAMB = -40 to +85ºC. Typical
values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TAMB = +25ºC (unless otherwise specified).
Table 4. AC Electrical Characteristics
1, 2
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Differential Propagation Delay Highto-Low
tPHLD
Figure 20 on page 11 and Figure 21 on
page 12
1
1.8
3.1
ns
Differential Propagation Delay Lowto-High
tPLHD
Figure 20 on page 11 and Figure 21 on
page 12
1
1.8
3.1
ns
tSKD1
Figure 20 on page 11 and Figure 21 on
page 12
250
600
ps
Differential Channel-to-Channel
4
Skew
tSKD2
Figure 20 on page 11 and Figure 21 on
page 12
600
ps
5
tSKD3
Figure 20 on page 11 and Figure 21 on
page 12
0.8
ns
6
tSKD4
Figure 20 on page 11 and Figure 21 on
page 12
1.5
ns
Rise Time
tTLH
Figure 20 on page 11 and Figure 21 on
page 12
0.4
1.0
ns
Fall Time
tTHL
Figure 20 on page 11 and Figure 21 on
page 12
0.4
1.0
ns
fMAX
All Channels Switching
Differential Pulse Skew
(tPHLD - tPLHD)
3
Differential Part-to-Part Skew
Differential Part-to-Part Skew
Maximum Operating Frequency
7, 8
130
160
MHz
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
AC parameters are guaranteed by design and characterization.
CL includes scope probe and test jig capacitance.
tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|.
tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same device.
tSKD3 is the magnitude difference of any differential propagation delays between devices operating over rated
conditions at the same VCC and within 5ºC of each other.
tSKD4 is the magnitude difference of any differential propagation delays between devices operating over rated
conditions.
fMAX generator output conditions:
a. Rise time = fall time = 1ns (0 to 100%)
b. 50% duty cycle
c. VOH = +1.3V
d. VOL = +1.1V
Output criteria:
a. Duty cycle = 60% to 40%
b. VOL = 0.4V (max)
c. VOH = 2.7V (min)
d. Load = 10pF
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AS1153/55
Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CLOAD = 10pF, TAMB = +25ºC, unless otherwise noted.
Figure 3. Supply Current vs. Frequency
Figure 4. Supply Current vs. Temperature
20
.
40
Supply Current (mA)
Supply Current (mA)
.
50
All Channels Switching
30
20
One Channel Switching
10
50
100
150
200
250
10
f = 1MHz
5
0
-45 -30 -15
0
0
f = 100MHz
15
300
15 30
45 60
120
30
High to Low
VTH
100
25
80
20
15
60
VTL
Low to High
40
10
20
5
0
3
3.1
3.2
3.3
3.4
3.5
0
3
3.6
3.1
3.2
3.3
3.4
Supply Voltage (V)
Supply Voltage(V)
Figure 7. Output Low Voltage vs. VCC
Figure 8. Output High Voltage vs. VCC
74,5
Output Voltage (V) .
.
3.5
3.6
3.5
3.6
3.2
75
Output Voltage (mV)
75 90
Figure 6. Output Short-Circuit Current vs. VCC
Output Short Circuit Current (mA)
.
.
Figure 5. Diff. Threshold Voltage vs. VCC
Differential Output Voltage (mV)
0
Temperature(°C)
Frequency (MHz)
74
73,5
73
72,5
3.1
3
2.9
2.8
2.7
72
3
3,1
3,2
3,3
3,4
3,5
3
3,6
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3.1
3.2
3.3
3.4
Supply Voltage (V)
Supply Voltage (V)
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AS1153/55
Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 9. Differential Propagation Delay vs. VCC
Figure 10. Differential Propagation Delay vs. Temp.
1.94
.
1.9
Diff. Propagation Delay (ns)
Diff. Propagation Delay (ns)
.
2.05
tPHLD
1.86
1.82
1.78
tPLHD
1.74
1.7
3
3.1
3.2
3.3
3.4
3.5
2
1.95
1.9
tPLHD
1.85
tPHLD
1.8
1.75
-45 -30 -15 0
3.6
Supply Voltage(V)
Figure 11. Differential Propagation Delay vs. VCM
Figure 12. Differential Propagation Delay vs. VID
2.25
.
.
2
1.95
Diff. Propagation Delay (ns)
Diff. Propagation Delay (ns)
15 30 45 60 75 90
Temperature(°C)
1.9
tPHLD
1.85
1.8
1.75
tPLHD
1.7
2
tPHLD
1.75
tPLHD
1.5
1.25
1
0.75
1.65
0
0.5
1
1.5
2
0.1
2.5
0.5
0.9
1.3
1.7
2.1
2.5
Differential-Input Voltage(V)
Common-Mode Voltage(V)
Figure 13. Differential Propagation Delay vs. Load
Diff. Propagation Delay (ns)
.
3
2.5
tPHLD
2
tPLHD
1.5
1
0.5
0
10
15
20
25
30
35
40
45
50
Capacitive Load (pF)
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AS1153/55
Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 14. Differential Pulse Skew vs. VCC
Figure 15. Transition Time vs. Capacitive Load
1600
250
1400
.
Transition Time (ps)
Differential Pulse Skew (ps)
.
300
200
150
100
50
tTHL
1200
800
600
400
0
3
3.1
3.2
3.3
3.4
3.5
10
3.6
Figure 16. Transition Time vs. VCC
20
25
30
35
40
45
50
Figure 17. Transition Time vs. Temperature
475
400
.
390
Transition Time (ps)
.
15
Capacitive Load (pF)
Supply Voltage(V)
Transition Time (ps)
tTLH
1000
380
tTHL
370
tTLH
360
350
450
tTHL
425
tTLH
400
375
350
325
340
3
3.1
3.2
3.3
3.4
3.5
3.6
300
-45 -30 -15 0
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15 30 45 60 75 90
Temperature(°C)
Supply Voltage(V)
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AS1153/55
Data Sheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
The AS1155/58 and AS1153/57 are 260Mbps, single/dual-channel LVDS receivers intended for high-speed, point-topoint, low-power applications. Each independent channel accepts and converts an LVDS input to an LVTTL/LVCMOS
output. The devices are capable of detecting differential signals from 100mV to 1V within an input voltage range of 0 to
2.4V.
The 250 to 450mV differential output of an LVDS driver is nominally centered around 1.25V. Due to the receiver input
voltage range, a ±1V voltage shift in the signal relative to the receiver is allowed. Thus, a difference in ground references of the transmitter and the receiver, as well as the common mode effect of coupled noise, can be tolerated.
LVDS Interface
The LVDS Interface Standard is a signaling method defined for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, resulting in higher data rates, reduced power consumption
and EMI emissions, and less susceptibility to noise.
The devices fully comply with the LVDS standard input voltage range of 0 to +2.4V referenced to receiver ground.
The AS1157/58 has an integrated termination resistors connected internally across each receiver input. This internal
termination saves board space, eases layout, and reduces stub length compared to an external termination resistor. In
other words, the transmission line is terminated on the IC.
Failsafe Circuit
The devices contain an integrated Failsafe circuit to prevent noise at inputs that are open, undriven and terminated, or
undriven and shorted.
Open or undriven terminated input conditions can occur if there is a cable failure or when the LVDS driver outputs are
high impedance. A short condition also can occur because of a cable failure. The Failsafe circuit of the AS1153/55 and
AS1157/58 automatically sets the output high if any of these conditions are true.
The Failsafe input circuit (see Figure 18) samples the input common-mode voltage and compares it to VCC - 0.3V
(nominal). If the input is driven to levels specified in the LVDS standards, the input common-mode voltage is less than
VCC - 0.3V and the Failsafe circuit is not activated. If the inputs are open, undriven and shorted, or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the Failsafe circuit pulls both inputs above VCC
- 0.3V, activating the Failsafe circuit and thus forcing the device output high.
Figure 18. Failsafe Input Circuit
VCC
VCC
RIN2
RIN2
VCC - 0.3V
VCC - 0.3V
INx+
INx+
RIN1
RIN1
RDIFF
OUTx
RIN1
OUTx
RIN1
INx-
INx-
AS1153/55
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AS1157/58
Revision 1.01
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AS1153/55
Data Sheet - A p p l i c a t i o n s
9 Applications
Table 5. Function Table
Input
INx+
Output
INx-
OUTx
VID ≥ +100mV
H
VID ≤ +100mV
L
AS1153/55 – Open, undriven short, or undriven
100Ω parallel termination
H
AS1157/58 – Open or undriven short
Figure 19. Typical Application Circuit
+3.3V
+3.3V
0.001µF
0.001µF
0.1µF
0.1µF
LVDS
Signals
LVTTL/LVCMOS
Data Inputs
Tx
107Ω
Rx
LVTTL/LVCMOS
Data Outputs
AS1158
Single LVDS Receiver
AS1152
100Ω Shielded Twisted Cable or Microstrip PC Board Traces
Power-Supply Bypassing
To bypass VCC, use high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the
device as possible, with the smaller valued capacitor closest to pin VCC.
Differential Traces
Input trace characteristics can adversely affect the performance of the AS1155/58 and AS1153/57.
!
Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor
must also be matched to this characteristic impedance.
!
Eliminate reflections and ensure that noise couples as common mode by running differential traces close together.
!
Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper
data recovery of the devices.
!
Route each channel’s differential signals very close to each other for optimal cancellation of their respective external magnetic fields. Use a constant distance between the differential traces to avoid irregularities in differential
impedance.
!
Avoid 90° turns (use two 45° turns).
!
Minimize the number of vias to further prevent impedance irregularities.
Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables.
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AS1153/55
Data Sheet - A p p l i c a t i o n s
!
Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mismatches.
!
Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
!
Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
Termination
Due to the high data rates of LVDS drivers, matched termination will prevent the generation of any signal reflections,
and reduce EMI.
!
The AS1157/58 has integrated termination resistors connected across the inputs of each receiver. The value of the
integrated resistor is specified in Table 3.
!
The AS1153/55 requires an external termination resistor. The termination resistor should match the differential
impedance of the transmission line and be placed as close to the receiver inputs as possible. Termination resistance values may range between 90 to 132Ω depending on the characteristic impedance of the transmission
medium. Use 1% surface-mount resistors.
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
!
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
!
Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
!
Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent
coupling.
!
Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 20. Propagation Delay and Transition Time Test Circuit
INx+
Pulse
Generator**
OUT
INx50Ω
50Ω
CL
Receiver
AS1153/55, AS1157/58
* 50Ω required for pulse generator.
** When testing the AS1157/58, adjust the pulse generator output to account for internal termination resistor.
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AS1153/55
Data Sheet - A p p l i c a t i o n s
Figure 21. Propagation Delay and Transition Time Waveforms
INxVID
VID = 0
VID = 0
INx+
tPLHD
tPHLD
VOH
VID = (VINx+) - (VINx-)
Note: VCM = (VIN- + VIN+)
2
80
80
50%
50%
20
OUTx
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20
tTLH
tTHL
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AS1153/55
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
10 Package Drawings and Markings
The AS1155/58 and AS1153/57 are available in a 8-pin SOIC package.
Figure 22. 8-pin SOIC Package Diagram
Table 6. 8-pin SOIC Package Dimensions
SOIC - 8LD
Symbol
MILLIMETERS
MIN
MAX
A1
0.10
0.25
B
0.36
D
E
MILLIMETERS
MIN
MAX
h
0.25
0.50
0.48
L
0.41
1.27
4.80
4.98
A
1.52
1.72
3.81
3.99
0º
8º
e
H
Symbol
1.27 BSC
5.80
ZD
6.20
A2
0.53 REF
1.37
1.57
Note:
1. Lead coplanarity should be 0 to 0.10MM max.
2. Package surface finishing:
Top: Matte (Charmilles #18~30)
All Sides: Matte (Charmilles #18~30)
Bottom: Smooth or Matte (Charmilles #18~30)
3. All dimension excluding Mold Flashes and End Flash from the package body shall not exceed 0.25MM per side (D)
4. Details of PIN #1 identifier are optional, but must be located within the zone indicated.
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AS1153/55
Data Sheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
Part Number
AS1155
Marking
AS1155
Description
Single LVDS Receiver
Delivery Form Package Type
Tubes
8-pin SOIC
AS1155-T
AS1155
Single LVDS Receiver
Tape and Reel
8-pin SOIC
AS1158
AS1158
Single LVDS Receiver, with termination
Tubes
8-pin SOIC
AS1158-T
Tape and Reel
8-pin SOIC
AS1158
Single LVDS Receiver, with termination
AS1153
AS1153
Dual LVDS Receiver
Tubes
8-pin SOIC
AS1153-T
AS1153
Dual LVDS Receiver
Tape and Reel
8-pin SOIC
AS1157
AS1157
Dual LVDS Receiver, with termination
Tubes
8-pin SOIC
AS1157-T
AS1157
Dual LVDS Receiver, with termination
Tape and Reel
8-pin SOIC
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Revision 1.01
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AS1153/55
Data Sheet
Copyrights
Copyright © 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information.
This product is intended for use in normal commercial applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for
each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
www.austriamicrosystems.com
Revision 1.01
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