Cypress CY7C1049DV33-10VXI 4-mbit (512k x 8) static ram Datasheet

CY7C1049DV33
4-Mbit (512K x 8) Static RAM
Functional Description[1]
Features
• Pin- and function-compatible with CY7C1049CV33
The CY7C1049DV33 is a high-performance CMOS Static
RAM organized as 512K words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. Writing
to the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A18).
• High speed
— tAA = 10 ns
• Low active power
— ICC = 90 mA @ 10 ns (Industrial)
• Low CMOS standby power
— ISB2 = 10 mA
• 2.0V data retention
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
• Available in Lead-Free 36-lead (400-mil) Molded SOJ
V36 and 44-pin TSOP II ZS44 packages
The CY7C1049DV33 is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
Pin Configuration
Logic Block Diagram
TSOP II
Top View
SOJ
Top View
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
I/O0
INPUTBUFFER
I/O1
CE
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
512K x 8
I/O3
I/O4
I/O5
COLUMN
DECODER
POWER
DOWN
I/O7
A 11
A 12
A 13
A 14
A 15
A 16
A17
A18
WE
OE
I/O6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
VSS
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
Selection Guide
-10 (Industrial)
10
90
10
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
-12 (Automotive)[2]
12
95
15
Unit
ns
mA
mA
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. Automotive product information is Preliminary.
Cypress Semiconductor Corporation
Document #: 38-05475 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 3, 2006
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CY7C1049DV33
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............. ...............................>2001V
(Above which the useful life may be impaired. For user guidelines, not tested.)
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Ambient
Temperature
VCC
Speed
Industrial
–40°C to +85°C
3.3V ± 0.3V
10 ns
Automotive
–40°C to +125°C
3.3V ± 0.3V
12 ns
Supply Voltage on VCC to Relative GND[3] .... –0.3V to +4.6V
Range
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.3V to VCC + 0.3V
DC Input Voltage[3] .................................–0.3V to VCC + 0.3V
Electrical Characteristics Over the Operating Range
-10 (Industrial)
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH[3]
VIL[3]
Input HIGH Voltage
IIX
Input Leakage Current
GND < VI < VCC
IOZ
Output Leakage
Current
GND < VOUT < VCC,
Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX
= 1/tRC
Input LOW
Min.
Max.
-12 (Automotive)
Min.
Max.
2.4
2.4
V
0.4
Voltage[3]
Unit
0.4
V
V
2.0
VCC + 0.3
2.0
VCC + 0.3
–0.3
0.8
–0.3
0.8
V
–1
+1
–1
+1
µA
–1
+1
–1
+1
µA
100MHz
90
-
mA
83MHz
80
95
mA
66MHz
70
85
mA
40MHz
60
75
mA
ISB1
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH;
VIN > VIH or
VIN < VIL, f = fMAX
20
25
mA
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10
15
mA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz,
VCC = 3.3V
8
pF
8
pF
Thermal Resistance[4]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)[4]
ΘJC
Thermal Resistance
(Junction to Case)[4]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
SOJ
Package
TSOP II
Package
Unit
57.91
50.66
°C/W
36.73
17.17
°C/W
Notes:
3. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05475 Rev. *C
Page 2 of 8
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CY7C1049DV33
AC Test Loads and Waveforms[5]
10 ns device
Z = 50Ω
ALL INPUT PULSES
3.0V
90%
OUTPUT
50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
90%
10%
10%
GND
1.5V
(b)
Rise Time: 1 V/ns
(a)
High-Z characteristics:
Fall Time: 1 V/ns
R 317Ω
3.3V
OUTPUT
R2
351Ω
5 pF
(c)
AC Switching
Characteristics[6]
Over the Operating Range
-10 (Industrial)
Parameter
Description
Min.
Max.
-12 (Automotive)
Min.
Max.
Unit
Read Cycle
tpower[7]
VCC(typical) to the first access
100
100
µs
tRC
Read Cycle Time
10
12
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to
High-Z[8, 9]
Low-Z[9]
tLZCE
CE LOW to
tHZCE
CE HIGH to High-Z[8, 9]
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
10
3
12
3
10
5
0
ns
12
ns
6
ns
0
5
3
ns
6
ns
6
ns
12
ns
3
5
0
ns
0
10
ns
ns
Write Cycle[10, 11]
tWC
Write Cycle Time
10
12
ns
tSCE
CE LOW to Write End
7
8
ns
tAW
Address Set-up to Write End
7
8
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
7
8
ns
tSD
Data Set-up to Write End
5
6
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low-Z[9]
3
3
ns
tHZWE
WE LOW to
High-Z[8, 9]
5
6
ns
Notes:
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05475 Rev. *C
Page 3 of 8
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CY7C1049DV33
Data Retention Characteristics Over the Operating Range
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
tR
[4]
Conditions [13]
Description
Min.
2.0
Unit
V
VCC = VDR = 2.0V, CE > VCC – 0.3V
Ind’l
10
mA
VIN > VCC – 0.3V or VIN < 0.3V
Auto
15
mA
Chip Deselect to Data Retention Time
[12]
Max
Operation Recovery Time
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
3.0V
VDR > 2V
tCDR
tR
CE
Switching Waveforms
Read Cycle No. 1[14, 15]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tHZCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
ICC
50%
ISB
Notes:
12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs
13. No input may exceed VCC + 0.3V.
14. Device is continuously selected. OE, CE = VIL.
15. WE is HIGH for Read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05475 Rev. *C
Page 4 of 8
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CY7C1049DV33
Switching Waveforms(continued)
Write Cycle No. 1 (WE Controlled, OE HIGH During Write)[17, 18]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 19
tHZOE
Write Cycle No. 2 (WE Controlled, OE LOW)[18]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 19
tHD
DATA VALID
tHZWE
tLZWE
Notes:
17. Data I/O is high-impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
19. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05475 Rev. *C
Page 5 of 8
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CY7C1049DV33
Switching Waveforms(continued)
Write Cycle No. 3 (CE Controlled)[17, 18]
tWC
ADDRESS
tSCE
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Truth Table
CE
H
OE
X
WE
X
I/O0–I/O7
Mode
Power
High-Z
Power-down
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
12
Ordering Code
CY7C1049DV33-10VXI
Package
Name
51-85090
Package Type
36-lead (400-Mil) Molded SOJ (Pb-Free)
CY7C1049DV33-10ZSXI
51-85087
44-pin TSOP II (Pb-Free)
CY7C1049DV33-12VXE
51-85090
36-lead (400-Mil) Molded SOJ (Pb-Free)
CY7C1049DV33-12ZSXE
51-85087
44-pin TSOP II (Pb-Free)
Operating
Range
Industrial
Automotive
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05475 Rev. *C
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CY7C1049DV33
Package Diagrams
36-lead (400-mil) Molded SOJ (51-85090)
51-85090-*B
44-pin TSOP II (51-85087)
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05475 Rev. *C
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1049DV33
Document History Page
Document Title: CY7C1049DV33 4-Mbit (512K x 8) Static RAM
Document Number: 38-05475
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
201560
See ECN
SWI
Advance Data sheet for C9 IPP
*A
233729
See ECN
SYT
1.AC, DC parameters are modified as per EROS(Spec # 01-2165)
2.Pb-free offering in the ‘ordering information’
*B
351096
See ECN
PCI
Changed from Advance to Preliminary
Removed 20 ns Speed bin
Corrected DC voltage (min) value in maximum ratings section from - 0.5 to
- 0.3V
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 100, 80 and 67 mA to 90, 80 and 75 mA for 8, 10
and 12ns speed bins respectively
ICC (Ind’l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns
speed bins respectively
Added VIH(max) spec in Note# 2
Changed reference voltage level for measurement of Hi-Z parameters from
±500 mV to ±200 mV
Added Data Retention Characteristics/Waveform and footnotes 11 and 12
Changed Package Diagram name from 44-pin TSOP II Z44 to 44-pin TSOP
II ZS44
Changed part names from Z to ZS in the Ordering Information Table
Added 8 ns parts in the Ordering Information Table
Added Lead-Free Ordering Information
Shaded Ordering Information Table
*C
446328
See ECN
NXR
Converted from Preliminary to Final
Removed -8 speed bin
Removed Commercial Operating Range product information
Added Automotive Operating Range product information
Updated Thermal Resistance table
Updated footnote #8 on High-Z parameter measurement
Replaced Package Name column with Package Diagram in the Ordering
Information table
Document #: 38-05475 Rev. *C
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