AD AD9613BCPZRL7-210 12-bit, 170 msps/210 msps/250 msps, 1.8 v dual analog-to-digital converter (adc) Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS
SFDR = 86 dBc at 185 MHz fIN and 250 MSPS
−149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and
250 MSPS
Total power consumption: 770 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
Energy-saving power-down modes
AVDD
VIN+A
PIPELINE
12-BIT
ADC
VIN–A
VCM
12
AD9613
VIN+B
PIPELINE
12-BIT
ADC
VIN–B
DRVDD
AGND
12
D0±
PARALLEL
DDR LVDS
AND
DRIVERS
.
.
.
.
.
D11±
DCO±
REFERENCE
OR±
1 TO 8
CLOCK
DIVIDER
SERIAL PORT
OEB
PDWN
CLK+
CLK– SYNC
CSB
SCLK SDIO
NOTES
1. THE D0± TO D11± PINS REPRESENT BOTH THE CHANNEL A
AND CHANNEL B LVDS OUTPUT DATA.
09637-001
Data Sheet
12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Dual Analog-to-Digital Converter (ADC)
AD9613
Figure 1.
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The AD9613 is a dual 12-bit, analog-to-digital converter (ADC)
with sampling speeds of up to 250 MSPS. The AD9613 is designed
to support communications applications where low cost, small
size, wide bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of userselectable input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer (DCS) is provided to
compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
The ADC output data is routed directly to the two external 12-bit
LVDS output ports and formatted as either interleaved or channel
multiplexed.
Flexible power-down options allow significant power savings,
when desired.
Rev. D
Programming for setup and control is accomplished using a
3-wire SPI-compatible serial interface.
The AD9613 is available in a 64-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.
2. Fast overrange and threshold detect.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
4. SYNC input allows synchronization of multiple devices.
5. 3-pin, 1.8 V SPI port for register programming and register
readback.
6. Pin compatibility with the AD9643, allowing a simple
migration up to 14 bits, and with the AD6649 and the AD6643.
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Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved.
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AD9613* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
DOCUMENTATION
View a parametric search of comparable parts.
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
EVALUATION KITS
• AN-282: Fundamentals of Sampled Data Systems
• AD9613 Evaluation Board
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AD9643 Evaluation Board
• AN-501: Aperture Uncertainty and ADC System
Performance
• AN-586: LVDS Outputs for High Speed A/D Converters
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-742: Frequency Domain Response of SwitchedCapacitor ADCs
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
• AD9613: 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual
Analog-to-Digital Converter (ADC) Data Sheet
Technical Books
• The Data Conversion Handbook, 2005
User Guides
• UG-293: Evaluating the AD9643/AD9613/AD6649/AD6643
Analog-to-Digital Converters
TOOLS AND SIMULATIONS
• Visual Analog
• AD9613 IBIS Model
REFERENCE MATERIALS
DESIGN RESOURCES
Product Selection Guide
• AD9613 Material Declaration
• RF Source Booklet
• PCN-PDN Information
Technical Articles
• Quality And Reliability
• MS-1779: Nine Often Overlooked ADC Specifications
• Symbols and Footprints
• MS-2210: Designing Power Supplies for High Speed ADC
Tutorials
DISCUSSIONS
• MT-001: Taking the Mystery out of the Infamous Formula,
"SNR=6.02N + 1.76dB", and Why You Should Care
View all AD9613 EngineerZone Discussions.
• MT-002: What the Nyquist Criterion Means to Your
Sampled Data System Design
SAMPLE AND BUY
• MT-031: Grounding Data Converters and Solving the
Mystery of "AGND" and "DGND"
• MT-075: Differential Drivers for High Speed ADCs
Overview
Visit the product page to see pricing options.
TECHNICAL SUPPORT
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number.
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AD9613
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Input Considerations ................................................... 23
Applications ....................................................................................... 1
Voltage Reference ....................................................................... 25
General Description ......................................................................... 1
Clock Input Considerations ...................................................... 25
Functional Block Diagram .............................................................. 1
Power Dissipation and Standby Mode .................................... 27
Product Highlights ........................................................................... 1
Digital Outputs ........................................................................... 27
Revision History ............................................................................... 2
ADC Overrange (OR)................................................................ 27
Specifications..................................................................................... 3
Channel/Chip Synchronization .................................................... 28
ADC DC Specifications ............................................................... 3
Serial Port Interface (SPI) .............................................................. 29
ADC AC Specifications ............................................................... 4
Configuration Using the SPI ..................................................... 29
Digital Specifications ................................................................... 6
Hardware Interface ..................................................................... 29
Switching Specifications .............................................................. 8
SPI Accessible Features .............................................................. 30
Timing Specifications .................................................................. 9
Memory Map .................................................................................. 31
Absolute Maximum Ratings .......................................................... 11
Reading the Memory Map Register Table............................... 31
Thermal Characteristics ............................................................ 11
Memory Map Register Table ..................................................... 32
ESD Caution ................................................................................ 11
Memory Map Register Description ......................................... 34
Pin Configurations and Function Descriptions ......................... 12
Applications Information .............................................................. 35
Typical Performance Characteristics ........................................... 16
Design Guidelines ...................................................................... 35
Equivalent Circuits ......................................................................... 22
Outline Dimensions ....................................................................... 36
Theory of Operation ...................................................................... 23
Ordering Guide .......................................................................... 36
ADC Architecture ...................................................................... 23
REVISION HISTORY
2/2017—Rev. C to Rev. D
Changes to Table 9 .......................................................................... 14
1/2013—Rev. B to Rev. C
Changes to Features.......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ........................................................................... 5
Change to Logic Inputs (SDIO) Paramter, Table 3....................... 6
Changes to Table 4 ............................................................................ 8
Change to Reading the Memory Map Register Table Section ....... 31
Changes to Table 14 ........................................................................ 33
Change to Memory Map Register Description Section............. 34
Updated Outline Dimensions ....................................................... 36
9/2011—Rev. A to Rev. B
Changes to Figure 1 .......................................................................... 1
Changes to Temperature Drift Parameters ................................... 3
Changes Output Offset Voltage (VOS), ANSI Mode Typ
Parameter and Output Offset Voltage (VOS), Reduced Swing
Mode Parameter................................................................................ 7
Changes DCO to Data Skew (tSKEW) Parameters .......................... 8
Changes to Output Enable Bar and Power-Down Pin Type
and Pin 47 Description .................................................................. 13
Changes to Figure 5 and Pin 7 and Pin 8 Descriptions ............. 14
Changes to Pin 42 and Pin 43, Output Enable Bar and PowerDown Pin Type, and Pin 47 Descriptions ................................... 15
Changes to Typical Performance Characteristics Conditions .. 16
Changes to Fiugre 43 ...................................................................... 22
Added ADC Overrange (OR) Section ......................................... 27
Changes to Channel/Chip Synchronization Section ................. 28
Changes to Reading the Memory Map Register Table
Section and Transfer Register Map Section ................................ 31
Changes to Register 0x02, Bits[5:4].............................................. 32
Changes to Register 0x16, Bit 5 .................................................... 33
Added Register 0x3A ..................................................................... 34
Deleted Register 0x59 .................................................................... 34
Changes to Bit 0—Master Sync Buffer Enable Section ............. 34
Deleted SYNC Pin Control (Register 0x59) Section.................. 34
5/2011—Rev. 0 to Rev. A
Changes to Table 2, AD9613-170: Worst Second or Third
Harmonic and Worst Other (Harmonic or Spur) Max Values
and Spurious Free Dynamic Range Min Value .............................4
4/2011—Revision 0: Initial Version
Rev. D | Page 2 of 36
Data Sheet
AD9613
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range, DCS enabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL) 1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT-REFERRED NOISE
VREF = 1.75 V
ANALOG INPUT
Input Span
Input Capacitance 2
Input Resistance 3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1
POWER CONSUMPTION
Sine Wave Input1 (DRVDD = 1.8 V)
Standby Power 4
Power-Down Power
Temp
Full
Min
12
Full
Full
Full
Full
25°C
Full
25°C
AD9613-170
Typ
Max
Min
12
Guaranteed
±10
+2/−6
±0.5
±0.25
±0.5
±0.20
Full
Full
AD9613-210
Typ
Max
Min
12
Guaranteed
±10
+3/−5
±0.5
±0.25
±0.6
±0.25
±13
±2.5
AD9613-250
Typ
Max
Guaranteed
±10
±4
±0.5
±0.25
±0.8
±0.28
±13
+3.5/−2
±13
+3.5/−2.5
Unit
Bits
mV
%FSR
LSB
LSB
LSB
LSB
mV
%FSR
Full
Full
±5
±70
±5
±80
±5
±100
ppm/°C
ppm/°C
25°C
0.39
0.39
0.39
LSB rms
Full
Full
Full
Full
1.75
2.5
20
0.9
1.75
2.5
20
0.9
1.75
2.5
20
0.9
V p-p
pF
kΩ
V
Full
Full
1.7
1.7
1.8
1.8
1.9
1.9
Full
Full
230
142
Full
Full
Full
670
90
10
1.7
1.7
1.8
1.8
1.9
1.9
250
160
241
159
738
720
90
10
1.8
1.8
1.9
1.9
V
V
265
185
252
176
275
210
mA
mA
810
770
90
10
873
mW
mW
mW
Measured with a low input frequency, full-scale sine wave.
Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3
Input resistance refers to the effective resistance between one differential input pin and its complement.
4
Standby power is measured with a dc input and the CLK± pin inactive (that is, set to AVDD or AGND).
1
2
Rev. D | Page 3 of 36
1.7
1.7
AD9613
Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range, unless
otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
AD9613-170
Min
Typ
Max
AD9613-210
Min
Typ
Max
AD9613-250
Min
Typ
Max
70.1
70.0
70.1
70.0
70.0
69.8
69.8
69.5
69.8
69.5
69.6
69.2
69.4
69.3
69.0
69.1
69.0
69.1
69.0
69.0
68.8
68.8
68.5
68.8
68.5
68.6
68.2
68.4
68.3
68.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
25°C
11.2
11.2
11.1
11.1
11.1
11.2
11.2
11.1
11.1
11.0
11.2
11.1
11.1
11.0
11.0
Bits
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
Full
25°C
−94
−92
−94
−94
−90
−89
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
Full
25°C
Temp
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
69.3
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
69.2
67.8
68.2
68
66.5
−78
−80
−87
−89
−88
−83
−86
−86
−80
−83
−85
94
92
90
90
92
89
87
89
88
83
86
86
83
83
85
−97
−96
−95
−95
−93
−92
−80
78
dBc
dBc
dBc
dBc
dBc
dBc
dBc
80
80
−78
−80
−97
−91
−97
−96
−91
−91
−93
−94
−89
−80
Rev. D | Page 4 of 36
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Data Sheet
Parameter 1
TWO-TONE SFDR
fIN = 184.12 MHz (−7 dBFS),
187.12 MHz (−7 dBFS)
CROSSTALK 2
FULL POWER BANDWIDTH 3
1
2
3
AD9613
Temp
AD9613-170
Min
Typ
Max
AD9613-210
Min
Typ
Max
AD9613-250
Min
Typ
Max
Unit
25°C
88
88
88
dBc
Full
95
1000
95
1000
95
1000
dB
25°C
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved.
Rev. D | Page 5 of 36
MHz
AD9613
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled,
unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Temp
Min
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS/LVPECL
0.9
0.3
3.6
AGND
AVDD
0.9
1.4
10
22
−22
−10
4
8
10
12
Full
Full
Full
Full
Full
Full
Full
Full
Rev. D | Page 6 of 36
Typ
Max
CMOS/LVDS
0.9
AGND
1.2
AGND
−5
−5
12
Full
Full
Full
Full
Full
Full
1.22
0
−5
−80
Full
Full
Full
Full
Full
Full
1.22
0
45
−5
Full
Full
Full
Full
Full
Full
1.22
0
45
−5
AVDD
AVDD
0.6
+5
+5
1
16
20
V
V p-p
V
V
µA
µA
pF
kΩ
V
V
V
V
µA
µA
pF
kΩ
2.1
0.6
+5
+45
V
V
µA
µA
kΩ
pF
2.1
0.6
70
+5
V
V
µA
µA
kΩ
pF
2.1
0.6
70
+5
V
V
µA
µA
kΩ
pF
26
2
26
2
26
5
Unit
Data Sheet
AD9613
Parameter
LOGIC INPUTS (OEB, PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
LVDS Data and OR Outputs
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS), Reduced Swing Mode
1
2
Pull up.
Pull down.
Rev. D | Page 7 of 36
Temp
Min
Full
Full
Full
Full
Full
Full
1.22
0
45
−5
Full
Full
Full
Full
250
1.15
150
1.15
Typ
Max
Unit
2.1
0.6
70
+5
V
V
µA
µA
kΩ
pF
450
1.35
280
1.35
mV
V
mV
V
26
5
350
1.22
200
1.22
AD9613
Data Sheet
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate 1
CLK Period, Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-by-8 Mode
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
LVDS Mode
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time (from Standby)
Wake-Up Time (from Power Down)
Out-of-Range Recovery Time
1
Temp
AD9613-170
Min Typ Max
Full
Full
Full
40
5.8
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
2.61
2.76
0.8
0.4
625
170
2.9
2.9
3.19
3.05
AD9613-210
Min
Typ Max
625
210
40
4.8
6.0
6.7
0.7
10
1.0
0.1
10
250
6.0
6.7
0.7
10
1.0
0.1
10
250
3
6.0
6.7
0.7
10
1.0
0.1
10
250
3
ns
ns
ns
Cycles
ns
ps rms
µs
µs
Cycles
Conversion rate is the clock rate after the divider.
Rev. D | Page 8 of 36
0.4
2.0
2.0
2.2
2.1
1.0
0.1
1.0
1.8
1.9
0.8
MHz
MSPS
ns
1.0
0.1
3
2.64
2.52
625
250
1.0
0.1
0.4
2.4
2.4
40
4
Unit
ns
ns
ns
ns
ps rms
1.0
2.16
2.28
0.8
AD9613-250
Min Typ Max
1.0
Data Sheet
AD9613
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Test Conditions/Comments
See Figure 3 for timing details
SYNC to the rising edge of CLK setup time
SYNC to the rising edge of CLK hold time
See Figure 58 for SPI timing diagram
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge (not shown in Figure 58)
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge (not shown in Figure 58)
Rev. D | Page 9 of 36
Min
Typ
0.3
0.4
Max
Unit
ns
ns
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
AD9613
Data Sheet
Timing Diagrams
tA
N–1
N+4
N+5
N
N+3
VIN
N+1
tCH
N+2
tCLK
CLK+
CLK–
tDCO
DCO–
DCO+
tSKEW
PARALLEL INTERLEAVED
D0±
(LSB)
CH A
N – 10
CH B
N – 10
CH A
N–9
CH B
N–9
CH A
N–8
CH B
N–8
CH A
N–7
CH B
N–7
CH A
N–6
D11±
(MSB)
CH A
N – 10
CH B
N – 10
CH A
N–9
CH B
N–9
CH A
N–8
CH B
N–8
CH A
N–7
CH B
N–7
CH A
N–6
D0±/D1±
(LSB)
CH A0
N – 10
CH A1
N – 10
CH A0
N–9
CH A1
N–9
CH A0
N–8
CH A1
N–8
CH A0
N–7
CH A1
N–7
CH A0
N–6
CH A10
N – 10
CH A11
N – 10
CH A10
N–9
CH A11
N–9
CH A10
N–8
CH A11
N–8
CH A10
N–7
CH A11
N–7
CH A10
N–6
CH B0
N – 10
CH B1
N – 10
CH B0
N–9
CH B1
N–9
CH B0
N–8
CH B1
N–8
CH B0
N–7
CH B1
N–7
CH B0
N–6
CH B10
N – 10
CH B11
N – 10
CH B10
N–9
CH B11
N–9
CH B10
N–8
CH B11
N–8
CH B10
N–7
CH B11
N–7
CH B10
N–6
CHANNEL A AND
CHANNEL B
CHANNEL MULTIPLEXED
(EVEN/ODD) MODE
CHANNEL A
.
.
.
.
.
.
D10±/D11±
(MSB)
CHANNEL MULTIPLEXED
(EVEN/ODD) MODE
D0±/D1±
(LSB)
CHANNEL B
.
.
.
D10±/D11±
(MSB)
Figure 2. Interleaved LVDS Mode Data Output Timing
CLK+
tHSYNC
09637-003
tSSYNC
SYNC
Figure 3. SYNC Timing Inputs
Rev. D | Page 10 of 36
09637-002
tPD
Data Sheet
AD9613
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VCM to AGND
CSB to AGND
SCLK to AGND
SDIO to AGND
OEB to AGND
PDWN to AGND
OR+/OR− to AGND
D0−/D0+ Through D11−/D11+ to
AGND
DCO+/DCO− to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
printed circuit board (PCB) increases the reliability of the
solder joints, maximizing the thermal capability of the package.
Typical θJA is specified for a 4-layer PCB with solid ground
plane. As shown in Figure 40, airflow increases heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes reduces the θJA.
Table 7. Thermal Resistance
Package Type
64-Lead LFCSP
9 mm × 9 mm
(CP-64-4)
Airflow
Velocity
(m/sec)
0
1.0
2.0
θJA1, 2
26.8
21.6
20.2
θJC1, 3
1.14
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
1
−40°C to +85°C
2
150°C
−65°C to +125°C
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. D | Page 11 of 36
θJB1, 4
10.4
Unit
°C/W
°C/W
°C/W
AD9613
Data Sheet
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
AVDD
VIN+B
VIN–B
AVDD
AVDD
DNC
VCM
DNC
DNC
AVDD
AVDD
VIN–A
VIN+A
AVDD
AVDD
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AD9613
PARALLEL LVDS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK
SDIO
OR+
OR–
D11+ (MSB)
D11– (MSB)
D10+
D10–
DRVDD
D9+
D9–
D8+
D8–
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE
MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
09637-004
D2–
D2+
DRVDD
D3–
D3+
D4–
D4+
DCO–
DCO+
D5–
D5+
DRVDD
D6–
D6+
D7–
D7+
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLK+
CLK–
SYNC
DNC
DNC
DNC
DNC
DNC
DNC
DRVDD
DNC
DNC
D0– (LSB)
D0+ (LSB)
D1–
D1+
Figure 4. Pin Configuration (Top View) for the LFCSP Interleaved Parallel LVDS Mode
Table 8. Pin Function Descriptions for the LFCSP Interleaved Parallel LVDS Mode
Pin No.
ADC Power Supplies
0
Mnemonic
Type
Description
AGND,
Exposed Paddle
Ground
4 to 9, 11, 12, 55, 56, 58
10, 19, 28, 37
49, 50, 53, 54, 59, 60, 63, 64
ADC Analog
1
2
51
52
57
DNC
DRVDD
AVDD
Supply
Supply
Analog Ground. The exposed thermal paddle on the bottom of the
package provides the analog ground for the part. This exposed paddle
must be connected to ground for proper operation.
Do not connect. Do not connect to these pins.
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
CLK+
CLK−
VIN+A
VIN−A
VCM
Input
Input
Input
Input
Output
61
62
Digital Input
3
VIN−B
VIN+B
Input
Input
ADC Clock Input—True.
ADC Clock Input—Complement.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Common-Mode Level Bias Output for Analog Inputs. This pin should
be decoupled to ground using a 0.1 µF capacitor.
Differential Analog Input Pin (−) for Channel B.
Differential Analog Input Pin (+) for Channel B.
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Rev. D | Page 12 of 36
Data Sheet
Pin No.
Digital Outputs
14
13
16
15
18
17
21
20
23
22
27
26
30
29
32
31
34
33
36
35
39
38
41
40
43
42
25
24
SPI Control
45
44
46
Output Enable Bar and
Power-Down
47
48
AD9613
Mnemonic
Type
Description
D0+ (LSB)
D0− (LSB)
D1+
D1−
D2+
D2−
D3+
D3−
D4+
D4−
D5+
D5−
D6+
D6−
D7+
D7−
D8+
D8−
D9+
D9−
D10+
D10−
D11+ (MSB)
D11− (MSB)
OR+
OR−
DCO+
DCO−
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0—True.
Channel A/Channel B LVDS Output Data 0—Complement.
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3—True.
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
Channel A/Channel B LVDS Output Data 4—Complement.
Channel A/Channel B LVDS Output Data 5—True.
Channel A/Channel B LVDS Output Data 5—Complement.
Channel A/Channel B LVDS Output Data 6—True.
Channel A/Channel B LVDS Output Data 6—Complement.
Channel A/Channel B LVDS Output Data 7—True.
Channel A/Channel B LVDS Output Data 7—Complement.
Channel A/Channel B LVDS Output Data 8—True.
Channel A/Channel B LVDS Output Data 8—Complement.
Channel A/Channel B LVDS Output Data 9—True.
Channel A/Channel B LVDS Output Data 9—Complement.
Channel A/Channel B LVDS Output Data 10—True.
Channel A/Channel B LVDS Output Data 10—Complement.
Channel A/Channel B LVDS Output Data 11—True.
Channel A/Channel B LVDS Output Data 11—Complement.
Channel A/Channel B LVDS Overrange—True.
Channel A/Channel B LVDS Overrange—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
SCLK
SDIO
CSB
Input
Input/Output
Input
SPI Serial Clock.
SPI Serial Data I/O.
SPI Chip Select (Active Low).
OEB
PDWN
Input/Output
Input/Output
Output Enable Bar Input (Active Low).
Power-Down Input (Active High). Operation depends upon SPI mode;
this input can be configured as power-down or standby. For further
description, refer to Table 14.
Rev. D | Page 13 of 36
Data Sheet
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
AVDD
VIN+B
VIN–B
AVDD
AVDD
DNC
VCM
DNC
DNC
AVDD
AVDD
VIN–A
VIN+A
AVDD
AVDD
AD9613
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AD9613
CHANNEL
MULTIPLEXED
(EVEN/ODD)
LVDS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK
SDIO
ORA+
ORA–
A D10+/D11+ (MSB)
A D10–/D11– (MSB)
A D8+/D9+
A D8–/D9–
DRVDD
A D6+/D7+
A D6–/D7–
A D4+/D5+
A D4–/D5–
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE
ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
09637-005
B D6–/D7–
B D6+/D7+
DRVDD
B D8–/D9–
B D8+/D9+
B D10–/D11– (MSB)
B D10+/D11+ (MSB)
DCO–
DCO+
DNC
DNC
DRVDD
A D0–/D1– (LSB)
A D0+/D1+ (LSB)
A D2–/D3–
A D2+/D3+
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLK+
CLK–
SYNC
DNC
DNC
ORB–
ORB+
DNC
DNC
DRVDD
B D0–/D1– (LSB)
B D0+/D1+ (LSB)
B D2–/D3–
B D2+/D3+
B D4–/D5–
B D4+/D5+
Figure 5. Pin Configuration (Top View) for the LFCSP Channel Multiplexed (Even/Odd) LVDS Mode
Table 9. Pin Function Descriptions for the LFCSP Channel Multiplexed (Even/Odd) LVDS Mode
Pin No.
ADC Power Supplies
10, 19, 28, 37
49, 50, 53, 54, 59, 60, 63, 64
4, 5, 8, 9, 26, 27, 55, 56, 58
0
ADC Analog
51
52
62
61
57
1
2
Digital Input
3
Digital Outputs
7
6
Mnemonic
Type
Description
DRVDD
AVDD
DNC
AGND, Exposed
Paddle
Supply
Supply
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Do Not Connect. Do not connect to these pins.
The exposed thermal paddle on the bottom of the package provides
the analog ground for the part. This exposed paddle must be connected
to ground for proper operation.
VIN+A
VIN−A
VIN+B
VIN−B
VCM
Input
Input
Input
Input
Output
CLK+
CLK−
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Common-Mode Level Bias Output for Analog Inputs. This pin should be
decoupled to ground using a 0.1 µF capacitor.
ADC Clock Input—True.
ADC Clock Input—Complement.
SYNC
Input
Digital Synchronization Pin. Slave mode only.
ORB+
Output
ORB−
Output
Channel B LVDS Overrange Output—True. The overrange indication is
valid on the rising edge of the DCO.
Channel B LVDS Overrange Output—Complement. The overrange
indication is valid on the rising edge of the DCO.
Ground
Rev. D | Page 14 of 36
Data Sheet
Pin No.
11
12
13
14
15
16
17
18
20
21
22
23
29
30
31
32
33
34
35
36
38
39
40
41
43
42
25
24
SPI Control
45
44
46
Output Enable Bar and
Power-Down
47
48
AD9613
Mnemonic
B D0−/D1− (LSB)
B D0+/D1+ (LSB)
B D2−/D3−
B D2+/D3+
B D4−/D5−
B D4+/D5+
B D6−/D7−
B D6+/D7+
B D8−/D9−
B D8+/D9+
B D10−/D11−
B D10+/D11+
A D0−/D1− (LSB)
A D0+/D1+ (LSB)
A D2−/D3−
A D2+/D3+
A D4−/D5−
A D4+/D5+
A D6−/D7−
A D6+/D7+
A D8−/D9−
A D8+/D9+
A D10−/D11−
A D10+/D11+
ORA+
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
ORA−
Output
DCO+
DCO−
Output
Output
Description
Channel B LVDS Output Data 1/Data 0—Complement.
Channel B LVDS Output Data 1/Data 0—True.
Channel B LVDS Output Data 3/Data 2—Complement.
Channel B LVDS Output Data 3/Data 2—True.
Channel B LVDS Output Data 5/Data 4—Complement.
Channel B LVDS Output Data 5/Data 4—True.
Channel B LVDS Output Data 7/Data 6—Complement.
Channel B LVDS Output Data 7/Data 6—True.
Channel B LVDS Output Data 9/Data 8—Complement.
Channel B LVDS Output Data 9/Data 8—True.
Channel B LVDS Output Data 11/Data 10—Complement.
Channel B LVDS Output Data 11/Data 10—True.
Channel A LVDS Output Data 1/Data 0—Complement.
Channel A LVDS Output Data 1/Data 0—True.
Channel A LVDS Output Data 3/Data 2—Complement.
Channel A LVDS Output Data 3/Data 2—True.
Channel A LVDS Output Data 5/Data 4—Complement.
Channel A LVDS Output Data 5/Data 4—True.
Channel A LVDS Output Data 7/Data 6—Complement.
Channel A LVDS Output Data 7/Data 6—True.
Channel A LVDS Output Data 9/Data 8—Complement.
Channel A LVDS Output Data 9/Data 8—True.
Channel A LVDS Output Data 11/Data 10—Complement.
Channel A LVDS Output Data 11/Data 10—True.
Channel A LVDS Overrange Output—True. The overrange indication is
valid on the rising edge of the DCO.
Channel A LVDS Overrange Output—Complement. The overrange
indication is valid on the rising edge of the DCO.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
SCLK
SDIO
CSB
Input
Input/Output
Input
SPI Serial Clock.
SPI Serial Data I/O.
SPI Chip Select (Active Low).
OEB
PDWN
Input
Input
Output Enable Bar Input (Active Low).
Power-Down Input (Active High). Operation depends upon SPI mode;
this input can be configured as power-down or standby. For further
description, refer to Table 14.
Rev. D | Page 15 of 36
AD9613
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN =
−1.0 dBFS, 32k sample, TA = 25°C, unless otherwise noted.
120
0
170MSPS
90.1MHz @ –1dBFS
SNR = 69.7dB (70.7dBFS)
SFDR = 88dBc
SFDR (dBFS)
100
SNR/SFDR (dBc AND dBFS)
–20
–60
SECOND HARMONIC
THIRD HARMONIC
–80
–100
80
60
SFDR (dBc)
40
SNR (dBc)
0
10
20
40
50
60
30
FREQUENCY (MHz)
70
80
0
–100
09637-013
–140
Figure 6. AD9613-170 Single-Tone FFT with fIN = 90.1 MHz
–80
–70 –60 –50 –40 –30
INPUT AMPLITUDE (dBFS)
–20
–10
0
Figure 9. AD9613-170 Single-Tone SNR/SFDR vs.
Input Amplitude (AIN) with fIN = 90.1 MHz
0
100
170MSPS
185.1MHz @ –1dBFS
SNR = 68.9dB (69.9dBFS)
SFDR = 80dBc
SFDR (dBc)
95
SNR/SFDR (dBc AND dBFS)
–20
–40
–60
THIRD HARMONIC
–80
–100
–120
90
85
80
75
SNR (dBFS)
70
65
0
10
20
30
40
50
60
FREQUENCY (MHz)
70
80
60
60
09637-014
–140
Figure 7. AD9613-170 Single-Tone FFT with fIN = 185.1 MHz
90
120 150
180 210 240 270 300
FREQUENCY (MHz)
330 360 390
09637-017
AMPLITUDE (dBFS)
–90
09637-016
20
–120
Figure 10. AD9613-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
0
0
170MSPS
305.1MHz @ –1dBFS
SNR = 67dB (68dBFS)
SFDR = 79dBc
–20
SFDR/IMD3 (dBc AND dBFS)
–20
–40
SECOND HARMONIC
–60
THIRD HARMONIC
–80
–100
SFDR (dBc)
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–120
–100
–140
–120
–90.0
IMD3 (dBFS)
0
10
20
30
40
50
60
FREQUENCY (MHz)
70
80
Figure 8. AD9613-170 Single-Tone FFT with fIN = 305.1 MHz
09637-015
AMPLITUDE (dBFS)
SNR (dBFS)
–78.5
–67.0
–55.5
–44.0
–32.5
INPUT AMPLITUDE (dBFS)
–21.0
–7.0
09637-018
AMPLITUDE (dBFS)
–40
Figure 11. AD9613-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 89.12, fIN2 = 92.12 MHz, fS = 170 MSPS
Rev. D | Page 16 of 36
Data Sheet
AD9613
100
0
95
SNR/SFDR (dBc AND dBFS)
SFDR/IMD3 (dBc AND dBFS)
–20
SFDR (dBc)
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–100
90
85
SNR, CHANNEL B
SFDR, CHANNEL B
SNR, CHANNEL A
SFDR, CHANNEL A
80
75
70
–78.5
–32.5
–44.0
–67.0
–55.5
INPUT AMPLITUDE (dBFS)
–21.0
–7.0
65
40
09637-019
–120
–90.0
Figure 12. AD9613-170 Two-Tone SFDR/IMD3 vs.
Input Amplitude (AIN) with fIN1 = 184.12, fIN2 = 187.12 MHz, fS = 170 MSPS
60
70
80 90 100 110 120 130 140 150 160 170
SAMPLE RATE (MSPS)
Figure 15. AD9613-170 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90 MHz
0
16,000
170MSPS
89.12MHz @ –7dBFS
92.12MHz @ –7dBFS
SFDR = 87dBc (94dBFS)
–20
0.38LSB rms
16,384 TOTAL HITS
14,000
12,000
NUMBER OF HITS
–40
AMPLITUDE (dBFS)
50
09637-022
IMD3 (dBFS)
–60
–80
10,000
8000
6000
–100
4000
–120
2000
10
20
60
40
50
30
FREQUENCY (MHz)
70
80
0
N–1 N N+1
OUTPUT CODE
Figure 13. AD9613-170 Two-Tone FFT with fIN1 = 89.12, fIN2 = 92.12 MHz,
fS = 170 MSPS
Figure 16. AD9613-170 Grounded Input Histogram
0
0
170MSPS
184.12MHz @ –7dBFS
187.12MHz @ –7dBFS
SFDR = 84dBc (91dBFS)
–20
210MSPS
90.1MHz @ –1dBFS
SNR = 69.5dB (70.5dBFS)
SFDR = 88dBc
–20
–40
–40
AMPLITUDE (dBFS)
–60
–80
–100
–120
–60
THIRD HARMONIC
–80
–100
–120
0
10
20
40
50
60
30
FREQUENCY (MHz)
70
80
–140
09637-021
–140
0
Figure 14. AD9613-170 Two-Tone FFT with fIN1 = 184.12, fIN2 = 187.12 MHz,
fS = 170 MSPS
Rev. D | Page 17 of 36
10
20
30
60
70
40
50
FREQUENCY (MHz)
80
90
100
Figure 17. AD9613-210 Single-Tone FFT with fIN = 90.1 MHz
09637-024
AMPLITUDE (dBFS)
09637-023
0
09637-020
–140
AD9613
Data Sheet
0
100
210MSPS
185.1MHz @ –1dBFS
SNR = 68.5dB (69.5dBFS)
SFDR = 88dBc
95
SFDR (dBc)
SNR/SFDR (dBc AND dBFS)
–20
–60
THIRD HARMONIC
–80
–100
–120
85
80
75
SNR (dBFS)
70
65
0
10
20
30
60
70
40
50
FREQUENCY (MHz)
80
90
60
60
09637-025
–140
100
Figure 18. AD9613-210 Single-Tone FFT with fIN = 185.1 MHz
90
120 150
180 210 240 270 300
FREQUENCY (MHz)
330 360 390
Figure 21. AD9613-210 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
0
0
210MSPS
305.1MHz @ –1dBFS
SNR = 66.5dB (67.5dBFS)
SFDR = 75dBc
–20
SFDR/IMD3 (dBc AND dBFS)
–20
–40
AMPLITUDE (dBFS)
90
09637-028
AMPLITUDE (dBFS)
–40
THIRD HARMONIC
–60
SECOND HARMONIC
–80
–100
SFDR (dBc)
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–120
–100
–140
–120
–90.0
10
20
30
40
50
60
70
FREQUENCY (MHz)
80
90
100
Figure 19. AD9613-210 Single-Tone FFT with fIN = 305.1 MHz
–78.5
–67.0
–55.5
–44.0
–32.5
INPUT AMPLITUDE (dBFS)
–21.0
–7.0
09637-029
0
09637-026
IMD3 (dBFS)
Figure 22. AD9613-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 89.12 , fIN2 = 92.12 MHz, fS = 210 MSPS
120
0
SFDR (dBFS)
–20
80
SFDR/IMD3 (dBc AND dBFS)
SNR/SFDR (dBc AND dBFS)
100
SNR (dBFS)
60
SFDR (dBc)
40
SNR (dBc)
SFDR (dBc)
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–100
20
–80
–70 –60 –50 –40 –30
INPUT AMPLITUDE (dBFS)
–20
–10
0
09637-027
–90
–120
–90.0
Figure 20. AD9613-210 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 90.1 MHz
–78.5
–67.0
–55.5
–44.0
–32.5
INPUT AMPLITUDE (dBFS)
–21.0
–7.0
09637-030
IMD3 (dBFS)
0
–100
Figure 23. AD9613-210 Two-Tone SFDR/IMD3 vs.
Input Amplitude (AIN) with fIN1 = 184.12, fIN2 = 187.12 MHz, fS = 210 MSPS
Rev. D | Page 18 of 36
Data Sheet
AD9613
14,000
0
210MSPS
89.12MHz @ –7dBFS
92.12MHz @ –7dBFS
SFDR = 90dBc (97dBFS)
–20
NUMBER OF HITS
10,000
–60
–80
8000
6000
–100
4000
–120
2000
0
10
20
30
70
50
60
40
FREQUENCY (MHz)
80
90
100
0
N–2 N–1 N N+1
OUTPUT CODE
Figure 27. AD9613-210 Grounded Input Histogram
Figure 24. AD9613-210 Two-Tone FFT with fIN1 = 89.12, fIN2 = 92.12 MHz,
fS = 210 MSPS
0
0
210MSPS
184.12MHz @ –7dBFS
187.12MHz @ –7dBFS
SFDR = 88dBc (95dBFS)
–20
250MSPS
90.1MHz @ –1dBFS
SNR = 68.9dB (69.9dBFS)
SFDR = 88dBc
–20
–40
AMPLITUDE (dBFS)
–40
–60
–80
–100
SECOND HARMONIC
–60
THIRD HARMONIC
–80
–100
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
80
90
100
–140
09637-032
–140
0
0
95
–20
90
–40
AMPLITUDE (dBFS)
100
SNR, CHANNEL B
SFDR, CHANNEL B
SNR, CHANNEL A
SFDR, CHANNEL A
80
–120
180
200
90
100 110 120
THIRD HARMONIC
–140
09637-033
100
120
140
160
SAMPLE RATE (MSPS)
50 60 70 80
FREQUENCY (MHz)
SECOND HARMONIC
70
80
40
–80
–100
60
30
250MSPS
185.1MHz @ –1dBFS
SNR = 68.1dB (69.1dBFS)
SFDR = 85dBc
–60
75
65
40
20
Figure 28. AD9613-250 Single-Tone FFT with fIN = 90.1 MHz
Figure 25. AD9613-210 Two-Tone FFT with fIN1 = 184.12, fIN2 = 187.12 MHz,
fS = 210 MSPS
85
10
0
Figure 26. AD9613-210 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90 MHz
10
20
30
40
50 60 70 80
FREQUENCY (MHz)
90
100 110 120
Figure 29. AD9613-250 Single-Tone FFT with fIN = 185.1 MHz
Rev. D | Page 19 of 36
09637-035
–120
–120
09637-036
AMPLITUDE (dBFS)
09637-034
–140
09637-031
AMPLITUDE (dBFS)
–40
SNR/SFDR (dBc AND dBFS)
0.437LSB rms
16,384 TOTAL HITS
12,000
AD9613
Data Sheet
0
0
250MSPS
305.1MHz @ –1dBFS
SNR = 66.5dB (67.5dBFS)
SFDR = 83dBc
–20
SFDR/IMD3 (dBc AND dBFS)
–20
AMPLITUDE (dBFS)
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
–100
SFDR (dBc)
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–120
–100
–140
–120
–90.0
10
20
30
40
50 60 70 80
FREQUENCY (MHz)
90
100 110 120
Figure 30. AD9613-250 Single-Tone FFT with fIN = 305.1 MHz
–78.5
–67.0
–55.5
–44.0
–32.5
INPUT AMPLITUDE (dBFS)
–21.0
–7.0
09637-040
0
09637-037
IMD3 (dBFS)
Figure 33. AD9613-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 89.12, fIN2 = 92.12 MHz, fS = 250 MSPS
120
0
SFDR (dBFS)
–20
80
SFDR/IMD3 (dBc AND dBFS)
SNR/SFDR (dBc AND dBFS)
100
SNR (dBFS)
60
SFDR (dBc)
40
SNR (dBc)
20
SFDR (dBc)
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–100
–80
–70 –60 –50 –40 –30
INPUT AMPLITUDE (dBFS)
–20
–10
0
09637-038
–90
–120
–90.0
100
0
95
–20
–7.0
–40
85
80
75
SNR (dBFS)
70
–60
–80
–100
100
120
140 160 180 200
FREQUENCY (MHz)
220
240
260
–140
09637-039
80
0
Figure 32. AD9613-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
10
20
30
40
50 60 70 80
FREQUENCY (MHz)
90 100 110 120
09637-042
–120
65
60
60
–21.0
250MSPS
89.12MHz @ –7dBFS
92.12MHz @ –7dBFS
SFDR = 86dBc (93dBFS)
SFDR (dBc)
90
–67.0
–55.5
–44.0
–32.5
INPUT AMPLITUDE (dBFS)
Figure 34. AD9613-250 Two-Tone SFDR/IMD3 vs.
Input Amplitude (AIN) with fIN1 = 184.12, fIN2 = 187.12 MHz, fS = 250 MSPS
AMPLITUDE (dBFS)
SNR/SFDR (dBc AND dBFS)
Figure 31. AD9613-250 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 90.1 MHz
–78.5
09637-041
IMD3 (dBFS)
0
–100
Figure 35. AD9613-250 Two-Tone FFT with fIN1 = 89.12, fIN2 = 92.12 MHz,
fS = 250 MSPS
Rev. D | Page 20 of 36
Data Sheet
AD9613
16,000
0
250MSPS
184.12MHz @ –7dBFS
187.12MHz @ –7dBFS
SFDR = 86dBc (93dBFS)
–20
12,000
NUMBER OF HITS
–40
AMPLITUDE (dBFS)
0.39LSB rms
16,384 TOTAL HITS
14,000
–60
–80
10,000
8000
6000
–100
4000
–120
0
10
20
30
40
50 60 70 80
FREQUENCY (MHz)
90 100 110 120
0
09637-043
–140
N–1 N N+1
OUTPUT CODE
Figure 36. AD9613-250 Two-Tone FFT with fIN1 = 184.12, fIN2 = 187.12 MHz,
fS = 250 MSPS
100
SNR/SFDR (dBc AND dBFS)
95
90
85
SNR, CHANNEL B
SFDR, CHANNEL B
SNR, CHANNEL A
SFDR, CHANNEL A
80
75
65
40
60
80
100
120 140 160 180
SAMPLE RATE (MSPS)
200
220
240
09637-044
70
Figure 37. AD9613-250 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90.1 MHz
Rev. D | Page 21 of 36
Figure 38. AD9613-250 Grounded Input Histogram
09637-045
2000
AD9613
Data Sheet
EQUIVALENT CIRCUITS
AVDD
350Ω
SCLK
OR
PDWN
OR OEB
26kΩ
09637-010
09637-006
VIN
Figure 43. Equivalent SCLK, PDWN, or OEB Input Circuit
Figure 39. Equivalent Analog Input Circuit
AVDD
AVDD
AVDD
AVDD
26kΩ
0.9V
15kΩ
350Ω
CLK–
09637-011
09637-007
CLK+
CSB
15kΩ
Figure 40. Equivalent Clock lnput Circuit
Figure 44. Equivalent CSB Input Circuit
DRVDD
AVDD
V+
AVDD
V–
DATAOUT–
DATAOUT+
V–
SYNC
0.9V
V+
Figure 41. Equivalent LVDS Output Circuit
Figure 45. Equivalent SYNC Input Circuit
DRVDD
350Ω
26kΩ
09637-009
SDIO
09637-012
09637-063
16kΩ
0.9V
Figure 42. Equivalent SDIO Circuit
.
Rev. D | Page 22 of 36
Data Sheet
AD9613
THEORY OF OPERATION
The AD9613 has two analog input channels, two filter channels,
and two digital output channels. The intermediate frequency (IF)
input signal passes through several stages before appearing at the
output port(s) as a filtered, and optionally, decimated digital signal.
The dual ADC design can be used for diversity reception of signals,
where the ADCs operate identically on the same carrier but from
two separate antennae. The ADCs can also be operated with
independent analog inputs. The user can sample frequencies
from dc to 300 MHz using appropriate low-pass or band-pass
filtering at the ADC inputs with little loss in ADC performance.
Operation to 400 MHz analog input is permitted but occurs at
the expense of increased ADC noise and distortion.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9613 are accomplished
using a 3-pin, SPI-compatible serial interface.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, the
shunt capacitors should be reduced. In combination with the
driving source impedance, the shunt capacitors limit the input
bandwidth. Refer to the AN-742 Application Note, Frequency
Domain Response of Switched-Capacitor ADCs; the AN-827
Application Note, A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs; and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D Converters,”
for more information on this subject.
BIAS
S
S
CFB
CS
The AD9613 architecture consists of a dual front-end sampleand-hold circuit, followed by a pipelined, switched-capacitor
ADC. The quantized outputs from each stage are combined into
a final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-ended
modes. The output staging block aligns the data, corrects errors,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing digital output noise to be
separated from the analog core. During power-down, the output
buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9613 is a differential switched-capacitor
circuit that has been designed for optimum performance while
processing a differential input signal.
VIN+
CPAR1
CPAR2
S
S
H
CS
VIN–
CPAR1
CPAR2
S
S
BIAS
CFB
09637-050
ADC ARCHITECTURE
Figure 46. Switched-Capacitor Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched, and the inputs should be
differentially balanced.
Input Common Mode
The analog inputs of the AD9613 are not internally dc biased. In
ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD (or
0.9 V) is recommended for optimum performance. An on-board
common-mode voltage reference is included in the design and
is available from the VCM pin. Using the VCM output to set the
input common mode is recommended. Optimum performance
is achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM
pin must be decoupled to ground by a 0.1 µF capacitor, as described
in the Applications Information section. Place this decoupling
capacitor close to the pin to minimize the series resistance and
inductance between the part and this capacitor.
The clock signal alternatively switches the input between sample
mode and hold mode (see the configuration shown in Figure 46).
When the input is switched into sample mode, the signal source
must be capable of charging the sampling capacitors and settling
within 1/2 clock cycle.
Rev. D | Page 23 of 36
AD9613
Data Sheet
Differential Input Configurations
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz. Excessive signal power can also cause
core saturation, which leads to distortion.
Optimum performance is achieved while driving the AD9613
in a differential input configuration. For baseband applications, the
AD8138, ADA4937-2, ADA4938-2, and ADA4930-2 differential
drivers provide excellent performance and a flexible interface to
the ADC.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9613. For applications where
SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 49). In this
configuration, the input is ac-coupled, and the CML is provided
to each input through a 33 Ω resistor. These resistors compensate
for losses in the input baluns to provide a 50 Ω impedance to
the driver.
The output common-mode voltage of the ADA4930-2 is
easily set with the VCM pin of the AD9613 (see Figure 47),
and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
15pF
200Ω
76.8Ω
VIN
33Ω
90Ω
15Ω
VIN–
AVDD
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters,
the value of the input resistors and capacitors may need to be
adjusted or some components may need to be removed. Table 10
displays recommended values to set the RC network for different
input frequency ranges. However, these values are dependent
on the input signal and bandwidth and should be used only as
a starting guide. Note that the values given in Table 10 are for
each R1, R2, C2, and R3 component shown in Figure 48 and
Figure 49.
5pF
ADC
ADA4930-2
0.1µF
33Ω
15Ω
VCM
VIN+
120Ω
200Ω
33Ω
0.1µF
09637-051
15pF
Figure 47. Differential Input Configuration Using the ADA4938-2
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 48. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use an amplifier with variable
gain. The AD8375 or AD8376 digital variable gain amplifier
(DVGAs) provides good performance for driving the
AD9613. Figure 50 shows an example of the AD8376 driving the
AD9613 through a band-pass antialiasing filter.
C2
R3
R2
VIN+
R1
49.9Ω
ADC
C1
R2
R1
R3
0.1µF
VCM
VIN–
33Ω
0.1µF
09637-052
2V p-p
C2
Figure 48. Differential Transformer-Coupled Configuration
Table 10. Example RC Network
Frequency Range (MHz)
0 to 100
100 to 300
R1 Series (Ω)
33
15
C1 Differential (pF)
8.2
3.9
R2 Series (Ω)
0
0
C2 Shunt (pF)
15
8.2
C2
R3
R1
0.1µF
0.1µF
2V p-p
R2
VIN+
33Ω
S
S
P
0.1µF
33Ω
0.1µF
ADC
C1
R1
R2
R3
VIN–
33Ω
C2
Figure 49. Differential Double Balun Input Configuration
Rev. D | Page 24 of 36
VCM
0.1µF
09637-053
PA
R3 Shunt (Ω)
49.9
49.9
Data Sheet
AD9613
1000pF
180nH 220nH
1µH
165Ω
VPOS
AD8376
5.1pF
301Ω
1nF
1µH
1000pF
3.9pF
165Ω
AD9613
15pF
VCM
1nF
2.5kΩ║2pF
68nH
180nH 220nH
09637-054
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
2. FILTER VALUES SHOWN FOR A 20MHz BANDWIDTH FILTER
CENTERED AT 140MHz.
Figure 50. Differential Input Configuration Using the AD8376 (Filter Values Shown for a 20 MHz Bandwidth Filter Centered at 140 MHz)
A stable and accurate voltage reference is built into the
AD9613. The full-scale input range can be adjusted by varying the
reference voltage via SPI. The input span of the ADC tracks
reference voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
the clock from feeding through to other portions of the AD9613,
while preserving the fast rise and fall times of the signal, which are
critical to low jitter performance.
390pF
CLOCK
INPUT
For optimum performance, the AD9613 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal. The
signal is typically ac-coupled into the CLK+ and CLK− pins via
a transformer or via capacitors. These pins are biased internally
(see Figure 51) and require no external bias. If the inputs are
floated, the CLK− pin is pulled low to prevent spurious clocking.
AVDD
Mini-Circuits®
ADT1-1WT, 1:1Z
390pF
XFMR
50Ω
100Ω
390pF
SCHOTTKY
DIODES: HSMS2822
CLK–
Figure 52. Transformer Coupled Differential Clock (Up to 200 MHz)
CLOCK
INPUT
390pF
25Ω
ADC
390pF
CLK+
390pF
0.9V
CLK–
SCHOTTKY
DIODES:
HSMS2822
25Ω
CLK–
09637-057
Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)
09637-055
4pF
Figure 51. Simplified Equivalent Clock Input Circuit
Clock Input Options
The AD9613 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 52 and Figure 53 show two preferable methods for
clocking the AD9613 (at clock rates of up to 625 MHz). A low
jitter clock source is converted from a single-ended signal to a
differential signal using an RF balun or RF transformer.
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in Figure 54. The AD9510, AD9511, AD9512,
AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,
AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/
ADCLK925 clock drivers offer excellent jitter performance.
0.1µF
CLOCK
INPUT
CLK+
AD95xx
CLOCK
INPUT
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is
recommended for clock frequencies from 10 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9613 to approximately 0.8 V p-p
differential. This limit helps prevent the large voltage swings of
Rev. D | Page 25 of 36
ADC
0.1µF
0.1µF
PECL DRIVER
100Ω
0.1µF
CLK–
50kΩ
50kΩ
240Ω
240Ω
Figure 54. Differential PECL Sample Clock (Up to 625 MHz)
09637-058
CLK+
4pF
ADC
CLK+
09637-056
VOLTAGE REFERENCE
AD9613
Data Sheet
Jitter Considerations
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 55. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517,
AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers
offer excellent jitter performance.
0.1µF
0.1µF
CLOCK
INPUT
SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 ( − SNRLF /10) ]
ADC
CLK+
AD95xx
0.1µF
LVDS DRIVER
100Ω
0.1µF
CLK–
50kΩ
09637-059
CLOCK
INPUT
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input frequency
(fIN) due to jitter (tJ) can be calculated by
50kΩ
In the equation, the rms aperture jitter represents the rootmean-square of all jitter sources, which include the clock input,
the analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 56.
80
Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)
75
Input Clock Divider
The AD9613 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. The
duty cycle stabilizer (DCS) is enabled by default on power-up.
The AD9613 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9613 contains a duty-cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9613.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The
duty cycle control loop does not function for clock rates less
than 40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate can change
dynamically. A wait time of 1.5 µs to 5 µs is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the period that the
loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
65
60
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
55
50
1
10
100
INPUT FREQUENCY (MHz)
1000
09637-060
SNR (dBc)
70
Figure 56. AD9613-250 SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9613.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance, and the AN-756 Application Note,
Sample Systems and the Effects of Clock Phase Noise and Jitter,
for more information about jitter performance as it relates to
ADCs.
Rev. D | Page 26 of 36
Data Sheet
AD9613
POWER DISSIPATION AND STANDBY MODE
DIGITAL OUTPUTS
As shown in Figure 57, the power dissipated by the AD9613 is
proportional to its sample rate. The data in Figure 57 was taken
using the same operating conditions as those used for the Typical
Performance Characteristics section.
The AD9613 output drivers can be configured for either ANSI
LVDS or reduced drive LVDS using a 1.8 V DRVDD supply.
0.8
0.5
0.7
TOTAL POWER
Digital Output Enable Function (OEB)
0.4
IAVDD
0.4
0.2
0.3
IDRVDD
SUPPLY CURRENT (A)
0.3
The AD9613 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the OEB pin or
through the SPI interface. If the OEB pin is low, the output data
drivers are enabled. If the OEB pin is high, the output data drivers
are placed in a high impedance state. This OEB function is not
intended for rapid access to the data bus. Note that OEB is
referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
09637-061
TOTAL POWER (W)
0.6
0.5
When using the SPI interface, the data outputs of each channel
can be independently three-stated by using the output enable bar
bit (Bit 4) in Register 0x14. Because the output data is interleaved,
if only one of the two channels is disabled, the output data of
the remaining channel is repeated in both the rising and falling
output clock cycles.
0.2
0.1
0.1
0
40
0
60
80
100 120 140 160 180 200
ENCODE FREQUENCY (MSPS)
220
240
As detailed in Application Note AN-877, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
Figure 57. AD9613-250 Power and Current vs. Sample Rate
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9613 is placed in power-down mode.
In this state, the ADC typically dissipates 10 mW. During powerdown, the output drivers are placed in a high impedance state.
Asserting the PDWN pin low returns the AD9613 to its normal
operating mode. Note that PDWN is referenced to the digital
output driver supply (DRVDD) and should not exceed that
supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section and the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI, for additional details.
Timing
The AD9613 provides latched data with a pipeline delay of 10 input
sample clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9613. These
transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9613 is 40 MSPS. At
clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9613 also provides data clock output (DCO) intended for
capturing the data in an external register. Figure 2 shows a timing
diagram of the AD9613 output modes.
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 10 ADC clock. An overrange at the input is
indicated by this bit 10 clock cycles after it.
Table 11. Output Data Format
Input (V)
VIN+ − VIN–
VIN+ − VIN–
VIN+ − VIN–
VIN+ − VIN–
VIN+ − VIN–
VIN+ − VIN−,
Input Span = 1.75 V p-p (V)
Less than –0.875
–0.875
0
+0.875
Greater than +0.875
Offset Binary Output Mode
0000 0000 0000
0000 0000 0000
1000 0000 0000
1111 1111 1111
1111 1111 1111
Rev. D | Page 27 of 36
Twos Complement Mode (Default)
1000 0000 0000
1000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
OR
1
0
0
0
1
AD9613
Data Sheet
CHANNEL/CHIP SYNCHRONIZATION
The AD9613 has a SYNC input that allows the user flexible
synchronization options for synchronizing the internal blocks.
The sync feature is useful for guaranteeing synchronized operation
across multiple ADCs. The input clock divider can be synchronized
using the SYNC input. The divider can be enabled to synchronize
on a single occurrence of the SYNC signal or on every occurrence
by setting the appropriate bits in Register 0x3A.
The SYNC input is internally synchronized to the sample clock.
However, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be synchronized
to the input clock signal. The SYNC input should be driven
using a single-ended CMOS type signal.
Rev. D | Page 28 of 36
Data Sheet
AD9613
SERIAL PORT INTERFACE (SPI)
The AD9613 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that can
be further divided into fields. These fields are documented in the
Memory Map section. For detailed operational information, see
the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CSB pin (see Table 12). The SCLK (serial clock) pin
is used to synchronize the read and write data presented from/to
the ADC. The SDIO (serial data input/output) pin is a dualpurpose pin that allows data to be sent and read from the internal
ADC memory map registers. The CSB (chip select bar) pin is an
active-low control that enables or disables the read and write cycles.
Table 12. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
Function
Serial Clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip Select Bar. An active-low control that gates the read
and write cycles.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 58 and
Table 5.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes
to allow for additional external timing. When CSB is tied high,
SPI functions are placed in a high impedance mode. This mode
turns on any SPI pin secondary functions.
All data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether a read or write command is
issued. This allows the serial data input/output (SDIO) pin to
change direction from an input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 12 comprise the physical interface
between the user programming device and the serial port of the
AD9613. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between this
bus and the AD9613 to prevent these signals from transitioning at
the converter inputs during critical sampling periods.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase and its length is determined
by the W0 and W1 bits.
Rev. D | Page 29 of 36
AD9613
Data Sheet
SPI ACCESSIBLE FEATURES
Table 13 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9613 part-specific features are described in the
Memory Map Register Description section.
Table 13. Features Accessible Using the SPI
Feature Name
Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
Digital Processing
Description
Allows the user to set either power-down mode or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the converter offset
Allows the user to set test modes to have known data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
Allows the user to enable the synchronization features
tHIGH
tDS
tS
tDH
tCLK
tH
tLOW
CSB
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 58. Serial Port Interface Timing Diagram
Rev. D | Page 30 of 36
D4
D3
D2
D1
D0
DON’T CARE
09637-062
SCLK DON’T CARE
Data Sheet
AD9613
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Logic Levels
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into four sections: the chip
configuration registers (Address 0x00 to Address 0x02); the
channel index and transfer registers (Address 0x05 and
Address 0xFF); and the ADC functions registers, including
setup, control, and test (Address 0x08 to Address 0x3A).
An explanation of logic level terminology follows:
The memory map register table (see Table 14) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the default
hexadecimal value given. For example, Address 0x14, the output
mode register, has a hexadecimal default value of 0x05. This
means that Bit 0 = 1 and Bit 2 = 1, and the remaining bits are
0s. This setting is the default output format value, which is twos
complement. For more information on this function and others,
see the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. This document details the functions controlled by
Register 0x00 to Register 0x20. The remaining register, Register
0x3A, is documented in the Memory Map Register Description
section.
Open and Reserved Locations
All address and bit locations that are not included in Table 14
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
Default Values
After the AD9613 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table (see Table 14).
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x20 and Address 0x3A are shadowed.
Writes to these addresses do not affect part operation until a
transfer command is issued by writing 0x01 to Address 0xFF,
setting the transfer bit. This allows these registers to be updated
internally and simultaneously when the transfer bit is set. The
internal update takes place when the transfer bit is set and the
bit autoclears.
Channel Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed to a different value for each
channel. In these cases, channel address locations are internally
duplicated for each channel. These registers and bits are designated
in Table 14 as local. These local registers and bits can be accessed
by setting the appropriate Channel A or Channel B bits in Register
0x05. If both bits are set, the subsequent write affects the registers
of both channels. In a read cycle, only Channel A or Channel B
should be set to read one of the two registers. If both bits are set
during an SPI read cycle, the part returns the value for Channel A.
Registers and bits designated as global in Table 14 affect the entire
part and the channel features for which independent settings are
not allowed between channels. The settings in Register 0x05 do
not affect the global registers and bits.
Rev. D | Page 31 of 36
AD9613
Data Sheet
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 14 are not currently supported for this device.
Table 14. Memory Map Registers
Addr
Register
Bit 7
(Hex)
Name
(MSB)
Chip Configuration Registers
0
0x00
SPI port
configuration
(global) 1
0x01
0x02
Chip ID
(global)
Chip grade
(global)
Open
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
LSB first
Soft reset
1
1
Soft reset
LSB first
0
Open
8-bit chip ID[7:0] (AD9613 = 0x83)
(default)
Speed grade ID
Open
Open
00 = 250 MSPS
01 = 210 MSPS
11 = 170 MSPS
Default
Value
(Hex)
Default
Notes/
Comments
0x18
The nibbles
are mirrored
so that LSBfirst mode
or MSB-first
mode
registers
correctly,
regardless
of shift
mode
Read only
0x83
Open
Open
Speed
grade ID
used to
differentiate
devices;
read only
Channel Index and Transfer Registers
0x05
Channel index Open
(global)
Open
Open
Open
Open
Open
ADC B
(default)
ADC A
(default)
0x03
0xFF
Open
Open
Open
Open
Open
Open
Open
Transfer
0x00
ADC Functions
0x08
Power modes
(local)
Open
Open
Open
Open
Open
0x09
Global clock
(global)
Open
Open
External
powerdown pin
function
(local)
0 = powerdown
1 = standby
Open
Open
Open
Open
0x0B
Clock divide
(global)
Open
Open
Transfer
(global)
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Rev. D | Page 32 of 36
Internal power-down mode
(local)
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
Open
Duty cycle
stabilizer
(default)
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
Bits are set
to
determine
which
device on
the chip
receives the
next write
command;
applies to
local
registers
only
Synchronously
transfers
data from
the master
shift register
to the slave
Determines
various
generic
modes of
chip
operation
0x01
0x00
Clock divide
values other
than 000
automatically
cause the
duty cycle
stabilizer to
become
active
Data Sheet
AD9613
Addr
(Hex)
0x0D
Register
Name
Test mode
(local)
Bit 7
(MSB)
User test
mode
control
0=
continuou
s/repeat
pattern
1 = single
pattern,
then 0s
0x10
Offset adjust
(local)
Output mode
Open
Open
Open
Open
Open
0x15
Output Adjust
(Global)
Open
Open
Open
0x16
Clock phase
control
(global)
Invert
DCO clock
Open
Odd/Even
Mode
Output
Enable
0=
disabled
1=
enabled
0x17
DCO output
delay (global)
Enable
DCO
clock
delay
Open
Open
0x18
Input span
select (global)
Open
Open
Open
0x19
User Test
Pattern 1 LSB
(global)
User Test
Pattern 1 MSB
(global)
User Test
Pattern 2 LSB
(global)
User Test
Pattern 2 MSB
(global)
User Test
Pattern 3 LSB
(global)
0x14
0x1A
0x1B
0x1C
0x1D
Bit 6
Open
Bit 5
Reset PN
long gen
Bit 4
Reset PN
short gen
Bit 3
Bit 2
Bit 0
(LSB)
Bit 1
Output test mode
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN long sequence
0110 = PN short sequence
0111 = one/zero word toggle
1000 = user test mode
1001 to 1110 = unused
1111 = ramp output
Offset adjust in LSBs from +31 to −32
(twos complement format)
Output
Open
Output invert
Output format
enable bar
(local)
00 = offset binary
1 = normal
01 = twos complement
(local)
(default)
(default)
10 = gray code
0 = inverted
11 = reserved
(local)
Open
LVDS output drive current adjust
0000 = 3.72 mA output drive current
0001 = 3.5 mA output drive current (default)
0010 = 3.30 mA output drive current
0011 = 2.96 mA output drive current
0100 = 2.82 mA output drive current
0101 = 2.57 mA output drive current
0110 = 2.27 mA output drive current
0111 = 2.0 mA output drive current (reduced range)
1000 – 1111 = reserved
Open
Open
Open
Open
Open
Default
Value
(Hex)
0x00
0x00
0x05
Configures
the outputs
and the
format of
the data
0x01
0x00
DCO clock delay
[delay = (3100 ps × register value/31 +100)]
00000 = 100 ps
00001 = 200 ps
00010 = 300 ps
…
11110 = 3100 ps
11111 = 3200 ps
Full-scale input voltage selection
01111 = 2.087 V p-p
…
00001 = 1.772 V p-p
00000 = 1.75 V p-p (default)
11111 = 1.727 V p-p
…
10000 = 1.383 V p-p
User Test Pattern 1[7:0]
0x00
User Test Pattern 1[15:8]
0x00
User Test Pattern 2[7:0]
0x00
User Test Pattern 2[15:8]
0x00
User Test Pattern 3[7:0]
0x00
Rev. D | Page 33 of 36
Default
Notes/
Comments
When this
register is
set, the test
data is
placed on
the output
pins in
place of
normal data
0x00
0x00
Full-scale
input
adjustment
in 0.022 V
steps
AD9613
Addr
(Hex)
0x1E
0x1F
0x3A
1
Register
Name
User Test
Pattern 3 MSB
(global)
User Test
Pattern 4 LSB
(global)
Sync control
(global)
Data Sheet
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
User Test Pattern 3[15:8]
Bit 1
Bit 0
(LSB)
Open
Open
Open
Open
Default
Notes/
Comments
0x00
User Test Pattern 4[7:0]
Open
Default
Value
(Hex)
0x00
Clock
divider
next sync
only
Clock
divider
sync
enable
Master sync
buffer enable
0x00
The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00.
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00
to Register 0x20, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
Sync Control (Register 0x3A)
Bits[7:3]—Reserved
it receives and to ignore the rest. The clock divider sync enable
bit (Address 0x3A, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Buffer Enable
Bit 2—Clock Divider Next Sync Only
If the master sync buffer enable bit (Address 0x3A, Bit 0) and
the clock divider sync enable bit (Address 0x3A, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse that
Bit 0 must be set high to enable any of the sync functions. If
the sync capability is not used, this bit should remain low to
conserve power.
Rev. D | Page 34 of 36
Data Sheet
AD9613
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting system-level design and layout of the AD9613,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9613, it is recommended that
two separate 1.8 V supplies be used: one supply should be used
for analog (AVDD), and a separate supply should be used for the
digital outputs (DRVDD). The designer can employ several
different decoupling capacitors to cover both high and low
frequencies. These capacitors should be located close to the
point of entry at the PC board level and close to the pins of the
part with minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9613. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask) copper plane on the PCB should mate to the
AD9613 exposed paddle, Pin 0.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow through
the bottom of the PCB. These vias should be filled or plugged with
nonconductive epoxy.
To maximize the coverage and adhesion between the ADC
and the PCB, a silkscreen should be overlaid to partition the
continuous plane on the PCB into several uniform sections.
This provides several tie points between the ADC and the PCB
during the reflow process. Using one continuous plane with no
partitions guarantees only one tie point between the ADC and
the PCB. See the evaluation board for a PCB layout example.
For detailed information about the packaging and PCB layout
of chip-scale packages, refer to the AN-772 Application Note, A
Design and Manufacturing Guide for the Lead Frame Chip Scale
Package (LFCSP).
VCM
The VCM pin should be decoupled to ground with a 0.1 µF
capacitor, as shown in Figure 48. For optimal channel-to-channel
isolation, a 33 Ω resistor should be included between the AD9613
VCM pin and the Channel A analog input network connection,
as well as between the AD9613 VCM pin and the Channel B
analog input network connection.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9613 to keep these signals from transitioning at the converter
input pins during critical sampling periods.
Rev. D | Page 35 of 36
AD9613
Data Sheet
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
0.30
0.25
0.18
0.60 MAX
0.60
MAX
64 1
49
48
PIN 1
INDICATOR
PIN 1
INDICATOR
8.85
8.75 SQ
8.65
0.50
BSC
0.50
0.40
0.30
33
32
0.25 MIN
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
06-12-2012-C
0.05 MAX
0.02 NOM
SEATING
PLANE
16
7.50 REF
0.80 MAX
0.65 TYP
12° MAX
17
BOTTOM VIEW
TOP VIEW
1.00
0.85
0.80
6.35
6.20 SQ
6.05
EXPOSED
PAD
Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9613BCPZ-170
AD9613BCPZ-210
AD9613BCPZ-250
AD9613BCPZRL7-170
AD9613BCPZRL7-210
AD9613BCPZRL7-250
AD9613-170EBZ
AD9613-210EBZ
AD9613-250EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 170 MSPS
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 210 MSPS
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 250 MSPS
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 170 MSPS
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 210 MSPS
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 250 MSPS
Evaluation Board with AD9613, 170 MSPS
Evaluation Board with AD9613, 210 MSPS
Evaluation Board with AD9613, 250 MSPS
Z = RoHS Compliant Part.
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