TI ADS7822UC/2K5G4 12-bit, high-speed, 2.7v micropower sampling analog-to-digital converter Datasheet

ADS7822
ADS
ADS
7822
OPA7822
658
SBAS062A – JANUARY 1996 – REVISED MARCH 2005
12-Bit, High-Speed, 2.7V microPower Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 75kHz SAMPLING RATE
● MICRO POWER:
0.54mW at 75kHz
0.06mW at 7.5kHz
● POWER DOWN: 3µA max
● MINI-DIP-8, SOIC-8, AND MSOP-8
● PSEUDO-DIFFERENTIAL INPUT
● SERIAL INTERFACE
The ADS7822 is a 12-bit sampling analog-to-digital (A/D)
converter with ensured specifications over a 2.7V to 5.25V
supply range. It requires very little power even when operating at the full 75kHz rate. At lower conversion rates, the
high speed of the device enables it to spend most of its time
in the power-down mode—the power dissipation is less than
60µW at 7.5kHz.
The ADS7822 also features operation from 2.0V to 5V, a
synchronous serial interface, and a pseudo-differential input.
The reference voltage can be set to any level within the
range of 50mV to VCC.
Ultra low power and small size make the ADS7822 ideal for
battery-operated systems. It is also a perfect fit for remote
data acquisition modules, simultaneous multi-channel systems, and isolated data acquisition. The ADS7822 is available in a plastic mini-DIP-8, an SOIC-8, or an MSOP-8
package.
APPLICATIONS
●
●
●
●
BATTERY-OPERATED SYSTEMS
REMOTE DATA ACQUISITION
ISOLATED DATA ACQUISITION
SIMULTANEOUS SAMPLING,
MULTI-CHANNEL SYSTEMS
Control
SAR
VREF
DOUT
+In
CDAC
Serial
Interface
–In
S/H Amp
Comparator
DCLOCK
CS/SHDN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 1996-2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
SPECIFICATIONS: +VCC = +2.7V
At –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
ADS7822
PARAMETER
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
CONDITIONS
MIN
+In – (–In)
+In
–In
0
–0.2
–0.2
Capacitance
Leakage Current
Current Drain
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
VIL
VOH
VOL
Data Format
TEMPERATURE RANGE
Specified Performance
NOTES: (1)
(2)
(3)
(4)
(5)
2
TYP
VREF
VCC +0.2
+1.0
0
–0.2
–0.2
±0.5
±0.5
ADS7822C
MAX
MIN
VREF
VCC +0.2
+1.0
0
–0.2
–0.2
+2
+2
+3
+3
12
–1
–1
–3
–3
±0.5
±0.5
+1
+1
+3
+3
2.0
–0.3
2.1
75
VCC
5
5
8
0.8
0.001
40
3
CMOS
2.0
–0.3
2.1
5.5
0.8
CS = VCC
200
20
180
3
–40
+85
40
3
2.0
–0.3
2.1
5.5
0.8
0.4
2.7
2.0
3.6
V
GΩ
GΩ
µA
µA
µA
0.4
V
V
V
V
Straight Binary
3.6
2.7
5.25
325
2.7
2.0
3.6
200
20
180
3
–40
Clk Cycles
Clk Cycles
kHz
CMOS
Straight Binary
3.6
2.7
5.25
325
VCC
5
5
8
0.8
0.001
3
Bits
Bits
LSB(1)
LSB
LSB
LSB
µVrms
dB
dB
dB
dB
0.05
40
0.4
200
20
180
75
–82
71
86
0.05
Straight Binary
2.7
2.0
3.6
+0.75
+0.75
+1
+1
12
–82
71
86
5.5
0.8
±0.25
±0.25
1.5
CMOS
IIH = +5µA
IIL = +5µA
IOH = –250µA
IOL = 250µA
V
V
V
pF
µA
12
–82
71
86
VCC
VREF
VCC +0.2
+1.0
33
82
75
5
5
8
0.8
0.001
11
–0.75
–0.75
–1
–1
33
82
1.5
0.05
UNITS
12
12
CS = GND, fSAMPLE = 0Hz
CS = VCC
At Code 710h
fSAMPLE = 7.5kHz
CS = VCC
MAX
25
±1
12
1.5
VIN = 2.5Vp-p at 1kHz
VIN = 2.5Vp-p at 1kHz
VIN = 2.5Vp-p at 1kHz
TYP
25
±1
33
82
POWER SUPPLY REQUIREMENTS
VCC
Specified Performance
See Notes 2 and 3
See Note 3
Quiescent Current
fSAMPLE = 7.5kHz(4,5)
fSAMPLE = 75kHz(5)
Power Down
MIN
12
11
–2
–2
–3
–3
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
REFERENCE INPUT
Voltage Range
Resistance
MAX
25
±1
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Noise
Power Supply Rejection
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
SINAD
Spurious Free Dynamic Range
ADS7822B
TYP
+85
–40
3.6
2.7
5.25
325
V
V
V
µA
µA
µA
3
µA
+85
°C
LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 0.61mV.
The maximum clock rate of the ADS7822 is less than 1.2MHz in this power supply range.
See the Typical Performance Curves for more information.
fCLK = 1.2MHz, CS = VCC for 145 clock cycles out of every 160.
See the Power Dissipation section for more information regarding lower sample rates.
ADS7822
www.ti.com
SBAS062A
SPECIFICATIONS: +VCC = +5V
At –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
ADS7822
PARAMETER
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
CONDITIONS
MIN
+In – (–In)
+In
–In
0
–0.2
–0.2
Capacitance
Leakage Current
Current Drain
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
VIL
VOH
VOL
Data Format
VREF
VCC +0.2
+1.0
0
–0.2
–0.2
+3
+4
12
–1
–1
–3
–3
33
70
±0.5
12
V
V
V
pF
µA
+1
+1
+3
+3
12
200
–78
71
79
0.05
–78
71
79
VCC
5
5
40
2.5
0.001
0.05
100
3
3.0
–0.3
3.5
3.0
–0.3
3.5
–40
100
3
5.5
0.8
0.4
Straight Binary
320
Clk Cycles
Clk Cycles
kHz
V
GΩ
GΩ
µA
µA
µA
CMOS
5.5
0.8
4.5
Bits
Bits
LSB(1)
LSB
LSB
LSB
µVrms
dB
dB
dB
dB
VCC
5
5
40
2.5
0.001
CMOS
IIH = +5µA
IIL = +5µA
IOH = –250µA
IOL = 250µA
VREF
VCC +0.2
+1.0
1.5
200
CS = GND, fSAMPLE = 0Hz
CS = VCC
At Code 710h
fSAMPLE = 12.5kHz
CS = VCC
UNITS
33
70
1.5
VIN = 5Vp-p at 10kHz
VIN = 5Vp-p at 10kHz
VIN = 5Vp-p at 10kHz
MAX
12
+2
–3
–4
TYP
25
±1
±0.8
POWER SUPPLY REQUIREMENTS
VCC
Specified Performance
Quiescent Current
fSAMPLE = 200kHz
Power Down
CS = VCC
TEMPERATURE RANGE
Specified Performance
MIN
12
11
–2
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
REFERENCE INPUT
Voltage Range
Resistance
ADS7822B
MAX
25
±1
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Noise
Power Supply Rejection
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
SINAD
Spurious Free Dynamic Range
TYP
0.4
V
V
V
V
5.25
550
3
V
µA
µA
+85
°C
Straight Binary
5.25
550
3
4.75
+85
–40
320
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +5V, one LSB is 1.22mV.
ADS7822
SBAS062A
www.ti.com
3
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
VCC ....................................................................................................... +6V
Analog Input .............................................................. –0.3V to (VCC + 0.3V)
Logic Input ............................................................................... –0.3V to 6V
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +125°C
External Reference Voltage .............................................................. +5.5V
Top View
DIP, MSOP, SO
NOTE: (1) Stresses above these ratings may permanently damage the device.
ELECTROSTATIC
DISCHARGE SENSITIVITY
VREF
1
+In
2
8
+VCC
7
DCLOCK
ADS7822
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Texas
Instruments recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
–In
3
6
DOUT
GND
4
5
CS/SHDN
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
PIN ASSIGNMENTS
PIN
NAME
1
VREF
DESCRIPTION
2
+In
Non Inverting Input.
3
–In
Inverting Input. Connect to ground or to remote ground sense point.
Reference Input.
4
GND
5
CS/SHDN
Ground.
6
DOUT
7
DCLOCK
8
+VCC
Chip Select when LOW, Shutdown Mode when HIGH.
The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The
second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.
Data Clock synchronizes the serial data transfer and determines conversion speed.
Power Supply.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
ADS7822E
ADS7822E
ADS7822EB
ADS7822EB
ADS7822EC
ADS7822EC
ADS7822P
ADS7822PB
ADS7822PC
ADS7822U
ADS7822U
ADS7822UB
ADS7822UB
ADS7822UC
ADS7822UC
MAXIMUM
INTEGRAL
LINEARITY
ERROR
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
ERROR
(LSB)
±2
"
±1
PACKAGE
PACKAGE
DESIGNATOR
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
MARKING(2)
ORDERING
NUMBER(3)
TRANSPORT
MEDIA
±2
MSOP-8
DGK
–40°C to +85°C
A22
"
"
"
"
±1
MSOP-8
DGK
–40°C to +85°C
A22
ADS7822E/250
ADS7822E/2K5
ADS7822EB/250
ADS7822EB/2K5
ADS7822EC/250
ADS7822EC/2K5
ADS7822P
ADS7822PB
ADS7822PC
ADS7822U
ADS7822U/2K5
ADS7822UB
ADS7822UB/2K5
ADS7822UC
ADS7822UC/2K5
Tape and Reel
"
"
"
"
"
"
"
±0.75
±0.75
MSOP-8
DGK
–40°C to +85°C
A22
"
"
"
"
±2
±1
±0.75
±2
±2
±1
±0.75
±2
Plastic DIP-8
Plastic DIP-8
Plastic DIP-8
SOIC-8
P
P
P
D
"
–40°C
–40°C
–40°C
–40°C
to
to
to
to
"
+85°C
+85°C
+85°C
+85°C
ADS7822P
ADS7822PB
ADS7822PC
ADS7822U
"
"
"
"
"
"
±1
±1
SOIC-8
D
–40°C to +85°C
ADS7822UB
"
"
"
"
"
"
±0.75
±0.75
SOIC-8
D
–40°C to +85°C
ADS7822UC
"
"
"
"
"
"
"
Tape and Reel
"
Tape and Reel
"
Rails
Rails
Rails
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
NOTES: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
(2) Performance Grade information is marked on the reel.
(3) Models with a slash(/) are available only in tape and reel in quantities indicated (e.g. /250 indicates 250 units per reel, /2K5 indicates 2500
devices per reel). Ordering 2500 pieces of ”ADS7822E/2K5“ will get a single 2500-piece tape and reel.
4
ADS7822
www.ti.com
SBAS062A
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
DIFFERENTIAL LINEARITY ERROR vs CODE
1.00
0.75
0.75
Differential Linearity Error (LSB)
Integral Linearity Error (LSB)
INTEGRAL LINEARITY ERROR vs CODE
1.00
0.50
0.25
0.00
–0.25
–0.50
–0.75
–1.00
0.50
0.25
0.00
–0.25
–0.50
–0.75
–1.00
0
2048
Code
4095
0
4095
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
350
120
300
100
Supply Current (nA)
Supply Current (µA)
2048
Code
250
200
150
100
80
60
40
20
50
0
–50
–25
0
25
50
75
100
–50
–25
0
Temperature (°C)
25
50
75
100
Temperature (°C)
QUIESCENT CURRENT vs VCC
MAXIMUM SAMPLE RATE vs VCC
400
1000
Sample Rate (kHz)
Quiescent Current (µA)
350
300
250
200
100
10
150
100
1
1
2
3
4
5
1
VCC (V)
ADS7822
SBAS062A
www.ti.com
2
3
VCC (V)
4
5
5
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
CHANGE IN OFFSET vs TEMPERATURE
CHANGE IN OFFSET vs REFERENCE VOLTAGE
0.6
1.2
VCC = 5V
0.4
0.8
Delta from 25°C (LSB)
Change in Offset (LSB)
1.0
0.6
0.4
0.2
0.0
–0.2
–0.4
0.2
0
–0.2
–0.4
–0.6
–0.6
–0.8
1
2
3
Reference Voltage (V)
4
–50
5
–25
CHANGE IN GAIN vs REFERENCE VOLTAGE
75
100
CHANGE IN GAIN vs TEMPERATURE
VCC = 5V
0.1
Delta from 25°C (LSB)
Change in Gain (LSB)
50
0.15
2.0
1.5
1.0
0.5
0.0
–0.5
0.05
0
–0.05
–0.1
–1.0
–0.15
–1.5
1
2
3
Reference Voltage (V)
4
–50
5
–25
0
25
50
75
100
Temperature (°C)
EFFECTIVE NUMBER OF BITS
vs REFERENCE VOLTAGE
PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE
10
12
VCC = 5V
9
VCC = 5V
11.75
Peak-to-Peak Noise (LSB)
Effective Number of Bits (rms)
25
Temperature (°C)
2.5
11.5
11.25
11
10.75
10.5
10.25
8
7
6
5
4
3
2
1
10
0
0.1
6
0
1
Reference Voltage (V)
0.1
10
1
Reference Voltage (V)
10
ADS7822
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SBAS062A
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
SPURIOUS FREE DYNAMIC RANGE and
SIGNAL-TO-NOISE RATIO vs FREQUENCY
TOTAL HARMONIC DISTORTION vs FREQUENCY
0
Spurious Free Dynamic Range
90
80
70
60
–10
Total Harmonic Distortion (dB)
Spurious Free Dynamic Range
and Signal-to-Noise Ratio (dB)
100
Signal-to-Noise Ratio
50
40
30
20
–20
–30
–40
–50
–60
–70
–80
10
–90
0
–100
1
10
Frequency (kHz)
100
1
Signal-to-(Noise + Distortion) (dB)
90
80
70
60
50
40
30
20
10
0
10
Frequency (kHz)
100
80
70
60
50
40
30
20
10
0
–40
–35
–30
–25
–20
–15
Input Level (dB)
–10
–5
0
REFERENCE CURRENT vs TEMPERATURE
(Code = 710h)
REFERENCE CURRENT vs SAMPLE RATE
14
14
12
12
Reference Current (µA)
Reference Current (µA)
100
SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL
Signal-to-(Noise Ratio Plus Distortion) (dB)
SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY
100
1
10
Frequency (kHz)
10
8
6
4
10
8
6
4
2
0
2
0
15
30
45
60
75
–50
Sample Rate (kHz)
0
25
50
75
100
Temperature (°C)
ADS7822
SBAS062A
–25
www.ti.com
7
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
0
0
−20
PSR (dB)
−30
VCC = 2.7V
Ripple = 500mVPP
VIN = 1.25VDC
VREF = 2.5V
−20
−30
−40
−50
−40
−50
−60
−60
−70
−70
−80
−80
PSR (dB) = 20log(500mV/∆VO)
where ∆VO = change in digital result
−90
1k
10k
VCC = 5V
Ripple = 500mVPP
VIN = 2.5VDC
VREF = 5V
−10
PSR (dB)
−10
100k
1M
PSR (dB) = 20log(500mV/∆VO)
where ∆VO = change in digital result
−90
10
10M
1
1k
10k
100k
1M
10M
Ripple Frequency (Hz)
Ripple Frequency (Hz)
CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL
LINEARITY vs REFERENCE VOLTAGE
Delta from +2.5V Reference (LSB)
0.20
VCC = 5V
0.15
Change in Integral
Linearity (LSB)
0.10
0.05
0.00
Change in Differential
Linearity (LSB)
–0.05
–0.10
1
8
2
3
Reference Voltage (V)
4
5
ADS7822
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SBAS062A
THEORY OF OPERATION
ANALOG INPUT
The ADS7822 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a 0.6µ
CMOS process. The architecture and process allow the
ADS7822 to acquire and convert an analog signal at up to
75,000 conversions per second while consuming very little
power.
The ADS7822 requires an external reference, an external
clock, and a single power source (VCC). The external reference can be any voltage between 50mV and VCC. The value
of the reference voltage directly sets the range of the analog
input. The reference input current depends on the conversion
rate of the ADS7822.
The external clock can vary between 10kHz (625Hz throughput) and 1.2MHz (75kHz throughput). The duty cycle of the
clock is essentially unimportant as long as the minimum high
and low times are at least 400ns (VCC = 2.7V or greater).
The minimum clock frequency is set by the leakage on the
capacitors internal to the ADS7822.
The analog input is provided to two input pins: +In and –In.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.
The digital result of the conversion is clocked out by the
DCLOCK input and is provided serially, most significant bit
first, on the DOUT pin. The digital data that is provided on the
DOUT pin is for the conversion currently in progress—there
is no pipeline delay. It is possible to continue to clock the
ADS7822 after the conversion is complete and to obtain the
serial data least significant bit first. See the digital timing
section for more information.
The +In and –In input pins allow for a pseudo-differential
input signal. Unlike some converters of this type, the –In
input is not re-sampled later in the conversion cycle. When
the converter goes into the hold mode, the voltage difference
between +In and –In is captured on the internal capacitor
array.
The range of the –In input is limited to –0.2V to +1V.
Because of this, the differential input can be used to reject
only small signals that are common to both inputs. Thus, the
–In input is best used to sense a remote signal ground that
may move slightly with respect to the local ground potential.
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, source impedance, and
power-down mode. Essentially, the current into the ADS7822
charges the internal capacitor array during the sample period.
After this capacitance has been fully charged, there is no
further input current. The source of the analog input voltage
must be able to charge the input capacitance (25pF) to a
12-bit settling level within 1.5 clock cycles. When the
converter goes into the hold mode or while it is in the power
down mode, the input impedance is greater than 1GΩ.
Care must be taken regarding the absolute analog input
voltage. To maintain the linearity of the converter, the –In
input should not drop below GND – 200mV or exceed
GND + 1V. The +In input should always remain within the
range of GND – 200mV to VCC + 200mV. Outside of these
ranges, the converter’s linearity may not meet specifications.
ADS7822
SBAS062A
www.ti.com
9
REFERENCE INPUT
With lower reference voltages, extra care should be taken to
provide a clean layout including adequate bypassing, a clean
power supply, a low-noise reference, and a low-noise input
signal. Because the LSB size is lower, the converter will also
be more sensitive to external sources of error such as nearby
digital signals and electromagnetic interference.
The external reference sets the analog input range. The
ADS7822 will operate with a reference in the range of 50mV
to VCC. There are several important implications of this.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the LSB (least significant bit) size and is equal
to the reference voltage divided by 4096. This means that any
offset or gain error inherent in the A/D converter will appear
to increase, in terms of LSB size, as the reference voltage is
reduced.
The noise inherent in the converter will also appear to
increase with lower LSB size. With a 2.5V reference, the
internal noise of the converter typically contributes only 0.32
LSB peak-to-peak of potential error to the output code. When
the external reference is 50mV, the potential error contribution from the internal noise will be 50 times larger—16
LSBs. The errors due to the internal noise are gaussian in
nature and can be reduced by averaging consecutive conversion results.
For more information regarding noise, consult the typical
performance curves “Effective Number of Bits vs Reference
Voltage” and “Peak-to-Peak Noise vs Reference Voltage.”
Note that the effective number of bits (ENOB) figure is
calculated based on the converter’s signal-to-(noise + distortion) ratio with a 1kHz, 0dB input signal. SINAD is related
to ENOB as follows
DIGITAL INTERFACE
SIGNAL LEVELS
The digital inputs of the ADS7822 can accommodate logic
levels up to 6V regardless of the value of VCC. Thus, the
ADS7822 can be powered at 3V and still accept inputs from
logic powered at 5V.
The CMOS digital output (DOUT) will swing 0V to VCC. If
VCC is 3V and this output is connected to a 5V CMOS logic
input, then that IC may require more supply current than
normal and may have a slightly longer propagation delay.
SERIAL INTERFACE
The ADS7822 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 1 and Table I. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on
the falling edge of DCLOCK. Most receiving systems will
capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the
system can use the falling edge of DCLOCK to capture each
bit.
SINAD = 6.02 • ENOB + 1.76
tCYC
CS/SHDN
Power
Down
tSUCS
DCLOCK
tCSD
DOUT
Hi-Z
Null
Bit
tSMPL
Null
Bit
Hi-Z
B11 B10 B9
(MSB)
B8
B7
B6
B5
B4
B3
B2
B1 B0(1)
tCONV
B11 B10
B9
B8
tDATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output LSB-First data then followed with zeroes indefinitely.
tCYC
CS/SHDN
tSUCS
Power Down
DCLOCK
tCSD
DOUT
Hi-Z
tSMPL
Null
Bit
Hi-Z
B11 B10 B9
(MSB)
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9 B10 B11
(1)
tCONV
tDATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output zeroes indefinitely.
tDATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
FIGURE 1. ADS7822 Basic Timing Diagrams.
10
ADS7822
www.ti.com
SBAS062A
SYMBOL
DESCRIPTION
MIN
tSMPL
Analog Input Sample Time
1.5
TYP
MAX
UNITS
2.0
Clk Cycles
tCONV
Conversion Time
tCYC
Throughput Rate
75
kHz
tCSD
CS Falling to
DCLOCK LOW
0
ns
tSUCS
CS Falling to
DCLOCK Rising
30
ns
thDO
DCLOCK Falling to
Current DOUT Not Valid
15
ns
tdDO
DCLOCK Falling to Next
DOUT Valid
tdis
CS Rising to DOUT Tri-State
40
80
ns
ten
DCLOCK Falling to DOUT
Enabled
75
175
ns
12
Clk Cycles
130
200
DATA FORMAT
The output data from the ADS7822 is in straight binary
format as shown in Table II. This table represents the ideal
output code for the given input voltage and does not include
the effects of offset, gain error, or noise.
ns
tf
DOUT Fall Time
90
200
ns
tr
DOUT Rise Time
110
200
ns
periods, DOUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in a
least significant bit first format.
After the most significant bit (B11) has been repeated, DOUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
TABLE I. Timing Specifications (VCC = 2.7V and above,
–40°C to +85°C.
DESCRIPTION
ANALOG VALUE
Full Scale Range
Least Significant
Bit (LSB)
A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, DOUT is enabled and will output a LOW
value for one clock period. For the next 12 DCLOCK
DIGITAL OUTPUT
VREF
STRAIGHT BINARY
VREF/4096
Full Scale
VREF –1 LSB
HEX CODE
FFF
VREF/2
1000 0000 0000
800
VREF/2 – 1 LSB
0111 1111 1111
7FF
0V
0000 0000 0000
000
Midscale
Midscale – 1 LSB
BINARY CODE
1111 1111 1111
Zero
TABLE II. Ideal Input Voltages and Output Codes.
1.4V
3kΩ
DOUT
VOH
DOUT
VOL
Test Point
tr
100pF
CLOAD
tf
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Load Circuit for tdDO, tr, and tf
Test Point
DCLOCK
VIL
VCC
DOUT
tdDO
VOH
DOUT
tdis Waveform 2, ten
3kΩ
tdis Waveform 1
100pF
CLOAD
VOL
thDO
Load Circuit for tdis and ten
Voltage Waveforms for DOUT Delay Times, tdDO
VIH
CS/SHDN
DOUT
Waveform 1(1)
CS/SHDN
90%
DCLOCK
1
2
tdis
DOUT
Waveform 2(2)
VOL
DOUT
10%
B11
ten
Voltage Waveforms for tdis
Voltage Waveforms for ten
NOTES: (1) Waveform 1 is for an output with internal conditions such that the output
is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with
internal conditions such that the output is LOW unless disabled by the output control.
FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I.
ADS7822
SBAS062A
www.ti.com
11
POWER DISSIPATION
1000
SHORT CYCLING
Another way of saving power is to utilize the CS signal to
short-cycle the conversion. Because the ADS7822 places the
latest data bit on the DOUT line as it is generated, the
converter can easily be short-cycled. This term means that
the conversion can be terminated at any time. For example,
if only 8 bits of the conversion result are needed, then the
conversion can be terminated (by pulling CS HIGH) after the
8th bit has been clocked out.
12
Supply Current (µA)
TA = 25°C
fCLK = 1.2MHz
100
VCC = 5.0V
VREF = 5.0V
VCC = 2.7V
VREF = 2.5V
10
1
0.1
1
10
100
Sample Rate (kHz)
FIGURE 3. Maintaining fCLK at the Highest Possible Rate
Allows Supply Current to Drop Linearly with
Sample Rate.
Supply Current (µA)
1000
100
10
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fCLK = 16 • fSAMPLE
1
0.1
1
10
100
Sample Rate (kHz)
FIGURE 4. Scaling fCLK Reduces Supply Current Only
Slightly with Sample Rate.
10.0
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fCLK = 16 • fSAMPLE
8.0
Supply Current (µA)
The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS7822 to
convert at up to a 75kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS7822 scales directly with
conversion rate. So, the first step to achieving the lowest
power dissipation is to find the lowest conversion rate that
will satisfy the requirements of the system.
In addition, the ADS7822 is in power-down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 1). Ideally, each conversion should
occur as quickly as possible, preferably at a 1.2MHz clock
rate. This way, the converter spends the longest possible time
in the power-down mode. This is very important as the
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the comparator.
The analog section dissipates power continuously, until the
power-down mode is entered.
Figure 3 shows the current consumption of the ADS7822
versus sample rate. For this graph, the converter is clocked at
1.2MHz regardless of the sample rate—CS is HIGH for the
remaining sample period. Figure 4 also show current consumption versus sample rate. However, in this case, the
DCLOCK period is 1/16th of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
There is an important distinction between the power-down
mode that is entered after a conversion is complete and the
full power-down mode that is enabled when CS is HIGH.
While both shutdown the analog section, the digital section
is completely shutdown only when CS is HIGH. Thus, if CS
is left LOW at the end of a conversion and the converter is
continually clocked, the power consumption will not be as
low as when CS is HIGH. See Figure 5 for more information.
Power dissipation can also be reduced by lowering the power
supply voltage and the reference voltage. The ADS7822 will
operate over a VCC range of 2.0V to 5.25V. However, at
voltages below 2.7V, the converter will not run at a 75kHz
sample rate. See the typical performance curves for more
information regarding power supply voltage and maximum
sample rate.
6.0
CS LOW (GND)
4.0
2.0
0.0
CS HIGH (VCC)
0.050
0.00
0.1
1
10
100
Sample Rate (kHz)
FIGURE 5. Shutdown Current with CS HIGH is 50nA
Typically, Regardless of the Clock. Shutdown
Current with CS LOW Varies with Sample
Rate.
ADS7822
www.ti.com
SBAS062A
This technique can be used to lower the power dissipation (or
to increase the conversion rate) in those applications where
an analog signal is being monitored until some condition
becomes true. For example, if the signal is outside a predetermined range, the full 12-bit conversion result may not be
needed. If so, the conversion can be terminated after the first
n-bits, where n might be as low as 3 or 4. This results in lower
power dissipation in both the converter and the rest of the
system, as they spend more time in the power-down mode.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7822 circuitry. This will be
particularly true if the reference voltage is low and/or the
conversion rate is high. At a 75kHz conversion rate, the
ADS7822 makes a bit decision every 830ns. That is, for each
subsequent bit decision, the digital output must be updated
with the results of the last bit decision, the capacitor array
appropriately switched and charged, and the input to the
comparator settled to a 12-bit level all within one clock cycle.
The basic SAR architecture is sensitive to spikes on the
power supply, reference, and ground connections that occur
just prior to latching the comparator output. Thus, during any
single conversion for an n-bit SAR converter, there are n
“windows” in which large external transient voltages can
easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high
power devices, to name a few. This particular source of error
can be very difficult to track down if the glitch is almost
synchronous to the converter’s DCLOCK signal—as the
phase difference between the two changes with time and
temperature, causing sporadic misoperation.
With this in mind, power to the ADS7822 should be clean
and well-bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the ADS7822 package as possible. In
addition, a 1 to 10µF capacitor and a 5Ω or 10Ω series
resistor may be used to lowpass filter a noisy supply.
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to lowpass filter the reference voltage. If the reference
voltage originates from an op amp, be careful that the op amp
can drive the bypass capacitor without oscillation (the series
resistor can help in this case). Keep in mind that while the
ADS7822 draws very little current from the reference on
average, there are still instantaneous current demands placed
on the external reference circuitry.
Also, keep in mind that the ADS7822 offers no inherent
rejection of noise or voltage variation in regards to the
reference input. This is of particular concern when the
reference input is tied to the power supply. Any noise and
ripple from the supply will appear directly in the digital
results. While high frequency noise can be filtered out as
described in the previous paragraph, voltage variation due to
the line frequency (50Hz or 60Hz), can be difficult to
remove.
The GND pin on the ADS7822 should be placed on a clean
ground point. In many cases, this will be the “analog”
ground. Avoid connecting the GND pin too close to the
grounding point for a microprocessor, microcontroller, or
digital signal processor. If needed, run a ground trace directly
from the converter to the power supply connection point. The
ideal layout will include an analog ground plane for the
converter and associated analog circuitry.
APPLICATION CIRCUITS
Figures 6 and 7 show some typical application circuits for
the ADS7822. Figure 6 uses an ADS7822 and a multiplexer
to provide for a flexible data acquisition circuit. A resistor
string provides for various voltages at the multiplexer input.
The selected voltage is buffered and driven into VREF. As
shown in Figure 6, the input range of the ADS7822 is
programmable to 100mV, 200mV, 300mV, or 400mV. The
100mV range would be useful for sensors such as the
thermocouple shown.
Figure 7 shows a basic data acquisition system. The ADS7822
input range is 0V to VCC, as the reference input is connected
directly to the power supply. The 5Ω resistor and 1µF to
10µF capacitor filter the microcontroller “noise” on the
supply, as well as any high-frequency noise from the supply
itself. The exact values should be picked such that the filter
provides adequate rejection of the noise.
ADS7822
SBAS062A
www.ti.com
13
+3V
+3V
+3V
R8
26kΩ
R1
150kΩ
D1
TC1
R9
1kΩ
OPA237
C2
0.1µF
R3
500kΩ
R2
59kΩ
0.4V
R7
5Ω
R6
1MΩ
0.3V
U2
C1
10µF
VREF
MUX
0.2V
DCLOCK
C3
0.1µF
TC2
ADS7822
DOUT
A0
CS/SHDN
A1
Thermocouple
TC3
R4
1kΩ
R10
1kΩ
U1
C4
10µF
ISO Thermal Block
U3
C5
0.1µF
R5
500Ω
R11
1kΩ
0.1V
R12
1kΩ
µP
3-Wire
Interface
U4
FIGURE 6. Thermocouple Application Using a MUX to Scale the Input Range of the ADS7822.
+2.7V to +3.6V
5Ω
+ 1µF to
10µF
ADS7822
VREF
VCC
0.1µF
+In
CS
–In
DOUT
GND
+ 1µF to
10µF
Microcontroller
DCLOCK
FIGURE 7. Basic Data Acquisition System.
14
ADS7822
www.ti.com
SBAS062A
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS7822E/250
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822E/2K5
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822E/2K5G4
ACTIVE
MSOP
DGK
8
2500
TBD
CU NIPDAU
Level-1-220C-UNLIM
ADS7822EB/250
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822EB/250G4
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822EB/2K5
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822EB/2K5G4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822EC/250
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822EC/2K5
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822EC/2K5G4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
ADS7822P
ACTIVE
PDIP
P
8
50
TBD
Call TI
Level-NA-NA-NA
ADS7822PB
ACTIVE
PDIP
P
8
50
TBD
Call TI
Level-NA-NA-NA
ADS7822PC
ACTIVE
PDIP
P
8
50
TBD
Call TI
Level-NA-NA-NA
ADS7822U
ACTIVE
SOIC
D
8
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822U/2K5
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822U/2K5G4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822UB
ACTIVE
SOIC
D
8
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822UB/2K5
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822UC
ACTIVE
SOIC
D
8
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822UC/2K5
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822UC/2K5G4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS7822UG4
ACTIVE
SOIC
D
8
100
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
Addendum-Page 1
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2005
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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