High Speed Super Low Power SRAM CS18LV10245 128K-Word By 8 Bit DESCRIPTION The CS18LV10245 is a high performance, high speed and super low power CMOS Static Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of 4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed, super low power features and maximum access time of 55/70ns in 5V operation. Easy memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable (/OE). The CS18LV10245 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV10245 is available in JEDEC standard 32-pin sTSOP - I (8x13.4 mm), TSOP - I (8x20mm), SOP (450 mil) and PDIP (600 mil) packages. FEATURES 1. Fully static operation and Tri-state output 2. TTL compatible inputs and outputs 3. Ultra low power consumption : z 2.0V (min) data retention z Low operation voltage : 4.5 ~ 5.5V ; 5mA＠1MHz (Max.) operating current (Vcc = 5.0V) 0.50uA, (Typical value @ Vcc = 5.0V, TA = 25 0C) 4. Standby Typ. = 5. Standard pin configuration z 32 - SOP 450mil z 32 - sTSOP-I - 8X13.4mm z 32 - TSOP-I z 32 - PDIP 600mil 8X20mm Product Family Part No. Operating Temp Vcc. Range Speed (ns) Standby (Typ.) CS18LV10245CC CS18LV10245DC CS18LV10245EC 32 SOP 32 STSOP 32 TSOP (I) 4.5 ~ 5.5 CS18LV10245CI CS18LV10245EI 0.50uA 0~70oC CS18LV10245LC CS18LV10245DI Package Type -40~85oC CS18LV10245LI 32 PDIP 55/70 32 SOP 0.80uA 32 STSOP 32 TSOP (I) 32 PDIP Note: Green package part no, sees order information. Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P1 High Speed Super Low Power SRAM 128K-Word By 8 Bit CS18LV10245 PIN CONFIGURATIONS 32 SOP 450 mil 32 PDIP 600 mil 32 STSOP 8x13.4mm 32 TSOP(I) 8x20mm BLOCK DIAGRAM Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P2 High Speed Super Low Power SRAM CS18LV10245 128K-Word By 8 Bit PIN DESCRIPTIONS Name Function A0-A16 Address Input These 17 address inputs select one of the 131,072 x 8-bit words in the RAM. /CE Chip Enable Input CE2 Chip Enable 2 Input /CE is active LOW and CE2 is active HIGH. Both chip enables must be active /WE Write Enable Input The write enable input is active LOW and controls read and write operations. when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. With the chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins; when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. /OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive. DQ0-DQ7 Data Input/Output Ports These 8 bi-directional ports are used to read data from or write data into the Vcc Power Supply Gnd Ground RAM. TRUTH TABLE MODE /WE /CE CE2 /OE Not Selected X H X X X X L X Output Disabled H L H Read H L Write L L Copyright DQ0~7 Vcc Current High Z ICCSB, ICCSB1 H High Z ICC H L DOUT ICC H X DIN ICC 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P3 High Speed Super Low Power SRAM CS18LV10245 128K-Word By 8 Bit ABSOLUTE MAXIMUM RATINGS (1) Symbol VTERM TBIAS Parameter Rating Terminal Voltage with Respect to GND Unit -0.5 to Vcc+0.5 Temperature Under Bias V -40 to +125 O -60 to +150 O C TSTG Storage Temperature PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA C Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Ambient Temperature o Commercial 0~70 C 4.5V ~5.5V o Industrial Vcc -40~85 C 4.5V ~ 5.5V CAPACITANCE (1) (TA = 25oC, f =1.0 MHz) Symbol Parameter Conditions MAX. Unit CIN Input Capacitance VIN=0V 6 pF CDQ Input/Output Capacitance VI/O=0V 8 pF 1. This parameter is guaranteed and not tested. Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P4 High Speed Super Low Power SRAM CS18LV10245 128K-Word By 8 Bit DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC ) Parameter Parameter Test Conduction MIN TYP(1) MAX Name VIL Guaranteed Input Low Voltage VIH -0.5 0.8 V 2.0 Vcc+0.2 V (2) Guaranteed Input High Voltage Unit (2) IIL Input Leakage Current VCC=MAX, VIN=0 to VCC 1 uA IOL Output Leakage VCC=MAX, /CE=VIN, or 1 uA Current /OE=VIN , VIO=0V to VCC VOL Output Low Voltage VCC=MAX, IOL = 2mA 0.4 V VOH Output High Voltage VCC=MIN, IOH = -1mA ICC Operating Power /CE=VIL, IDQ=0mA, F=FMAX 2.4 V (3) 35 mA 2 mA 10 uA Supply Current ICCSB Standby Supply - TTL /CE=VIH, IDQ=0mA, ICCSB1 Standby Current /CE≧VCC-0.2V, VIN≧ -CMOS VCC-0.2V or VIN≦0.2V 0.3 o 1. Typical characteristics are at TA = 25 C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC. DATA RETENTION CHARACTERISTICS ( TA = 0 to +70oC ) Parameter Name VRD ICCDR TCDR tR Parameter VCC for Data Retention Test Conduction /CE≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V Data Retention Current MIN 1.5 /CE≧VCC-0.2V, Retention Time See Retention Waveform Operation Recovery Time V 0.2 VIN≧VCC-0.2V or VIN≦0.2V Chip Deselect to Data TYP(1) MAX Unit 2.0 uA 0 ns tRC (2) ns o 1. Vcc = 3.0V, TA = + 25 C. 2. tRC= Read Cycle Time. Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P5 High Speed Super Low Power SRAM CS18LV10245 128K-Word By 8 Bit LOW Vcc DATA RETENTION WAVEFORM(1) ( /CE Controlled ) LOW Vcc DATA RETENTION WAVEFORM(2) ( CE2 Controlled ) KEY TO SWITCHING WAVEFORMS WAFEFORM INPUTS OUTPUTS Must be standby Must be standby May change for H to L Will be change from H to L May change for L to H May change for L to H Don’t care any change permitted Change state unknown Does not apply Center line is high impedance “OFF” state AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Vcc/0V 5ns Input and Output Timing Reference Level Copyright 0.5Vcc 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P6 High Speed Super Low Power SRAM CS18LV10245 128K-Word By 8 Bit AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V ) < READ CYCLE > JEDEC Parameter Parameter Name Name Description -55 -70 MIN MAX MIN Unit MAX tAVAX tRC Read Cycle Time tAVQV tAA Address Access Time 55 70 ns tELQV tACS1 Chip Select Access Time (/CE) 55 70 ns tELQV tACS2 Chip Select Access Time (CE2) 55 70 ns tGLQV tOE Output Enable to Output Valid 20 30 ns tE1LQX tCLZ1 Chip Select to Output Low Z (/CE) 10 10 ns tE2LOX tCLZ2 Chip Select to Output Low Z (CE2) 10 10 ns tGLQX tOLZ Output Enable to Output in Low Z 5 5 ns tEHQZ tCHZ1 Chip Deselect to Output in High Z (/CE) 0 25 0 30 ns tEHQZ tCHZ2 Chip Deselect to Output in High Z (CE2) 0 25 0 30 ns tGHQZ tOHZ Output Disable to Output in High Z 0 25 0 30 ns tAXOX tOH Out Disable to Address Change 10 Copyright 55 70 10 2004 March Chiplus Semiconductor Corp. All rights reserved. . ns ns Rev. 1.2 P7 High Speed Super Low Power SRAM 128K-Word By 8 Bit CS18LV10245 NOTES: 1. /WE is high in read Cycle. 2. Device is continuously selected when /CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. /OE = VIL. 5. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE (1,2,4) READ CYCLE (1,3,4) READ CYCLE (1,4) Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P8 High Speed Super Low Power SRAM CS18LV10245 128K-Word By 8 Bit AC ELECTRICAL CHARACTERISTICS ( TA = 0~70oC , Vcc = 5.0V ) < WRITE CYCLE > JEDEC Parameter Parameter Name Name Description -55 -70 MIN MAX MIN Unit MAX tAVAX tWC Write Cycle Time 55 70 ns tE1LWH tCW Chip Select to End of Write 55 70 ns tAVWL tAS Address Setup Time 0 0 ns tAVWH tAW Address Valid to End of Write 55 70 ns tWLWH tWP Write Pulse Width 55 70 ns tWHAX tWR Write Recovery Time (/CE, /WE) 0 0 ns tE2LAX tWR2 Write Recovery Time (CE2, ) 0 0 ns tWLQZ tWHZ Write to Output in High Z 0 tDVWH tDW Data to Write Time Overlap 25 25 ns tWHDX tDH Data Hold from Write Time 0 0 ns tWHOX tOW End of Write to Output Active 5 5 ns Copyright 20 0 2004 March Chiplus Semiconductor Corp. All rights reserved. . 25 ns Rev. 1.2 P9 High Speed Super Low Power SRAM 128K-Word By 8 Bit CS18LV10245 SWITCHING WAVEFORMS (WRITE CYCLE) Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P 10 High Speed Super Low Power SRAM 128K-Word By 8 Bit CS18LV10245 NOTES: 1. TAS is measured from the address valid to the beginning of write. 2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of /CE or /WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output remain in a high impedance state. Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P 11 High Speed Super Low Power SRAM 128K-Word By 8 Bit CS18LV10245 6. 7. 8. 9. /OE is continuously low (/OE = VIL ). DOUT is the same phase of write data of this write cycle. DOUT is the read data of next address. If /CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of /CE going low to the end of write. Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P 12 High Speed Super Low Power SRAM CS18LV10245 128K-Word By 8 Bit ORDER INFORMATION 1. NON-GREEN PACKAGE: CS18LV10245 X X - XX Package: C: 32SOP (450mil) D: 32STSOP I (8x13.4mm) E: 32TSOP I (8x20mm) L: 32PDIP (600mil) Speed: 55: 55NS 70: 70ns Grade: C: 0~70°C I: -40~85°C 2. GREEN PACKAGE: CS18LV10245 X X X XX Package: C: 32SOP (450mil) D: 32STSOP I (8x13.4mm) E: 32TSOP I (8x20mm) Grade: C: 0~70°C I: -40~85°C Speed: 55: 55ns 70: 70ns Green Code A: Pb Free + Halogen Free (SOP / TSOP Types) Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P 13 High Speed Super Low Power SRAM CS18LV10245 128K-Word By 8 Bit PACKAGE DIMENSIONS - 32 pin SOP (450 mil) : b WITH PLATING c c1 b1 BASE METAL SECTION A-A SYMBOL b1 c Nom. 2.821 0.229 2.680 0.35 _ 0.15 _ 0.15 20.320 11.176 13.792 1.118 _ 20.447 11.303 14.097 1.270 Max. 2.997 0.356 2.820 0.50 0.46 0.32 0.28 20.574 11.430 14.402 1.422 1.084 1.600 Min. mm e b 0.35 _ A UNIT Min. A1 A2 2.645 0.102 2.540 c1 D E E1 L 0.104 0.004 0.1000 0.014 0.014 0.006 0.006 0.800 0.440 0.543 0.044 _ _ _ _ 0.805 0.445 0.555 0.050 inch Nom. 0.111 0.009 0.1055 Max. 0.118 0.014 0.1110 0.020 - 0.018 0.012 0.011 0.810 0.450 0.567 0.056 y L1 0.584 1.194 _ 0.834 1.397 _ 0.023 0.047 0.1 _ 0.033 0.055 _ 0.043 0° _ 10° 0° _ 10° 0.063 0.004 32 pin STSOP I ( 8x13.4 mm) : 12°(2x) 12°(2x) e HD cL 32 16 17 b E 1 Seating Plane y 12°(2X) "A" D A2 A GAUGE PLANE 0 A1 17 16 SEATING PLANE 0.254 A A L 12°(2X) L1 "A" DATAIL VIEW b WITH PLATING c c1 1 32 b1 BASE METAL SECTION A-A SYMBOL A A1 A2 b b1 c c1 D E e HD L L1 y 1.00 0.05 0.95 0.17 0.17 7.90 0.40 13.20 0.40 0.70 _ 0.10 1.00 0.22 0.20 0.10 _ 11.70 Nom. 1.10 0.10 _ 11.80 8.00 0.50 13.40 0.50 0.80 _ 1.20 8.10 0.60 13.60 0.70 0.90 UNIT Min. mm 0.15 1.05 0.27 0.23 0.21 0.16 11.90 Min. 0.0393 0.002 0.037 0.007 0.007 0.520 0.0157 0.0275 0.1 _ 0.009 0.008 0.004 _ 0.311 0.016 0.039 0.004 _ 0.461 Nom. 0.0433 0.004 0.465 0.315 0.020 0.528 0.0197 0.0315 _ Max. 0.0473 0.006 0.041 0.011 0.009 0.008 0.006 0.469 0.319 0.024 0.536 0.0277 0.0355 0.004 Max. inch 0° _ 8° 0° _ 8° - Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P 14 High Speed Super Low Power SRAM CS18LV10245 128K-Word By 8 Bit 12°(2X) 32 pin TSOP(I) ( 8x20mm) 12°(2X) - e HD 16 17 b 32 E CL 1 Seating Plane y 12°(2x) A A2 "A" D GAUGE PLANE 0 0.254 A A1 SEATING PLANE A 12°(2x) L L1 "A" DETAIL VIEW 17 16 b WITH PLATING c c1 1 b1 BASE METAL 32 SECTION A-A SYMBOL A A1 A2 b b1 c c1 D E e HD L L1 y 1.00 0.05 0.95 0.17 0.17 7.90 0.40 19.80 0.40 0.70 _ 0.10 1.00 0.22 0.20 0.10 _ 18.30 Nom. 1.10 0.10 _ 18.40 8.00 0.50 20.00 0.50 0.80 _ 1.20 0.15 1.05 0.27 0.23 0.21 0.16 18.50 8.10 0.60 20.20 0.70 0.90 Min. 0.0393 0.002 0.037 0.007 0.007 0.311 0.016 0.779 0.0157 0.0275 0.039 0.009 0.008 0.004 _ 0.720 Nom. 0.0433 0.004 0.004 _ 0.1 _ 0.724 0.315 0.020 0.787 0.0197 0.0315 _ Max. 0.0473 0.006 0.041 0.011 0.009 0.008 0.006 0.728 0.319 UNIT Min. mm Max. inch - 0.024 0.795 0.0277 0.0355 0.004 0° _ 8° 0° _ 8° 32 pin PDIP ( 600 mil) SYMBOL A1 A2 Nom. 0.254 _ 3.912 Max. _ UNIT Min. mm inch Copyright B1 3.785 0.330 1.143 0.457 1.270 4.039 0.584 1.397 0.010 0.149 _ 0.154 Nom. _ 0.159 Max. Min. B c D E E1 e eB L S Q1 16.002 3.048 1.651 1.651 2.540 0.254 41.910 15.240 13.818 (TYP) 16.510 3.302 1.905 1.778 17.018 3.556 2.159 1.905 0.356 42.037 15.494 13.920 0.152 41.783 14.986 13.716 0.013 0.045 0.006 1.645 0.590 0.018 0.050 0.010 1.650 0.600 0.023 0.055 0.014 1.655 0.610 0.540 0.630 0.100 0.544 (TYP) 0.650 0.670 0.548 0.120 0.065 0.130 0.075 0.070 0.065 0.140 0.085 0.075 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P 15