FEATURES
10-Bit Dual Muxed Port DAC
300 MSPS Output Update Rate
Excellent SFDR and IMD Performance
SFDR to Nyquist @ 25 MHz Output: 64 dB
Internal Clock Doubling PLL
Differential or Single-Ended Clock Input
On-Chip 1.2 V Reference
Single 3.3 V Supply Operation
Power Dissipation: 155 mW @ 3.3 V
48-Lead LQFP
APPLICATIONS
Communications: LMDS, LMCS, MMDS
Base Stations
Digital Synthesis
QAM and OFDM
PRODUCT DESCRIPTION
The AD9751 is a dual muxed port, ultrahigh-speed, singlechannel, 10-bit CMOS DAC. It integrates a high-quality 10-bit
TxDAC+ core, a voltage reference, and digital interface circuitry
into a small 48-lead LQFP package. The AD9751 offers exceptional ac and dc performance while supporting update rates up
to 300 MSPS.
The AD9751 has been optimized for ultrahigh-speed applications up to 300 MSPS where data rates exceed those possible on
a single data interface port DAC. The digital interface consists
of two buffered latches as well as control logic. These latches
can be time multiplexed to the high-speed DAC in several ways.
This PLL drives the DAC latch at twice the speed of the externally applied clock and is able to interleave the data from the
two input channels. The resulting output data rate is twice that
of the two input channels. With the PLL disabled, an external
2× clock may be supplied and divided by two internally.
The CLK inputs (CLK+/CLK–) can be driven either differentially or single-endedly, with a signal swing as low as 1 V p-p.
FUNCTIONAL BLOCK DIAGRAM
DVDD
PORT1
DCOM
LATCH
MUX
PORT2
CLK+
CLK–
CLKVDD
PLLVDD
CLKCOM
LATCH
PLL
CLOCK
MULTIPLIER
AVDD
ACOM
DAC LATCH
a
10-Bit, 300 MSPS
High-Speed TxDAC+® D/A Converter
AD9751*
DAC
IOUTA
IOUTB
REFERENCE
REFIO
FSADJ
AD9751
RESET LPF DIV0 DIV1 PLLLOCK
The DAC utilizes a segmented current source architecture combined with a proprietary switching technique to reduce glitch
energy and to maximize dynamic accuracy. Differential current
outputs support single-ended or differential applications. The
differential outputs each provide a nominal full-scale current
from 2 mA to 20 mA.
The AD9751 is manufactured on an advanced low cost 0.35 µm
CMOS process. It operates from a single supply of 3.1 V to 3.5 V
and consumes 155 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9751 is a member of a pin-compatible family of highspeed TxDAC+s providing 10-, 12-, and 14-bit resolution.
2. Ultrahigh-Speed 300 MSPS Conversion Rate.
3. Dual 10-Bit Latched, Multiplexed Input Ports. The AD9751
features a flexible digital interface allowing high-speed data
conversion through either a single or dual port input.
4. Low Power. Complete CMOS DAC function operates on
155 mW from a 3.1 V to 3.5 V single supply. The DAC fullscale current can be reduced for lower power operation.
5. On-Chip Voltage Reference. The AD9751 includes a 1.20 V
temperature-compensated bandgap voltage reference.
TxDAC+ is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patent numbers 5450084, 5568145, 5689257 and 5703519.
Other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD9751–SPECIFICATIONS
(T to T , AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, CLKVDD = 3.3 V, I
DC SPECIFICATIONS
MIN
MAX
OUTFS
= 20 mA, unless otherwise
noted.)
Parameter
Min
RESOLUTION
Typ
Max
10
Unit
Bits
1
DC ACCURACY
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
–1
–0.5
± 0.3
± 0.2
+1
+0.5
LSB
LSB
–0.025
–5
–7
2.0
–1.0
± 0.01
± 0.5
± 0.25
+0.025
+2
+2
20.0
1.25
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
1.26
V
nA
1.25
1
V
MΩ
0
± 50
± 100
± 50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
100
5
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
1.14
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
0.1
1.20
100
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
PLLVDD
CLKVDD
Analog Supply Current (IAVDD)4
Digital Supply Current (IDVDD)4
PLL Supply Current (IPLLVDD)4
Clock Supply Current (ICLKVDD)4
Power Dissipation4 (3 V, IOUTFS = 20 mA)
Power Dissipation5 (3 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio6—AVDD
Power Supply Rejection Ratio6—DVDD
OPERATING RANGE
3.0
3.0
3.0
3.0
3.3
3.3
3.3
3.3
33
3.5
4.5
10.0
155
216
3.6
3.6
3.6
3.6
36
4.5
5.1
11.5
165
–0.1
–0.04
+0.1
+0.04
V
V
V
V
mA
mA
mA
mA
mW
mW
% of FSR/V
% of FSR/V
–40
+85
°C
NOTES
1
Measured at I OUTA, driving a virtual ground.
2
Nominal full-scale current, I OUTFS, is 32× the IREF current.
3
An external buffer amplifier is recommended to drive any external load.
4
100 MSPS fDAC with PLL on, fOUT = 1 MHz, all supplies = 3.0 V.
5
300 MSPS fDAC.
6
± 5% power supply variation.
Specifications subject to change without notice.
–2–
REV. 0
AD9751
(TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, CLKVDD = 3.3 V, IOUTFS = 20 mA,
DYNAMIC SPECIFICATIONS Differential Transformer Coupled Output, 50 ⍀ Doubly Terminated, unless otherwise noted.)
Parameter
Min
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fDAC)
Output Settling Time (tST) (to 0.1%)1
Output Propagation Delay (tPD)1
Glitch Impulse1
Output Rise Time (10% to 90%)1
Output Fall Time (90% to 10%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
Max
300
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fDAC = 100 MSPS; fOUT = 1.00 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
fDATA = 65 MSPS; fOUT = 1.1 MHz2
fDATA = 65 MSPS; fOUT = 5.1 MHz2
fDATA = 65 MSPS; fOUT = 10.1 MHz2
fDATA = 65 MSPS; fOUT = 20.1 MHz2
fDATA = 65 MSPS; fOUT = 30.1 MHz2
fDAC = 200 MSPS; fOUT = 1.1 MHz
fDAC = 200 MSPS; fOUT = 11.1 MHz
fDAC = 200 MSPS; fOUT = 31.1 MHz
fDAC = 200 MSPS; fOUT = 51.1 MHz
fDAC = 200 MSPS; fOUT = 71.1 MHz
fDAC = 300 MSPS; fOUT = 1.1 MHz
fDAC = 300 MSPS; fOUT = 26.1 MHz
fDAC = 300 MSPS; fOUT = 51.1 MHz
fDAC = 300 MSPS; fOUT = 101.1 MHz
fDAC = 300 MSPS; fOUT = 141.1 MHz
Spurious-Free Dynamic Range within a Window
fDAC = 100 MSPS; fOUT = 1 MHz; 2 MHz Span
0 dBFS
fDAC = 65 MSPS; fOUT = 5.02 MHz; 2 MHz Span
fDAC = 150 MSPS; fOUT = 5.04 MHz; 4 MHz Span
Total Harmonic Distortion
fDAC = 100 MSPS; fOUT = 1.00 MHz
0 dBFS
fDAC = 65 MHz; fOUT = 2.00 MHz
fDAC = 150 MHz; fOUT = 2.00 MHz
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
fDAC = 65 MSPS; fOUT = 2.00 MHz to 2.77 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
70
80
72
72
73
73
72
68
64
74
71
66
66
63
74
71
66
66
63
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
81
91
81
81
dBc
dBc
dBc
69
67
65
–3–
Unit
11
1
5
2.5
2.5
50
30
–80
–72
–72
NOTES
1
Measured single-ended into 50 Ω load.
2
Single-Port Mode (PLL disabled, DIV0 = 1, DIV1 = 0, data on Port 1).
Specifications subject to change without notice.
REV. 0
Typ
–69
dBc
dBc
dBc
dBc
dBc
dBc
AD9751–SPECIFICATIONS
(TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless
DIGITAL SPECIFICATIONS otherwise noted.)
Parameter
DIGITAL INPUTS
Logic “1”
Logic “0”
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Input Setup Time (tS, PLLVDD = 0 V)
Input Hold Time (tH, PLLVDD = 0 V))
Min CLK Freq1
Min
Typ
2.1
3
0
Max
Unit
V
V
µA
µA
pF
ns
ns
ns
ns
MHz
0.9
+10
+10
–10
–10
5
0.5
0.5
–1.5
1.7
6.25
1.0
1.0
–1.0
2.5
ABSOLUTE MAXIMUM RATINGS*
Parameter
With Respect to
Min
Max
Unit
AVDD, DVDD, CLKVDD, PLLVDD
AVDD, DVDD, CLKVDD, PLLVDD
ACOM, DCOM, CLKCOM, PLLCOM
REFIO, REFLO, FSADJ
IOUTA, IOUTB
Digital Data Inputs (DB9 to DB0)
CLK+/CLK–, PLLLOCK
DIV0, DIV1, RESET
LPF
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
ACOM, DCOM, CLKCOM, PLLCOM
ACOM, DCOM, CLKCOM, PLLCOM
ACOM, DCOM, CLKCOM, PLLCOM
ACOM
ACOM
DCOM
CLKCOM
CLKCOM
PLLCOM
–0.3
–3.9
–0.3
–0.3
–1.0
–0.3
–0.3
–0.3
–0.3
+3.9
+3.9
+3.9
AVDD + 0.3
AVDD + 0.3
DVDD + 0.3
CLKVDD + 0.3
CLKVDD + 0.3
PLLVDD + 0.3
150
+150
300
V
V
V
V
V
V
V
V
V
°C
°C
°C
–65
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
tS
PORT 1
tH
ORDERING GUIDE
DATA X
Model
DATA IN
PORT 2
INPUT CLK
(PLL ENABLED)
1ⴛ CLOCK @ PLLLOCK
(PLL DISABLED)
Temperature
Range
Package
Description
Package
Option
AD9751AST –40°C to +85°C 48-Lead LQFP ST-48
AD9751-EB
Evaluation Board
DATA Y
t LPW
NOTE
Min CLK freq only applies when using internal PLL. When PLL is disabled, there
is no minimum CLK frequency.
t PD
DATA X
IOUTA OR IOUTB
t PD
Figure 1. I/O Timing
DATA Y
THERMAL CHARACTERISTIC
Thermal Resistance
48-Lead LQFP
θJA = 91°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9751 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD9751
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
2
3
4, 22
5, 21
6
7–16
17–20, 33–36
23–32
37, 38
39
40
41
42
43
44
45
46
47
48
RESET
CLK+
CLK–
DCOM
DVDD
PLLLOCK
P1B9–P1B0
RESERVED
P2B9–P2B0
DIV0, DIV1
REFIO
FSADJ
AVDD
IOUTB
IOUTA
ACOM
CLKCOM
LPF
PLLVDD
CLKVDD
Internal Clock Divider Reset
Differential Clock Input
Differential Clock Input
Digital Common
Digital Supply Voltage
PLL Lock Indicator Output
Data Bits P1B9 to P1B0, Port 1
Data Bits P2B9 to P2B0, Port 2
Control inputs for PLL and input port selector mode, see Tables I and II for details.
Reference Input/Output
Full-Scale Current Output Adjust
Analog Supply Voltage
Differential DAC Current Output
Differential DAC Current Output
Analog Common
Clock and Phase-Locked Loop Common
PLL Loop Filter
Phase-Locked Loop Supply Voltage
Clock Supply Voltage
DIV0
DIV1
REFIO
FSADJ
AVDD
IOUTB
IOUTA
ACOM
CLKCOM
LPF
PLLVDD
CLKVDD
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
RESET 1
36
RESERVED
35
RESERVED
CLK– 3
34
RESERVED
DCOM 4
33
RESERVED
DVDD 5
32
P2B0–LSB
31
P2B1
30
P2B2
29
P2B3
P1B7 9
28
P2B4
P1B6 10
27
P2B5
P1B5 11
26
P2B6
P1B4 12
25
P2B7
PIN 1
IDENTIFIER
CLK+ 2
PLLLOCK 6
AD9751
MSB–P1B9 7
TOP VIEW
(Not to Scale)
P1B8 8
REV. 0
–5–
P2B8
MSB–P2B9
DCOM
DVDD
RESERVED
RESERVED
RESERVED
RESERVED
LSB–P1B0
P1B1
P1B2
P1B3
13 14 15 16 17 18 19 20 21 22 23 24
RESERVED = NO
USER CONNECTIONS
AD9751
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Glitch Impulse
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Offset Error
Spurious-Free Dynamic Range
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s, minus the output when all inputs are set to 0s.
Signal-to-Noise Ratio (SNR)
S/N is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Adjacent Channel Power Ratio (or ACPR)
A ratio in dBc between the measured power within a channel
relative to its adjacent channel.
Temperature Drift
Specified as the maximum change from the ambient (25°C)
value to the value at either TMIN or TMAX. For offset and gain
drift, the drift is reported in ppm of full-scale range (FSR) per
degree C. For reference drift, the drift is reported in ppm per
degree C.
3.1V TO 3.5V
DVDD
1.2V REF
REFIO
PMOS CURRENT
SOURCE ARRAY
FSADJ
0.1F
AVDD
SEGMENTED
SWITCHES FOR
DB0 TO DB9
DAC
IOUTB
PLL
CIRCUITRY
2 -1 MUX
DCOM
AD9751
PORT 1 LATCH
PORT 2 LATCH
DB0 – DB9
DB0 – DB9
50⍀
PLLVDD
CLKVDD
RESET
LPF
CLKCOM
DIV0
DIV1
DAC LATCH
RSET
2k⍀
MINI
CIRCUITS
T1-1T
IOUTA
TO ROHDE
AND
SCHWARZ
FSEA30
SPECTRUM
ANALYZER
50⍀
ACOM
CLK+ CLK–
PLLLOCK
DIGITAL DATA INPUTS
1k⍀
3.1V TO 3.5V
TEKTRONIX DG2020
OR
AWG2021 w/OPTION 4
MINI
CIRCUITS
T1-1T
LECROY 9210
PULSE GENERATOR
(FOR DATA RETIMING)
1k⍀
HP8644
SIGNAL
GENERATOR
Figure 2. Basic AC Characterization Test Setup
–6–
REV. 0
Typical Performance Characteristics–AD9751
90
90
90
0dBmFS
80
0dBmFS
80
80
70
–6dBmFS
–12dBmFS
60
60
50
50
5
10
15
20
fOUT – MHz
25
30
90
90
80
80
SFDR – dBc
200MSPS
70
60
10
20
30 40 50 60 70
fOUT – MHz
80 90 100
TPC 2. Single-Tone SFDR vs. fOUT
@ fDAC = 200 MSPS
TPC 1. Single-Tone SFDR vs. fOUT @
fDAC = 65 MSPS; Single Port Mode
–6dBmFS
60
0dBmFS
40
0
35
0
20
40
60
80 100 120 140 160
fOUT – MHz
TPC 3. Single-Tone SFDR vs. fOUT @
fDAC = 300 MSPS
90
SFDR NEAR CARRIERS
(2F1-F2, 2F2-F1)
80
SFDR – dBc
0
–12dBmFS
70
50
40
40
SFDR – dBc
–12dBmFS
70
SFDR – dBc
SFDR – dBc
SFDR – dBc
–6dBmFS
70
SFDR OVER
NYQUIST BAND
60
SFDR NEAR CARRIERS
(2F1-F2, 2F2-F1)
70
60
65MSPS
50
50
SFDR OVER NYQUIST BAND
50
300MSPS
40
0
40
20
40
60
80
fOUT – MHz
100
120
40
0
140
10
20
30 40 50 60 70
fOUT – MHz
80 90 100
0
40
60
80 100 120 140 160
fOUT – MHz
TPC 4. SFDR vs. fOUT @ 0 dBFS
TPC 5. Two-Tone IMD vs. fOUT @
fDAC = 200 MSPS, 1 MHz Spacing
between Tones, 0 dBFS
TPC 6. Two-Tone IMD vs. fOUT @
fDAC = 300 MSPS, 1 MHz Spacing
between Tones, 0 dBFS
90
90
90
80
80
18.18/19.18MHz
@ 200MSPS
11.82MHz @ 130MSPS
80
18.18MHz @ 200MSPS
70
60
27.27MHz @ 300MSPS
SFDR – dBc
SFDR – dBc
40MHz @ 200MSPS
SFDR – dBc
20
70
26MHz @ 130MSPS
60
27.27/28.27MHz
@ 300MSPS
70
11.82/12.82MHz
@ 130MSPS
60
60MHz @ 300MSPS
40
–16 –14 –12 –10 –8
–6
AOUT – dB
–4
–2
0
TPC 7. Single-Tone SFDR vs. AOUT @
fOUT = fDAC /11
REV. 0
50
50
50
40
–16 –14 –12 –10 –8
–6
AOUT – dBm
–4
–2
0
TPC 8. Single-Tone SFDR vs. AOUT
@ fOUT = fDAC /5
–7–
40
–20 –18 –16 –14 –12 –10 –8 –6 –4
AOUT – dBm
–2
0
TPC 9. Two-Tone IMD (Third Order
Products) vs. AOUT @ fOUT = fDAC /11
AD9751
90
18.18/19.18MHz
@ 200MSPS
80
60/61MHz
@ 300MSPS
SFDR – dBc
70
11.82/12.82MHz
@ 130MSPS
60
27.27/28.27MHz
@ 300MSPS
50
80
70
40/41MHz
@ 200MSPS
60
50
40
–20 –18 –16 –14 –12 –10 –8 –6 –4
AOUT – dBm
–2
–2
75
85
70
SFDR – dBc
70
65
75
60
55
IOUTFS = 10mA
50
50
150
200
fDAC – MHz
250
0
300
TPC 13. SINAD vs. fDAC @ fOUT =
10 MHz, 0 dBFS
20
40
60
80 100 120 140
fOUT – MHz
65
40MHz
60
55
80MHz
120MHz
40
–50
160
TPC 14. SFDR vs. IOUTFS, fDAC =
300 MSPS @ 0 dBFS
0.10
10MHz
45
40
100
–30
fDAC = 300MSPS
fOUT1 = 24MHz
fOUT2 = 25MHz
fOUT3 = 26MHz
fOUT4 = 27MHz
fOUT5 = 28MHz
fOUT6 = 29MHz
fOUT7 = 30MHz
fOUT8 = 31MHz
SFDR = 58dBc
MAGNITUDE = 0dBFS
–0.10
AMPLITUDE – dBm
DNL – LSB
INL – LSB
–20
0.14
–0.05
90
70
0
–10
0
–10
10
30
50
TEMPERATURE – ⴗC
TPC 15. SFDR vs. Temperature,
fDAC = 300 MSPS @ 0 dBFS
0.18
0.05
0
50
45
55
–2
70
IOUTFS = 5mA
50
60
60/61MHz
@ 300MSPS
80
65
75
60
TPC 12. Two-Tone IMD (to Nyquist)
vs. AOUT @ fOUT = fDAC/5
IOUTFS = 20mA
80
40/41MHz
@ 200MSPS
40
–20 –18 –16 –14 –12 –10 –8 –6 –4
AOUT – dBm
0
TPC 11. Two-Tone IMD (Third Order
Products) vs. AOUT @ fOUT = fDAC /5
90
26/27MHz
@ 130MSPS
70
50
40
–20 –18 –16 –14 –12 –10 –8 –6 –4
AOUT – dBm
0
TPC 10. Two-Tone IMD (to Nyquist)
vs. AOUT @ fOUT = fDAC /11
SINAD – dBm
26/27MHz
@ 130MSPS
SFDR – dBc
SFDR – dBc
80
90
SFDR – dBc
90
0.10
0.06
–30
–40
–50
–60
–70
–80
0.02
–90
–0.15
–100
–0.02
0
127 255 383
511 639 767 895 1024
CODE
TPC 16. Typical INL
0
127 255 383 511 639 767 895 1024
CODE
TPC 17. Typical DNL
–8–
0
20
80 100 120
40
60
FREQUENCY – MHz
140
TPC 18. Eight-Tone SFDR @ fOUT 艐
fDAC /11, fDAC = 300 MSPS
REV. 0
AD9751
FUNCTIONAL DESCRIPTION
REFERENCE OPERATION
Figure 3 shows a simplified block diagram of the AD9751. The
AD9751 consists of a PMOS current source array capable of
providing up to 20 mA of full-scale current, IOUTFS. The array is
divided into 31 equal sources that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of
15 equal current sources whose value is 1/16th of an MSB current source. The remaining LSB is a binary weighted fraction of
the middle bit current sources. Implementing the middle and
lower bits with current sources, instead of an R-2R ladder,
enhances dynamic performance for multitone or low-amplitude
signals and helps maintain the DAC’s high output impedance
(i.e., >100 kΩ).
The AD9751 contains an internal 1.20 V bandgap reference.
This can easily be overdriven by an external reference with no
effect on performance. REFIO serves as either an input or output,
depending on whether the internal or an external reference is
used. To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1 µF capacitor. The internal reference
voltage will be present at REFIO. If the voltage at REFIO is to
be used elsewhere in the circuit, an external buffer amplifier with
an input bias current less than 100 nA should be used. An example
of the use of the internal reference is given in Figure 4.
A low impedance external reference can be applied to REFIO
as shown in Figure 5. The external reference may provide either
a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that
the 0.1 µF compensation capacitor is not required since the internal reference is overdriven, and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
All of the current sources are switched to one or the other of the
two outputs (i.e., IOUTA or IOUTB) via PMOS differential current
switches. The switches are based on a new architecture that
drastically improves distortion performance. This new switch
architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential
current switches.
REFERENCE CONTROL AMPLIFIER
The analog and digital sections of the AD9751 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.1 V to 3.5 V range. The digital section,
which is capable of operating at a 300 MSPS clock rate, consists
of edge-triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the
associated differential switches, a 1.20 V bandgap voltage reference and a reference control amplifier.
The AD9751 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a voltage-to-current converter as shown in Figure 4, so that its current output, IREF, is
determined by the ratio of VREFIO and an external resistor, RSET,
as stated in Equation 4. IREF is applied to the segmented current
sources with the proper scaling factor to set IOUTFS as stated in
Equation 3.
The full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, RSET. The external resistor, in combination
with both the reference control amplifier and voltage reference
VREFIO, sets the reference current IREF, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, IOUTFS, is 32 times the value of IREF.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between
62.5 µA and 625 µA. The wide adjustment span of IOUTFS provides
several application benefits. The first benefit relates directly to
the power dissipation of the AD9751, which is proportional to
IOUTFS (refer to the Power Dissipation section). The second
benefit relates to the 20 dB adjustment, which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency, small
signal multiplying applications.
3.1V TO 3.5V
DVDD
1.2V REF
REFIO
PMOS CURRENT
SOURCE ARRAY
FSADJ
0.1F
VDIFF = VOUTA – VOUT B
AVDD
SEGMENTED
SWITCHES FOR
DB0 TO DB9
IOUTA
DAC
DAC LATCH
RSET
2k⍀
PLL
CIRCUITRY
2 -1 MUX
DCOM
IOUTB
AD9751
PORT 1 LATCH
PORT 2 LATCH
ACOM
DB0 – DB9
DB0 – DB9
DIGITAL DATA INPUTS
DIV0 DIV1 PLLLOCK
Figure 3. Simplified Block Diagram
REV. 0
–9–
PLLVDD
CLKVDD
CLK+
CLK–
CLKCOM
RESET
LPF
VOUT A
VOUT B
RLOAD
50⍀
RLOAD
50⍀
AD9751
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
tS
AVDD
AD9751
REFERENCE
SECTION
PORT 1
1.2V REF
IREF
PORT 2
CURRENT
SOURCE
ARRAY
FSADJ
0.1F
DATA X
DATA IN
REFIO
ADDITIONAL
EXTERNAL
LOAD
tH
2k⍀
DATA Y
CLK
t LPW
Figure 4. Internal Reference Configuration
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
IOUTA OR IOUTB
DATA Y
1/2 CYCLE + t PD
AVDD
AD9751
t PD
DATA X
7a.
REFERENCE
SECTION
1.2V REF
PORT 1
REFIO
ADDITIONAL
EXTERNAL
LOAD
0.1F
CURRENT
SOURCE
ARRAY
FSADJ
DATA Y
DATA X
DATA Z
DATA IN
PORT 2
IREF
DATA W
2k⍀
CLK
Figure 5. External Reference Configuration
PLL CLOCK MULTIPLIER OPERATION
XXX
IOUTA OR IOUTB
DATA W
The Phase Locked Loop (PLL) is intrinsic to the operation of the
AD9751 in that it produces the necessary internally synchronized
2× clock for the edge-triggered latches, multiplexer, and DAC.
With PLLVDD connected to its supply voltage, the AD9751 is
in PLL ACTIVE mode. Figure 6 shows a functional block diagram of the AD9751 clock control circuitry with PLL active.
The circuitry consists of a phase detector, charge pump, voltage
controlled oscillator (VCO), input data rate range control, clock
logic circuitry, and control input/outputs. The ÷ 2 logic in the
feedback loop allows the PLL to generate the 2× clock needed
for the DAC output latch.
Figure 7 defines the input and output timing for the AD9751
with the PLL active. CLK in Figure 7 represents the clock that
is generated external to the AD9751. The input data at both
ports 1 and 2 is latched on the same CLK rising edge. CLK may
be applied as a single-ended signal by tying CLK– to midsupply
and applying CLK to CLK+, or as a differential signal applied
to CLK+ and CLK–.
RESET has no purpose when using the internal PLL and should
be grounded. When the AD9751 is in PLL ACTIVE mode,
PLLLOCK is the output of the internal phase detector. When
locked, the lock output in this mode will be a Logic “1.”
392⍀ 1.0F
CLKVDD
(3.1V TO 3.5V)
DIFFERENTIAL
TO
SINGLE-ENDED
AMP
CLK+
CLK–
PLLLOCK
PHASE
DETECTOR
LPF
CHARGE
PUMP
VCO
AD9751
ⴜ2
TO DAC
LATCH
CLKCOM
Figure 6. Clock Circuitry with PLL Active
DATA Y DATA Z
7b.
Figure 7. DAC Input Timing Requirements with PLL Active
Typically, the VCO can generate outputs of 100 MHz to 400 MHz.
The range control is used to keep the VCO operating within its
designed range, while allowing input clocks as low as 6.25 MHz.
With the PLL active, logic levels at DIV0 and DIV1 determine
the divide (prescaler) ratio of the range controller. Table I gives
the frequency range of the input clock for the different states of
DIV0 and DIV1.
Table I. CLK Rates for DIV0, DIV1 Levels With PLL Active
CLK Frequency
DIV1
DIV0
Range Controller
50 MHz–150 MHz
25 MHz–100 MHz
12.5 MHz–50 MHz
6.25 MHz–25 MHz
0
0
1
1
0
1
0
1
÷1
÷2
÷4
÷8
A 392 Ω resistor and 1.0 µF capacitor connected in series from
LPF to PLLVDD are required to optimize the phase noise vs.
settling/acquisition time characteristics of the PLL. To obtain
optimum noise and distortion performance, PLLVDD should
be set to a voltage level similar to DVDD and CLKVDD.
In general, the best phase noise performance for any PLL range
control setting is achieved with the VCO operating near its
maximum output frequency of 400 MHz.
PLLVDD
RANGE
CONTROL
(ⴜ1, 2, 4, 8)
TO INPUT
LATCHES
3.1V TO
3.5V
DATA X
DIV0
DIV1
As stated earlier, applications requiring input data rates below
6.25 MSPS must disable the PLL clock multiplier and provide
an external 2× reference clock. At higher data rates however,
applications already containing a low phase noise (i.e., jitter)
reference clock that is twice the input data rate should consider
disabling the PLL clock multiplier to achieve the best SNR
performance from the AD9751. Note, the SFDR performance
of the AD9751 remains unaffected with or without the PLL
clock multiplier enabled.
–10–
REV. 0
AD9751
The effects of phase noise on the AD9751’s SNR performance
become more noticeable at higher reconstructed output frequencies and signal levels. Figure 8 compares the phase noise of
a full-scale sine wave at exactly fDATA/4 at different data rates
(hence carrier frequency) with the optimum DIV1, DIV0 setting.
As described previously in Figure 7, in PLL ACTIVE mode,
Port 1 and Port 2 input latches are updated on the rising edge of
CLK. On the same rising edge, data previously present in the
input Port 2 latch is written to the DAC output latch. The DAC
output will update after a short propagation delay (tPD).
Following the rising edge of CLK, at a time equal to half of its
period, the data in the Port 1 latch will be written to the DAC
output latch, again with a corresponding change in the DAC
output. Due to the internal PLL, the time at which the data in
the Port 1 and Port 2 input latches is written to the DAC latch
is independent of the duty cycle of CLK. When using the PLL,
0
–10
–20
NOISE DENSITY – dBm/Hz
DAC TIMING WITH PLL ACTIVE
–30
–40
–50
the external clock can be operated at any duty cycle that meets
the specified input pulsewidth.
–60
PLL ON, fDATA = 150MSPS
–70
On the next rising edge of CLK, the cycle begins again with the
two input port latches being updated, and the DAC output latch
being updated with the current data in the Port 2 input latch.
–80
–90
–100
PLL DISABLED MODE
PLL OFF, fDATA = 50MSPS
–110
0
1
2
3
FREQUENCY OFFSET – MHz
5
4
Figure 8. Phase Noise of PLL Clock Multiplier at fOUT =
fDATA/4 at Different fDATA Settings with DIV0/DIV1
Optimized, Using R&S FSEA30 Spectrum Analyzer
SNR is partly a function of the jitter generated by the clock
circuitry. As a result, any noise on PLLVDD or CLKVDD may
degrade the SNR at the output of the DAC. To minimize this
potential problem, PLLVDD and CLKVDD can be connected
to DVDD using an LC filter network similar to that shown in
Figure 9.
When PLLVDD is grounded, the PLL is disabled. An external
clock must now drive the CLK inputs at the desired DAC output
update rate. The speed and timing of the data present at input
Ports 1 and 2 is now dependent on whether or not the AD9751
is interleaving the digital input data, or only responding to data
on a single port. Figure 10 is a functional block diagram of the
AD9751 clock control circuitry with the PLL disabled.
PLLLOCK
AD9751
DIFFERENTIAL
TO
SINGLE-ENDED
AMP
CLKVDD
TTL/CMOS
LOGIC
CIRCUITS
100F
ELECT.
10-22F
TANT.
CLOCK
LOGIC
(ⴜ1 OR ⴜ2)
CLKIN+
CLKIN–
FERRITE
BEADS
TO DAC
LATCH
0.1F
CER.
TO INPUT
LATCHES
TO
INTERNAL
MUX
PLLVDD
PLLVDD
RESET DIV0 DIV1
Figure 10. Clock Circuitry with PLL Disabled
CLKCOM
3.1V OR 3.3V
POWER SUPPLY
Figure 9. LC Network for Power Filtering
DIV0 and DIV1 no longer control the PLL, but are used to set
the control on the input mux for either interleaving or noninterleaving the input data. The different modes for states of
DIV0 and DIV1 are given in Table II.
Table II. Input Mode for DIV0,
DIV1 Levels with PLL Disabled
REV. 0
–11–
Input Mode
DIV1
DIV0
Interleaved (2×)
Noninterleaved
Port 1 Selected
Port 2 Selected
Invalid
0
0
0
1
1
1
0
1
AD9751
INTERLEAVED (2ⴛ) MODE WITH PLL DISABLED
NONINTERLEAVED MODE WITH PLL DISABLED
The relationship between the internal and external clocks in this
mode is shown in Figure 11. A clock at the output update data
rate (2× the input data rate) must be applied to the CLK inputs.
Internal dividers then create the internal 1× clock necessary for
the input latches. Although the input latches are updated on the
rising edge of the delayed internal 1× clock, the setup-and-hold
times given in the Digital Specifications table are with respect to
the rising edge of the external 2× clock. With the PLL disabled,
a load-dependent delayed version of the 1× clock is present at
the PLLLOCK pin. This signal can be used to synchronize the
external data.
If the data at only one port is required, the AD9751 interface
can operate as a simple double-buffered latch with no interleaving.
On the rising edge of the 1× clock, input latch 1 or 2 is updated
with the present input data (depending on the state of DIV0/
DIV1). On the next rising edge, the DAC latch is updated and a
time tPD later, the DAC output reflects this change. Figure 13
represents the AD9751 timing in this mode.
tS
tS
tH
DATA IN
PORT 1 OR
PORT 2
tH
1ⴛ CLOCK
PORT 1
DATA X
DATA IN
PORT 2
t LPW
DATA ENTERS
INPUT LATCHES
ON THIS EDGE
DATA Y
IOUTA OR IOUTB
INTERNAL
2ⴛ CLK
t PD
XX
t LPW
t PD
t PD
Figure 13. Timing Requirements, Noninterleaved Mode
with PLL Disabled
DELAYED
INTERNAL
1ⴛ CLK
tD
EXTERNAL
1ⴛ CLK
@ PLLLOCK
DATA OUT
PORT 1 OR
PORT 2
DAC TRANSFER FUNCTION
IOUTA OR IOUTB
DATA X
The AD9751 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 1023) while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of
both the input code and IOUTFS, and can be expressed as:
DATA Y
Figure 11. Timing Requirements, Interleaved (2×) Mode
With PLL Disabled
Updates to the data at input Ports 1 and 2 should be synchronized to the specific rising edge of the external 2× clock which
corresponds to the rising edge of the 1× internal clock as shown
in Figure 11. To ensure synchronization, a Logic “1” must be
momentarily applied to the RESET pin. Doing this and returning RESET to Logic “0” brings the 1× clock at PLLLOCK to a
Logic “1.” On the next rising edge of the 2× clock, the 1× clock
will go to Logic “0.” On the second rising edge of the 2× clock,
the 1× clock (PLLLOCK) will again, go to Logic “1” as well as
update the data in both of the input latches. The details of this
are given in Figure 12.
IOUTA = (DAC CODE/1024) × IOUTFS
(1)
IOUTB = (1023 – DAC CODE)/1024 × IOUTFS
(2)
where DAC CODE = 0 to 1023 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage,
VREFIO, and external resistor RSET. It can be expressed as:
IOUTFS = 32 × IREF
(3)
where IREF = VREFIO/RSET
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc-coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note,
RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply :
DATA ENTERS
INPUT LATCHES
ON THESE EDGES
RESET
PLLLOCK
EXTERNAL
2ⴛ CLOCK
t RH = 1.2ns
t RS = 0.2ns
Figure 12. Reset Function Timing with PLL Disabled
For proper synchronization, sufficient delay must be present
between the time RESET goes low and the rising edge of the 2×
clock. RESET going low must occur either at least tRS ns before
the rising edge of the 2× clock, or tRH ns afterwards. In the former
case, the immediately occurring CLK rising edge will cause
PLLLOCK to go low. In the latter case, the next CLK rising
edge will toggle PLLLOCK.
VOUTA = IOUTA × RLOAD
(5)
VOUTB = IOUTB × RLOAD
(6)
Note the full-scale value of VOUTA and VOUTB should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
VDIFF = (IOUTA – IOUTB) × RLOAD
(7)
Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be
expressed as:
–12–
VDIFF = {(2 DAC CODE – 1023)/1024} ×
(32 RLOAD/RSET) × VREFIO
(8)
REV. 0
AD9751
These last two equations highlight some of the advantages of
operating the AD9751 differentially. First, the differential operation will help cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion, and dc offsets.
Second, the differential code-dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
Note that the gain drift temperature performance for a singleended (VOUTA and VOUTB) or differential output (VDIFF) of the
AD9751 can be enhanced by selecting temperature tracking
resistors for RLOAD and RSET due to their ratiometric relationship as shown in Equation 8.
ANALOG OUTPUTS
The AD9751 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-ended or
differential operation. IOUTA and IOUTB can be converted into
complementary single-ended voltage outputs, VOUTA and VOUTB,
via a load resistor, RLOAD, as described by Equations 5 through 8
in the DAC Transfer Function section. The differential voltage,
VDIFF, existing between VOUTA and VOUTB can also be converted
to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9751 is optimum
and specified using a differential transformer-coupled output in
which the voltage swing at IOUTA and IOUTB is limited to ± 0.5 V.
If a single-ended unipolar output is desirable, IOUTA should be
selected as the output, with IOUTB grounded.
The distortion and noise performance of the AD9751 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can be
significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform
increases. This is due to the first order cancellation of various
dynamic common-mode distortion mechanisms, digital feedthrough and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the reconstructed signal power to the load (i.e., assuming no source
termination). Since the output currents of IOUTA and IOUTB are
complementary, they become additive when processed differentially. A properly selected transformer will allow the AD9751 to
provide the required power and voltage levels to different loads.
Refer to Applying the AD9751 section for examples of various
output configurations.
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., VOUTA and VOUTB) due to the nature of a PMOS device.
As a result, maintaining IOUTA and/or IOUTB at a virtual ground
via an I-V op amp configuration will result in the optimum dc
linearity. Note that the INL/DNL specifications for the AD9751
are measured with IOUTA and IOUTB maintained at virtual ground
via an op amp.
REV. 0
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of –1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9751.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS
= 2 mA. The optimum distortion performance for a singleended or differential output is achieved when the maximum
full-scale signal at IOUTA and IOUTB does not exceed 0.5 V.
Applications requiring the AD9751’s output (i.e., VOUTA and/or
VOUTB) to extend its output compliance range should size RLOAD
accordingly. Operation beyond this compliance range will adversely
affect the AD9751’s linearity performance and subsequently
degrade its distortion performance.
DIGITAL INPUTS
The AD9751’s digital input consists of two channels of 10 data
input pins each and a pair of differential clock input pins. The
10-bit parallel data inputs follow standard straight binary coding
where DB9 is the most significant bit (MSB) and DB0 is the
least significant bit (LSB). IOUTA produces a full-scale output
current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two
outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch. With the PLL active or disabled, the DAC
output is updated twice for every input latch rising edge, as
shown in Figures 7 and 11. The AD9751 is designed to support
an input data rate as high as 150 MSPS giving a DAC output
update rate of 300 MSPS. The setup-and-hold times can also be
varied within the clock cycle as long as the specified minimum
times are met. Best performance is typically achieved when the
input data transitions on the falling edge of a 50% duty cycle clock.
The digital inputs are CMOS-compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive
supply (DVDD) or
VTHRESHOLD = DVDD/2 (± 20%)
The internal digital circuitry of the AD9751 is capable of operating over a digital supply range of 3.1 V to 3.5 V. As a result,
the digital inputs can also accommodate TTL levels when DVDD
is set to accommodate the maximum high level voltage of the
TTL drivers VOH(MAX). A DVDD of 3.1 V to 3.3 V will typically ensure proper compatibility with most TTL logic families.
Figure 14 shows the equivalent digital input circuit for the data
and clock inputs.
DVDD
DIGITAL
INPUT
Figure 14. Equivalent Digital Input
–13–
AD9751
The AD9751 features a flexible differential clock input operating
from separate supplies (i.e., CLKVDD, CLKCOM) to achieve
optimum jitter performance. The two clock inputs, CLK+ and
CLK–, can be driven from a single-ended or differential clock
source. For single-ended operation, CLK+ should be driven by
a logic source while CLK– should be set to the threshold voltage
of the logic source. This can be done via a resistor divider/
capacitor network as shown in Figure 15a. For differential operation, both CLK+ and CLK– should be biased to CLKVDD/2
via a resistor divider network as shown in Figure 15b.
Because the output of the AD9751 is capable of being updated
at up to 300 MSPS, the quality of the clock and data input
signals are important in achieving the optimum performance.
The drivers of the digital data interface circuitry should be
specified to meet the minimum setup-and-hold times of the
AD9751 as well as its required min/max input logic level thresholds.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a low
value resistor network (i.e., 20 Ω to 100 Ω) between the AD9751
digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
data feedthrough. For longer run lengths and high data update
rates, strip line techniques with proper termination resistors
should be considered to maintain “clean” digital inputs.
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9751 is rising edge triggered, and so
exhibits SNR sensitivity when the data transition is close to this
edge. In general, the goal when applying the AD9751 is to make
the data transition close to the falling clock edge. This becomes
more important as the sample rate increases. Figure 16 shows
the relationship of SNR to clock placement with different sample
rates. Note that the setup and hold times implied in Figure 16
appear to violate the maximums stated in the Digital Specifications of this data sheet. The variation in Figure 16 is due to the
skew present between data bits inherent in the digital data generator used to perform these tests. Figure 16 is presented to
show the effects of violating setup and hold times, and to show
the insensitivity of the AD9751 to clock placement when data
transitions fall outside of the so-called “bad window.” The setup
and hold times stated in the Digital Specifications were measured
on a bit-by-bit basis, therefore eliminating the skew present in
the digital data generator. At higher data rates, it becomes very
important to account for the skew in the input digital data when
defining timing specifications.
80
The external clock driver circuitry should provide the AD9751
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a reconstructed
waveform. Thus, the clock input should be driven by the fastest
logic family suitable for the application.
70
SNR – dBc
60
Note that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies. Also,
at higher sampling rates, the 20% tolerance of the digital logic
threshold should be considered since it will affect the effective
clock duty cycle and, subsequently, cut into the required data
setup-and-hold times.
RSERIES
CLKVDD
0.1F
CLK–
CLKCOM
Figure 15a. Single-Ended Clock Interface
0.1F
40
30
20
10
0
–3
–2
–1
0
1
2
3
TIME OF DATA TRANSITION RELATIVE TO PLACEMENT OF
CLK RISING EDGE (ns), fOUT = 10MHz, fDAC = 300MHz
Figure 16. SNR vs. Time of Data Transition Relative to
Clock Rising Edge
AD9751
CLK+
VTHRESHOLD
50
AD9751
CLK+
0.1F
CLKVDD
0.1F
POWER DISSIPATION
The power dissipation, PD, of the AD9751 is dependent on several factors that include: (1) The power supply voltages (AVDD
and DVDD), (2) the full-scale current output IOUTFS, (3) the
update rate fCLOCK, and (4) the reconstructed digital input waveform. The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD.
IAVDD is directly proportional to IOUTFS as shown in Figure 17,
and is insensitive to fCLOCK. Conversely, IDVDD is dependent on
both the digital input waveform, fCLOCK, and digital supply
DVDD. Figure 18 shows IDVDD as a function of the ratio (fOUT/
fDAC) for various update rates. In addition, Figure 19 shows the
effect the speed of fDAC has on the PLLVDD current, given the
PLL divider ratio.
CLK–
CLKCOM
Figure 15b. Differential Clock Interface
–14–
REV. 0
AD9751
APPLYING THE AD9751
40
OUTPUT CONFIGURATIONS
35
The following sections illustrate some typical output configurations for the AD9751. Unless otherwise noted, it is assumed
that IOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the optimum high-frequency performance and is recommended for any
application allowing for ac-coupling. The differential op amp
configuration is suitable for applications requiring dc-coupling,
a bipolar output, signal gain, and/or level shifting, within the
bandwidth of the chosen op amp.
IAVDD – mA
30
25
20
15
10
5
0
2.5
0
5
7.5
12.5
10
IOUTFS – mA
15
17.5
20
Figure 17. IAVDD vs. IOUTFS
20
18
16
IDVDD – mA
14
300MSPS
12
10
DIFFERENTIAL COUPLING USING A TRANSFORMER
200MSPS
8
100MSPS
6
50MSPS
4
25MSPS
2
0
0.001
0.01
0.1
RATIO – fOUT/f DAC
1
Figure 18. IDVDD vs. fOUT/fDAC Ratio
10
DIV SETTING 11
9
DIV SETTING 10
8
DIV SETTING 01
7
PLL_VDD – mA
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a
dc-coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus converting
IOUTA or IOUTB into a negative unipolar voltage. This configuration
provides the best dc linearity since IOUTA or IOUTB is maintained
at a virtual ground. Note that IOUTA provides slightly better performance than IOUTB.
6
An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 20. A
differentially-coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer’s passband. An RF transformer such
as the Mini-Circuits T1–1T provides excellent rejection of
common-mode distortion (i.e., even-order harmonics) and
noise over a wide frequency range. When IOUTA and IOUTB are
terminated to ground with 50 Ω, this configuration provides
0 dBm power to a 50 Ω load on the secondary with a DAC fullscale current of 20 mA. A 2:1 transformer such as the Coilcraft
WB2040-PC can also be used in a configuration in which IOUTA
and IOUTB are terminated to ground with 75 Ω. This configuration improves load matching and increases power to 2 dBm into
a 50 Ω load on the secondary. Transformers with different
impedance ratios may also be used for impedance matching
purposes. Note that the transformer provides ac-coupling only.
5
AD9751
DIV SETTING 00
4
MINI-CIRCUITS
T1-1T
IOUTA
3
RLOAD
2
IOUTB
1
0
0
25
50
75
100 125 150 175 200 225 250 275 300
fDAC – MHz
Figure 20. Differential Output Using a Transformer
Figure 19. PLLVDD vs. fDAC
REV. 0
–15–
AD9751
The center tap on the primary side of the transformer must
be connected to ACOM to provide the necessary dc current
path for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing
symmetrically around ACOM and should be maintained with
the specified output compliance range of the AD9751. A
differential resistor, RDIFF, may be inserted in applications
where the output of the transformer is connected to the load,
RLOAD, via a passive reconstruction filter or cable. RDIFF is
determined by the transformer’s impedance ratio and provides
the proper source termination that results in a low VSWR.
AD9751
225⍀
IOUTA
AD8041
225⍀
IOUTB
COPT
1k⍀
AVDD
25⍀
25⍀
1k⍀
Figure 22. Single Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-singleended conversion as shown in Figure 21. The AD9751 is configured
with two equal load resistors, RLOAD, of 25 Ω. The differential
voltage developed across IOUTA and I OUTB is converted to a
single-ended signal via the differential op amp configuration.
An optional capacitor can be installed across IOUTA and IOUTB,
forming a real pole in a low-pass filter. The addition of this
capacitor also enhances the op amp’s distortion performance by
preventing the DAC’s high slewing output from overloading the
op amp’s input.
500⍀
AD9751
500⍀
Figure 23 shows the AD9751 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly-terminated 50 Ω cable since the nominal full-scale current, IOUTFS, of
20 mA flows through the equivalent RLOAD of 25 Ω. In this case,
RLOAD represents the equivalent load resistance seen by IOUTA or
IOUTB. The unused output (IOUTA or IOUTB) can be connected to
ACOM directly or via a matching RLOAD. Different values of
IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in
this mode is the integral nonlinearity (INL) as discussed in the
Analog Output section of this data sheet. For optimum INL
performance, the single-ended, buffered voltage output configuration is suggested.
225⍀
IOUTA
225⍀
IOUTB
COPT
25⍀
AD9751
AD8047
IOUTFS = 20mA
VOUTA = 0V TO 0.5V
IOUTA
50⍀
500⍀
50⍀
IOUTB
25⍀
25⍀
Figure 21. DC Differential Coupling Using an Op Amp
Figure 23. 0 V to 0.5 V Unbuffered Voltage Output
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to
provide some additional signal gain. The op amp must operate
from a dual supply since its output is approximately ± 1.0 V.
A high-speed amplifier capable of preserving the differential
performance of the AD9751, while meeting other system level
objectives (i.e., cost, power), should be selected. The op amp’s
differential gain, its gain setting resistor values, and full-scale
output swing capabilities should all be considered when optimizing this circuit.
The differential circuit shown in Figure 22 provides the necessary level-shifting required in a single supply system. In this
case, AVDD, which is the positive analog supply for both the
AD9751 and the op amp, is also used to level-shift the differential output of the AD9751 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
Figure 24 shows a buffered single-ended output configuration in
which the op amp performs an I-V conversion on the AD9751
output current. The op amp maintains IOUTA (or IOUTB) at a
virtual ground, thus minimizing the nonlinear output impedance
effect on the DAC’s INL performance as discussed in the
Analog Output section. Although this single-ended configuration typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates may be
limited by the op amp’s slewing capabilities. The op amp provides a negative unipolar output voltage and its full-scale output
voltage is simply the product of RFB and IOUTFS. The full-scale
output should be set within the op amp’s voltage output swing
capabilities by scaling IOUTFS and/or RFB. An improvement in ac
distortion performance may result with a reduced IOUTFS, since
the signal current the op amp will be required to sink will be
subsequently reduced.
–16–
REV. 0
AD9751
COPT
RFB
200⍀
AD9751
IOUTA
VOUT = IOUTFS ⴛ RFB
IOUTB
200⍀
Figure 24. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing, as well
as power supply bypassing and grounding, to ensure optimum
performance. Figures 34 to 41 illustrate the recommended
printed circuit board ground, power and signal plane layouts
which are implemented on the AD9751 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the Power Supply Rejection Ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, IOUTFS. AC noise on the dc supplies is
common in applications where the power distribution is generated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR vs. frequency of the AD9751 AVDD
supply over this frequency range is shown in Figure 25.
85
80
75
Note that the units in Figure 25 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current.
The voltage noise on AVDD will thus be added in a nonlinear
manner to the desired IOUT. Due to the relative different size of
these switches, PSRR is very code-dependent. This can produce
a mixing effect that can modulate low frequency power supply
noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs will occur when the full-scale current
is directed toward that output. As a result, the PSRR measurement in Figure 25 represents a worst-case condition in which
the digital inputs remain static and the full-scale output current
of 20 mA is directed to the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV rms of noise and, for
simplicity sake (i.e., ignore harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired
noise will appear as current noise superimposed on the DAC’s
full-scale current, IOUTFS, one must determine the PSRR in dB
using Figure 25 at 250 kHz. To calculate the PSRR for a given
RLOAD, such that the units of PSRR are converted from A/V to
V/V, adjust the curve in Figure 25 by the scaling factor 20 × Log
(RLOAD ). For instance, if RLOAD is 50 Ω, the PSRR is reduced
by 34 dB (i.e., PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 25, becomes 51 dB VOUT/VIN).
Proper grounding and decoupling should be a primary objective
in any high-speed, high-resolution system. The AD9751 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be
decoupled to DCOM as close to the chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 26. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
PSRR – dB
70
FERRITE
BEADS
65
AVDD
60
TTL/CMOS
LOGIC
CIRCUITS
55
100F
ELECT.
10-22F
TANT.
0.1F
CER.
ACOM
50
45
40
0
2
4
8
6
FREQUENCY – MHz
10
Figure 25. Power Supply Rejection Ratio
REV. 0
3.3V
POWER SUPPLY
12
Figure 26. Differential LC Filter for a Single 3.3 V Application
–17–
AD9751
APPLICATIONS
QAM/PSK Synthesis
Quadrature modulation (QAM or PSK) consists of two baseband
PAM (Pulse Amplitude Modulated) data channels. Both channels are modulated by a common frequency carrier. However,
the carriers for each channel are phase-shifted 90° from each
other. This orthogonality allows twice the spectral efficiency
(data for a given bandwidth) of digital data transmitted via AM.
Receivers can be designed which selectively choose the ‘in phase’
and ‘quadrature’ carriers, and then recombine the data. The
recombination of the QAM data can be mapped as points representing digital words in a two dimensional constellation as shown
in Figure 27. Each point, or symbol, represents the transmission
of multiple bits in one symbol period.
0100
0101
0001
A figure of merit for wideband signal synthesis is the ratio of signal
power in the transmitted band to the power in an adjacent channel. In Figure 29, the adjacent channel power ratio (ACPR) at
the output of the AD9751 is measured to be 62 dB. The limitation on making a measurement of this type is often not the DAC
but the noise inherent in creating the digital data record using
computer tools. To find how much this is limiting the perceived
DAC performance, the signal amplitude can be reduced, as is
shown in Figure 29. The noise contributed by the DAC will
remain constant as the signal amplitude is reduced. When the
signal amplitude is reduced to the level where the noise floor
drops below that of the spectrum analyzer, ACPR will fall off at
the same rate that the signal level is being reduced. Under the
conditions measured in Figure 28, this point occurs in Figure 29
at –4 dBFS. This shows that the data record is actually degrading the measured ACPR by up to 4 dB.
0000
80
0110
0111
0011
0010
1110
1111
1011
1010
1100
1101
1001
1000
ACPR – dB
70
Figure 27. 16 QAM Constellation, Gray Coded (Two 4-Level
PAM Signals with Orthogonal Carriers)
Typically, the I and Q data channels are quadrature-modulated
in the digital domain. The high data rate of the AD9751 allows
extremely wide band (>10 MHz) quadrature carriers to be synthesized. Figure 28 shows an example of a 25 MSymbol/S
QAM signal, oversampled by eight at a data rate of 200 MSPS;
modulated onto a 25 MHz carrier and reconstructed using the
AD9751. The power in the reconstructed signal is measured
to be –12.08 dBm. In the first adjacent band, the power is
–73.67 dBm, while in the second adjacent band the power is
–76.91 dBm.
MARKER 1 [T1]
–74.49dBm
9.71442886MHz
RBW
5kHz RF ATT
VBW
50kHz
SWT 12.5 s
UNIT
0dB
dBm
60
50
40
–20
–15
–10
AMPLITUDE – dBFS
–5
0
Figure 29. ACPR vs. Amplitude for QAM Carrier
A single-channel active mixer such as the Analog Devices AD8343
can then be used for the hop to the transmit frequency. Figure 30
shows an applications circuit using the AD9751 and the AD8343.
The AD8343 is capable of mixing carriers from dc to 2.5 GHz.
Figure 31 shows the result of mixing the signal in Figure 28 up
to a carrier frequency of 800 MHz. ACPR measured at the
output of the AD8343 is shown in Figure 31 to be 58 dB.
–30
1 [T1]
–74.49bBM,
+9.71442886MHz
CH PWR
–73.67dBm
ACP UP
–76.91dBm
ACP LOW
–12.08dBm
–40
–50
REF LV1 – dBm
–60
–70
1RM
1
–80
–90
–100
–110
C11
C11
–120
C0
C0
Cu1
Cu1
–130
START 100kHz
12.49MHz/
STOP 125MHz
COMMENT A: 25 MSYMBOL, 64 QAM, CARRIER = 25MHz
Figure 28. Reconstructing Raised Cosine Signal at
120 MHz IF
–18–
REV. 0
AD9751
DVDD
AVDD
CLK+ CLK– PLLLOCK
PLL/DIVIDER
PORT 1
DATA
INPUT
50⍀
DAC
LATCHES
INPUT
LATCHES
PORT 2
DATA
INPUT
0.1F
IOUTA
INPP
OUTP
DAC
INPUT
LATCHES
0.1F
OUTM
IOUTB
INPM
50⍀
68⍀
LOIM
68⍀
AD9751
FSADJ
LOIP
REFIO ACOM1 ACOM DCOM
RSET2
1.9k⍀
AD8343 ACTIVE MIXER
0.1F
0.1F
LOINPUT
0.1F
M/A-COM ETC-1-1-13 WIDEBAND BALUM
Figure 30. QAM Transmitter Architecture Using AD9751 and AD8343 Active Mixer
MARKER 1 [T2]
–100.59dBm
859.91983968MHz
RBW
VBW
SWT
10kHz RF ATT
10kHz
2.8 s
UNIT
0dB
dBm
–20
1 [T2]
–30
CH PWR
ACP UP
ACP LOW
1 [T2]
–40
REF LV1 – dBm
–50
–60
–70
2 [T2]
1
2
–100.59bBm,
+859.91983968MHz
–64.88dBm
–62.26dBm
–7.38dBm
33.48dB
–49.91983968MHz
33.10dB
–49.91983968MHz
2MA
–80
–90
1
–100
C11
C11
–110
C0
C0
Cu1
Cu1
–120
CENTER 860MHz
11MHz/
SPAN 110MHz
COMMENT A: 25 MSYMBOL, 64 QAM CARRIER @ 825MHz
therefore theoretically be achieved with an energy/symbol-tonoise (E/NO) ratio of 27.8 dB. Due to the loss and interferers
inherent in the wireless path, this signal-to-noise ratio must be
realized at the receiver to achieve the given bit error rate.
Distortion effects on BER are much more difficult to determine
accurately. Most often in simulation, the energies of the strongest distortion components are root-sum-squared with the noise,
and the result is treated as if it were all noise. That being said,
using the example above of 64 QAM with the BER of 1e-6, if
the E/NO ratio is much greater than the worst-case SFDR, the
noise will dominate the BER calculation.
The AD9751 has a worst-case in-band SFDR of 47 dB at the
upper end of its frequency spectrum (see TPCs 2, 3). When
used to synthesize high-level QAM signals as described above,
noise, as opposed to distortion, will dominate its performance
in these applications.
Figure 31. Signal of Figure 27 Mixed to Carrier
Frequency of 800 MHz
00
SYMBOL ERROR PROBABILITY
Effects of Noise and Distortion on Bit Error Rate (BER)
Textbook analysis of Bit Error Rate (BER) performance is
generally stated in terms of E (energy in watts-per-symbol or
watts-per-bit) and NO (spectral noise density in watts/Hz). For
QAM signals, this performance is shown graphically in Figure
32. M represents the number of levels in each quadrature PAM
signal (i.e., M = 8 for 64 QAM, M = 16 for 256 QAM). Figure
32 implies grey coding in the QAM constellation, as well as the
use of matched filters at the receiver, which is typical. The
horizontal axis of Figure 32 can be converted to units of energy/
symbol by adding to the horizontal axis 10 log of the number of
bits in the desired curve. For instance, to achieve a BER of 1e-6
with 64 QAM, an energy per bit of 20 dB is necessary. To
calculate energy per symbol, add 10 log(6), or 7.8 dB. 64 QAM
with a BER of 1e-6 (assuming no source or channel coding) can
REV. 0
–01
–02
4 QAM
16 QAM
64 QAM
–03
–04
–05
–06
0
5
10
SNR/BIT – dB
15
20
Figure 32. Probability of a Symbol Error for QAM
–19–
AD9751
Pseudo Zero Stuffing/IF Mode
EVALUATION BOARD
The excellent dynamic range of the AD9751 allows its use in
applications where synthesis of multiple carriers is desired. In
addition, the AD9751 can be used in a pseudo zero-stuffing
mode which improves dynamic range at IF frequencies. In this
mode, data from the two input channels is interleaved to the
DAC, which is running at twice the speed of either of the input
ports. However, the data at Port 2 is held constant at midscale.
The effect of this is shown in Figure 31. The IF signal is the
image, with respect to the input data rate, of the fundamental.
Normally, the sinx/x response of the DAC will attenuate this
image. Zero stuffing improves the passband flatness so that the
image amplitude is closer to that of the fundamental signal.
Zero stuffing can be an especially useful technique in the
synthesis of IF signals.
The AD9751-EB is an evaluation board for the AD9751 TxDAC.
Careful attention to layout and circuit design, combined with
prototyping area, allows the user to easily and effectively evaluate the AD9751 in different modes of operation.
EFFECT OF SINX/X ROLL-OFF
0
–10
AMPLITUDE
OF IMAGE
USING
ZERO STUFFING
–20
AMPLITUDE
OF IMAGE
WITHOUT
ZERO STUFFING
–30
–40
–50
0
0.5
1
1.5
FREQUENCY – Normalized To Input Data Rate
2
Figure 33. Effects of Pseudo Zero Stuffing on Spectrum
of AD9751
Referring to Figures 34 and 35, the AD9751’s performance
can be evaluated differentially or single-endedly using either a
transformer, or directly coupling the output. To evaluate the
output differentially using the transformer, it is recommended
that either the Mini-Circuits T1-1T (through-hole) or the Coilcraft TTWB-1-B (SMT) be placed in the position of T1 on the
evaluation board. To evaluate the output either single-ended
or direct-coupled, remove the transformer and bridge either
BL1 or BL2.
The digital data to the AD9751 comes from two ribbon cables
that interface to the 40-lead IDC connectors P1 and P2. Proper
termination or voltage scaling can be accomplished by installing
the resistor pack networks RN1–RN12. RN1, 4, 7, 10 are 22 Ω
DIP resistor packs and should be installed as they help reduce the
digital edge rates and therefore peak current on the inputs.
A single-ended clock can be applied via J3. By setting the SE/
DIFF labeled jumpers J2, 3, 4, 6, the input clock can be directed
to the CLK+/CLK– inputs of the AD9751 in either a singleended or differential manner. If a differentially applied clock is
desired, a Mini-Circuits T1-1T transformer should be used in
the position of T2. Note that with a single-ended square wave
clock input, T2 must be removed. A clock can also be applied
via the ribbon cable on Port 1 (P1), Pin 33. By inserting the
EDGE jumper (JP1), this clock will be applied to the CLK+
input of the AD9751. JP3 should be set in its SE position in this
application to bias CLK– to 1/2 the supply voltage.
The AD9751’s PLL clock multiplier can be enabled by inserting
JP7 in the IN position. As described in the Typical Performance
Characteristics and Functional Description sections, with the
PLL enabled, a clock at 1/2 the output data rate should be
applied as described in the last paragraph. The PLL takes care
of the internal 2× frequency multiplication and all internal timing requirements. In this application, the PLLLOCK output
indicates when lock is achieved on the PLL. With the PLL
enabled, the DIV0 and DIV1 jumpers (JP8 and JP9) provide
the PLL divider ratio as described in Table I.
The PLL is disabled when JP7 is in the EX setting. In this mode,
a clock at the speed of the output data rate must be applied to
the clock inputs. Internally, the clock is divided by 2. For data
synchronization, a 1× clock is provided on the PLLLOCK pin
in this application. Care should be taken to read the timing
requirements described earlier in the data sheet for optimum performance. With the PLL disabled, the DIV0 and DIV1 jumpers
define the mode (interleaved, noninterleaved) as described in
Table II.
–20–
REV. 0
AD9751
RN2
VALUE
RN1
VALUE
2 P1
P1 1
4 P1
P1 3
6 P1
P1 5
8 P1
P1 7
10 P1
P1 9
12 P1
P1 11
14 P1
P1 13
16 P1
P1 15
1
1B13 1
16
P1B13
2
1B12 2
15
P1B12
3
1B11 3
14
P1B11
4
1B10 4
13
P1B10
5
1B09 5
12
P1B09
6
1B08 6
1B07 7
1B06 8
11
10
9
RN3
VALUE
P1B08
P1B07
P1B06
1
2
1B13
3
1B12
4
1B11
5
1B10
7
DVDD PLANE
7
1B08
8
18 P1
P1 17
20 P1
P1 19
22 P1
P1 21
24 P1
P1 23
26 P1
P1 25
28 P1
P1 27
30 P1
P1 29
32 P1
P1 31
34 P1
P1 33
36 P1
P1 35
38 P1
P1 37
40 P1
P1 39
P2 1
4 P2
P2 3
6 P2
P2 5
8 P2
P2 7
10 P2
P2 9
12 P2
P2 11
14 P2
P2 13
16 P2
P2 15
1
1
16
P1B05
2
15
P1B04
3
1B03 3
14
P1B03
4
1B02 4
13
P1B02
5
1B01 5
12
P1B01
6
1B00 6
11
P1B00
7
1O17 7
10
OUT15
8
9
OUT16
8
1O16
2 P2
RN6
VALUE
1B04 2
1O15
10
RN5
VALUE
1B05 1
9
20 P2
P2 19
22 P2
P2 21
24 P2
P2 23
26 P2
P2 25
28 P2
P2 27
30 P2
P2 29
32 P2
P2 31
34 P2
P2 33
36 P2
P2 35
38 P2
P2 37
40 P2
P2 39
4
1B03
5
1B02
6
1B01
7
1B00
8
JP10
1O16 9
10
10
1O17
RN7
VALUE
2B13 1
2B12 2
RN8
VALUE
RN9
VALUE
1
1
16
P2B13
2
15
P2B12
3
2B11 3
14
P2B11
4
2B10 4
13
P2B10
5
2B09 5
12
P2B09
6
2B08 6
11
P2B08
7
2B07 7
10
P2B07
8
2B06 8
9
P2B06
RN10
VALUE
18 P2
3
1B04
9
2B13
2B12
2B11
2B10
2B09
2B08
2B07
2B06
10
P2 17
2
1B05
1O15
2
3
4
5
6
7
1
1
P2B05
2
2B04 2
15
P2B04
3
2B03 3
14
P2B03
4
2B02 4
13
P2B02
5
2B01 5
12
P2B01
6
2B00 6
11
P2B00
7
7
10 P2OUT15 8
8
9 P2OUT16 9
10
2B05
2B04
2B03
2B02
2B01
2B00
2OUT15
2OUT16
P1B13 MSB
P1B12
P1B11
P1B10
P1B09
P1B08
P1B07
P1B06
P1B05
P1B04
P1B03
P1B02
P1B01
P1B00 LSB
DVDD PLANE
5 4 3
48
14
47
15
46
45
44
U1
AD9751/53/55
18
19
C11
1.0F
R5
392⍀
CLKVDD
LPF
2
3
IA
41
21
40
22
39
AVDD PLANE
R3
50⍀
23
38
MSB
P2B13
24
37
P2B12
25 26 27 28 29 30 31 32 33 34 35 36
P2B11
P2B10
P2B09
P2B08
P2B07
P2B06
P2B05
P2B04
P2B03
P2B02
P2B01
P2B00 LSB
R10
OPT
C10
10pF
3
6
1
TP1
WHT
REFIO
JP8
1
WHT
JP9
1
TP7
BLK
BLK
TP8
BLK
A B
2
TP9
BLK
TP10
BLK
9
10
P
–21–
BL2
C12
0.1F
AVDD_PLANE
3
6
TP6
P
3
5
BLK
R1
1.91k⍀
S
A B
DIV1 2
DIV0
TP5
T1
4
TP2
BLK
IOUT
J5
2
NOTES:
1. ALL DIGITAL INPUTS FROM RN1 – RN12
MUST BE OF EQUAL LENGTH.
2. ALL DECOUPLING CAPS TO BE LOCATED
AS CLOSE AS POSSIBLE TO DUT,
PREFERABLY UNDER DUT ON BOTTOM
SIGNAL LAYER.
3. CONNECT GNDS UNDER DUT USING
BOTTOM SIGNAL LAYER.
4. CREATE PLANE CAPACITOR WITH 0.007"
DIELECTRIC BETWEEN LAYERS 2 AND 3.
TP4
C9
10pF
1
FSADJ
8
R2
50⍀
BL1
4
7
NOTE:
SHIELD AROUND
R5 AND C11 ARE
CONNECTED TO
PLLVDD PLANE
43
IB
42
20
Figure 34. Evaluation Board Circuitry
REV. 0
PLLVDD PLANE
2 1
13
16
17
WHT
P
RESET
7 6
RESET
TP3
R4
50⍀
CLK+
12 11 10 9 8
JP5
3
CLK–
9
10
RN12
VALUE
16
EXT
8
RN11
VALUE
2B05 1
2 A
B
DGND: 3,4,5 2
9
10
RN4
VALUE
J1
8
1B06
1
EDGE
1
1B07
9
OUT16
6
1B09
TP12
BLK
2
AD9751
OUT15
EDGE
JP1
SE
2 A
B
CLK+
R8
50⍀
JP2
3
T2
R9
1k⍀
2
3 B A 1
JP6
DF
CKLVDD
1
P
3
2 A
B
CLK–
DF
1
DF
2
SE
CLK
JP4
4
JP3
R7
1k⍀
C16
0.1F
6
1
S
P
J3
2 PGND: 3, 4, 5
P
1
P
3
P
DVDD
J8
1
L1
FBEAD
1
TP13
1
1
L2
FBEAD
1
1
PINS 41, 44
AVDD PLANE
TP16
C5
0.1F
BLK
RED
C15
10F
10V
1
C4
1F
C6
1F
TP17
2
CLKGND
J13
C3
0.1F
AVDD PLANE
L3
FBEAD
1
C2
1F
RED
C14
10F
10V
1
CLKVDD
J12
PINS 21, 22
PINS 5, 6
DVDD PLANE
BLK
TP15
2
AGND
J11
TP14
C1
0.1F
AVDD
J10
U1 BYPASS CAPS
DVDD PLANE
C13
10F
10V
DGND
J8
RED
2
TP11
BLK
JP7
1
A 2
B
CLKVDD
PLLVDD PLANE
PINS 45, 47
C7
0.1F
CLKVDD
C8
1F
3
P
P
Figure 35. Evaluation Board Clock Circuitry
–22–
REV. 0
AD9751
Figure 36. Evaluation Board, Assembly—Top
Figure 37. Evaluation Board, Assembly—Bottom
REV. 0
–23–
AD9751
Figure 38. Evaluation Board, Top Layer
Figure 39. Evaluation Board, Layer 2, Ground Plane
–24–
REV. 0
AD9751
Figure 40. Evaluation Board, Layer 3, Power Plane
Figure 41. Evaluation Board, Bottom Layer
REV. 0
–25–
AD9751
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.063 (1.60)
MAX
0.354 (9.00) BSC SQ
0.030 (0.75)
0.018 (0.45)
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
0ⴗ
MIN
12
25
13
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
24
0.011 (0.27)
0.006 (0.17)
0.057 (1.45)
0.053 (1.35)
7ⴗ
0ⴗ
0.006 (0.15) SEATING
0.002 (0.05) PLANE
PRINTED IN U.S.A.
COPLANARITY
0.003 (0.08)
C02250–2.5–1/01 (rev. 0)
48-Lead LQFP Package
(ST-48)
–26–
REV. 0