Catalyst CAT24WC04 Serial eeprom Datasheet

CAT24WC01/02/04/08/16
1K/2K/4K/8K/16K-Bit Serial EEPROM
FEATURES
■ Self-Timed Write Cycle with Auto-Clear
■ 400 kHz I2C Bus Compatible*
■ 1,000,000 Program/Erase Cycles
■ 1.8 to 5.5Volt Operation
■ 100 Year Data Retention
■ Low Power CMOS Technology
■ 8-pin DIP, SOIC, TSSOP and MSOP packages
■ Write Protect Feature
■ Commercial, Industrial, Automotive and
■ Page Write Buffer
Extended Temperature Ranges
DESCRIPTION
08/16 feature a 16-byte page write buffer. The device
operates via the I2C bus serial interface, has a special
write protection feature, and is available in 8-pin DIP,
SOIC, TSSOP and MSOP packages.
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16Kbit Serial CMOS EEPROM internally organized as 128/
256/512/1024/2048 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces device power requirements. The the CAT24WC01/02/04/
PIN CONFIGURATION
VSS
1
2
3
4
8
7
6
5
d
e
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BLOCK DIAGRAM
SOIC Package (J, W, GW)
DIP Package (P, L, GL)
A0
A1
A2
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P
- "Green" package option available
— Entire Array Protected When WP at VIH
VCC
WP
SCL
SDA
A0
A1
A2
VSS
1
2
3
4
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it n
8
7
6
5
VCC
WP
SCL
SDA
5020 FHD F01
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
TSSOP Package (U, Y, GY)
(MSOP and TSSOP available for CAT24WC01,
CAT24WC02 and CAT24WC04 only)
MSOP Package (R, Z, GZ)
A0
A1
A2
VSS
1
2
8
7
VCC
WP
3
4
6
5
SCL
SDA
s
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A0
A1
A2
VSS
1
2
3
4
8
7
6
5
SDA
VCC
WP
SCL
SDA WP
START/STOP
LOGIC
XDEC
E2PROM
CONTROL
LOGIC
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
+1.8V to +5.5V Power Supply
VSS
Ground
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1022, Rev. O
CAT24WC01/02/04/08/16
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
NEND(3)
Endurance
TDR(3)
Data Retention
100
VZAP(3)
ESD Susceptibility
2000
ILTH(3)(4)
Latch-up
100
Max.
1,000,000
Cycles/Byte
Years
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
s
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a
P
Units
it n
d
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Volts
mA
Limits
Symbol
ICC
ISB
(5)
Parameter
Power Supply Current
n
o
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Standby Current (VCC = 5.0V)
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL
Input Low Voltage
s
i
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VIH
Input High Voltage
Min.
Typ.
Max.
Units
Test Conditions
3
mA
fSCL = 100 KHz
1
µA
VIN = GND or VCC
10
µA
VIN = GND to VCC
10
µA
VOUT = GND to VCC
–1
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage (VCC = 3.0V)
0.4
V
IOL = 3 mA
VOL2
Output Low Voltage (VCC = 1.8V)
0.5
V
IOL = 1.5 mA
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
Max.
Units
Conditions
CI/O(3)
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN(3)
Input Capacitance (A0, A1, A2, SCL, WP)
6
pF
VIN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1022, Rev. O
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC01/02/04/08/16
A.C. CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
Read & Write Cycle Limits
CAT24WCXX-1.8
1.8V-5.5V
Min.
Symbol
Parameter
FSCL
Clock Frequency
tBUF
Noise Suppression Time Constant at
SCL, SDA Inputs
SCL Low to SDA Data Out and ACK
Out
Time the Bus Must be Free Before
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
tLOW
(1)
TI
tAA
(1)
CAT24WCXX
2.5V-5.5V
Max.
Min.
200
200
ns
3.5
3.5
1
µs
4.7
4.7
tHIGH
Clock High Period
4
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT
Data In Hold Time
0
tSU:DAT
Data In Setup Time
50
SDA and SCL Fall Time
tF
tSU:STO
Stop Condition Setup Time
tDH
Data Out Hold Time
Symbol
tPUR
s
i
D
tPUW
Write Cycle Limits
Symbol
tWR
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4
4.7
0
1.2
µs
0.6
µs
1.2
µs
0.6
µs
0.6
µs
0
ns
50
it n
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Power-Up Timing(1)(2)
s
t
r
a
P
200
Clock Low Period
SDA and SCL Rise Time
4
100
50
ns
1
1
0.3
30 0
300
300
0.6
100
100
ns
Units
Power-up to Read Operation
1
ms
Power-up to Write Operation
1
ms
Write Cycle Time
Typ.
ns
4
Max.
Min.
µs
µs
Parameter
Parameter
Units
kHz
4
(1)
Max.
400
4
tR
Min.
100
4.7
(1)
Max.
10 0
4.7
4.7
4.5V-5.5V
Max
Units
10
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1022, Rev. O
CAT24WC01/02/04/08/16
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The CAT24WC01/02/04/08/16 supports the I2C Bus
data transmission protocol. This Inter-Integrated Circuit
Bus protocol defines any device that sends data to the
bus to be a transmitter and any device receiving data to
be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24WC01/
02/04/08/16 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter
or receiver, but the Master device controls which mode
is activated. A maximum of 8 devices (CAT24WC01 and
CAT24WC02), 4 devices (CAT24WC04), 2 devices
(CAT24WC08) and 1 device (CAT24WC16) may be
connected to the bus as determined by the device
address inputs A0, A1, and A2.
SCL: Serial Clock
The CAT24WC01/02/04/08/16 serial clock input pin is
used to clock all data transfers into or out of the device.
This is an input pin.
SDA: Serial Data/Address
The CAT24WC01/02/04/08/16 bidirectional serial data/
address pin is used to transfer data into and out of the
device. The SDA pin is an open drain output and can be
wire-ORed with other open drain or open collector
outputs.
s
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A0, A1, A2: Device Address Inputs
These inputs set device address when cascading multiple devices. When these pins are left floating the
default values are zeros.
A maximum of eight devices can be cascaded when
Figure 1. Bus Timing tF
tHIGH
tLOW
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
it n
SDA IN
tAA
SDA OUT
is
SCL
D
SDA
8TH BIT
BYTE n
tSU:DAT
tDH
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c
Figure 2. Write Cycle Timing
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tR
tSU:STO
tBUF
5020 FHD F03
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
5020 FHD F05
START BIT
Doc. No. 1022, Rev. O
STOP BIT
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC01/02/04/08/16
using either CAT24WC01 or CAT24WC02 device. All
three address pins are used for these densities. If only
one CAT24WC01 or CAT24WC02 is addressed on the
bus, all three address pins (A0, A1and A2) can be left
floating or connected to VSS.
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC01/02/04/08/16
monitor the SDA and SCL lines and will not respond until
this condition is met.
A total of four devices can be addressed on a single bus
when using CAT24WC04 device. Only A1 and A2
address pins are used with this device. The A0 address
pin is a no connect pin and can be tied to VSS or left
floating. If only one CAT24WC04 is being addressed on
the bus, the address pins (A1 and A2) can be left floating
or connected to VSS.
STOP Condition
Only two devices can be cascaded when using
CAT24WC08. The only address pin used with this
device is A2. The A0 and A1 address pins are no
connect pins and can be tied to VSS or left floating. If only
one CAT24WC08 is being addressed on the bus, the
address pin (A2) can be left floating or connected to VSS.
DEVICE ADDRESSING
The CAT24WC16 is a stand alone device. In this case,
all address pins (A0, A1and A2) are no connect pins and
can be tied to VSS or left floating.
WP: Write Protect
If the WP pin is tied to VCC the entire memory array
becomes Write Protected (READ only). When the WP
pin is tied to VSS or left floating normal read/write
operations are allowed to the device.
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I2C Bus Protocol
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The following defines the features of the I2C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
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A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5).
The next three significant bits (A2, A1, A0) are the device
address bits and define which device or which part of the
device the Master is accessing. Up to eight CAT24WC01/
02, four CAT24WC04, two CAT24WC08, and one
CAT24WC16 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
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After the Master sends a START condition and the slave
address byte, the CAT24WC01/02/04/08/16 monitors
the bus and responds with an acknowledge (on the SDA
line) when its address matches the transmitted slave
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1022, Rev. O
CAT24WC01/02/04/08/16
Figure 5. Slave Address Bits
CAT24WC01/02
1
0
1
0
CAT24WC04
1
0
1
0
A2
CAT24WC08
1
0
1
0
A2
CAT24WC16
1
0
1
A1
A1
a9
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0
it n
A2
a10
a9
A0
R/W
s
t
r
a
P
a8
R/W
a8
R/W
a8
R/W
* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8, a9 and a10 correspond to the address of the memory array address word.
*** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
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address. The CAT24WC01/02/04/08/16 then performs
a Read or Write operation depending on the state of the
R/W bit.
WRITE OPERATIONS
Acknowledge
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24WC01/02/04/08/16. After receiving
another acknowledge from the Slave, the Master device
transmits the data byte to be written into the addressed
memory location. The CAT24WC01/02/04/08/16 acknowledge once more and the Master generates the
STOP condition, at which time the device begins its
internal programming cycle to nonvolatile memory. While
this internal cycle is in progress, the device will not
respond to any request from the Master device.
Byte Write
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
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The CAT24WC01/02/04/08/16 responds with an acknowledge after receiving a START condition and its
slave address. If the device has been selected along
with a write operation, it responds with an acknowledge
after receiving each 8-bit byte.
When the CAT24WC01/02/04/08/16 is in a READ mode
it transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC01/02/04/08/16 will
continue to transmit data. If no acknowledge is sent by
the Master, the device terminates data transmission and
waits for a STOP condition.
Doc. No. 1022, Rev. O
Page Write
The CAT24WC01/02/04/08/16 writes up to 16 bytes of
data in a single write cycle, using the Page Write
operation. The Page Write operation is initiated in the
same manner as the Byte Write operation, however
instead of terminating after the initial word is transmitted,
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC01/02/04/08/16
the Master is allowed to send up to fifteen additional
bytes. After each byte has been transmitted the
CAT24WC01/02/04/08/16 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24WC01/
02/04/08/16 will accept both slave and byte addresses,
but the memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
If the Master transmits more than sixteen bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
The READ operation for the CAT24WC01/02/04/08/16
is initiated in the same manner as the write operation
with the one exception that the R/W bit is set to a one.
Three different READ operations are possible: Immediate
Address READ, Selective READ and Sequential READ.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host’s write operation,
the CAT24WC01/02/04/08/16 initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24WC01/02/04/
08/16 is still busy with the write operation, no ACK will be
returned. If the CAT24WC01/02/04/08/16 has completed
the write operation, an ACK will be returned and the host
can then proceed with the next read or write operation.
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S
T
A
R
T
BUS ACTIVITY:
MASTER
s
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SDA LINE
Immediate Address Read
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Figure 6. Byte Write Timing
SLAVE
ADDRESS
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READ OPERATIONS
Once all sixteen bytes are received and the STOP
condition has been sent by the Master, the internal
programming cycle begins. At this point all received data
is written to the CAT24WC01/02/04/08/16 in a single
write cycle.
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The CAT24WC01/02/04/08/16’s address counter
contains the address of the last byte accessed,
incremented by one. In other words, if the last READ or
WRITE access was to address N, the READ immediately
following would access data from address N+1. If N=E
(where E = 255 for 24WC02, 511 for 24WC04, 1023 for
24WC08, and 2047 for 24WC16), then the counter will
'wrap around' to address 0 and continue to clock out
data. If N = E (where E = 127 for the CAT24WC01) the
counter will not 'wrap around'.
BYTE
ADDRESS
S
T
O
P
DATA
*
S
P
A
C
K
A
C
K
A
C
K
5020 FHD F08
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
S
DATA n
DATA n+1
S
T
O
P
DATA n+P
P
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
P=7 for CAT24WC01 and P=15 for CAT24WC02/04/08/16
* = Don't care for CAT24WC01
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
24WCXX F09
7
Doc. No. 1022, Rev. O
CAT24WC01/02/04/08/16
Selective Read
operations. After the 24WC01/02/04/08/16 sends initial
8-bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24WC01/02/04/08/16 will continue to
output an 8-bit byte for each acknowledge sent by the
Master. The operation is terminated when the Master
fails to respond with an acknowledge, thus sending the
STOP condition.
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24WC01/02/04/08/16 acknowledge
the word address, the Master device resends the START
condition and the slave address, this time with the R/W
bit set to one. The CAT24WC01/02/04/08/16 then
responds with its acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
The data being transmitted from the CAT24WC01/02/
04/08/16 is outputted sequentially with data from address
N followed by data from address N+1. The READ
operation address counter increments all of the
CAT24WC01/02/04/08/16 address bits so that the entire
memory array can be read during one operation. If more
than the E (where E = 255 for 24WC02, 511 for 24WC04,
1023 for 24WC08, and 2047 for 24WC16) bytes are read
out, the counter will “wrap around” and continue to clock
out data bytes. If N = E (where E = 127 for the
CAT24WC01) the counter will not 'wrap around'.
Sequential Read
The Sequential READ operation can be initiated by
either the immediate Address READ or Selective READ
Figure 8. Immediate Address Read Timing
BUS ACTIVITY:
MASTER
s
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SCL
SDA
Doc. No. 1022, Rev. O
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SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
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S
T
O
P
S
8
s
t
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P
A
C
K
DATA
N
O
A
C
K
9
8TH BIT
DATA OUT
NO ACK
STOP
5020 FHD F10
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC01/02/04/08/16
Figure 9. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
S
S
T
O
P
SLAVE
ADDRESS
S
*
A
C
K
P
A
C
K
A
C
K
DATA n
N
O
s
t
r
a
P
A
C
K
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
it n
s
i
D
24WCXX F11
n
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© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
A
C
K
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N
O
A
C
K
5020 FHD F12
Doc. No. 1022, Rev. O
CAT24WC01/02/04/08/16
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L, GL)
0.245 (6.17)
0.295 (7.49)
s
t
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0.300 (7.62)
0.325 (8.26)
0.355 (9.02)
0.400 (10.16)
0.120 (3.05)
0.150 (3.81) 0.180 (4.57) MAX
0.015 (0.38)
0.110 (2.79)
0.150 (3.81)
0.100 (2.54)
BSC
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0.310 (7.87)
0.380 (9.65)
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
it n
8-LEAD 150 MIL WIDE SOIC (J, W, GW)
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0.1497 (3.80)
0.1574 (4.00)
0.1890 (4.80)
0.1968 (5.00)
0.2284 (5.80)
0.2440 (6.20)
0.0099 (0.25)
X 45
0.0196 (0.50)
0.0075 (0.19)
0.0098 (0.25)
0.0532 (1.35)
0.0688 (1.75)
0 —8
0.050 (1.27) BSC
0.013 (0.33)
0.020 (0.51)
0.0040 (0.10)
0.0098 (0.25)
0.016 (0.40)
0.050 (1.27)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
Doc. No. 1022, Rev. O
10
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC01/02/04/08/16
8 LEAD MSOP (R, Z, GZ)
0.38
0.28
0.0150
0.0110
0.1970
0.1890
0.0256 [0.65] BSC
0.1220
0.1142
0.039 [0.10] MAX.
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0.0276
0.0157
0.70
0.40
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0.1220
0.1142
3.10
2.90
S
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3.10
2.90
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0.0433 [1.10] MAX.
5.00
4.80
S
0.0374
0.0295
0.0059
0.0020
0.15
0.05
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0.95
0.75
S
0.0150
0.0110
0.38
0.28
WITH PLATING
0.0091
0.0051
0.23
0.13
0.0050 [0.127]
0˚ - 6˚
WITH
PLATING
BASE METAL
0.0118 [0.30] REF.
SECTION A - A
Notes:
(1) All dimensions are in mm Angles in degrees.
2 Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per side.
3 Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side.
4 Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm.
(5) This part is compliant with JEDEC Specification MO-187 Variations AA.
(6) Lead span/stand off height/coplanarity are considered as special characteristics. (S)
(7) Controlling dimensions in inches. [mm]
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 1022, Rev. O
CAT24WC01/02/04/08/16
8-LEAD TSSOP (U, Y, GY)
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Doc. No. 1022, Rev. O
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© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC01/02/04/08/16
ORDERING INFORMATION
Prefix
Device #
24WC02
CAT
Optional
Company ID
Suffix
J
I
-1.8
Temperature Range
Blank = Commercial (0°C to 70°C)
I = Industrial (-40°C to 85°C)
A = Automotive (-40°C to 105°C)
E = Extended (-40°C to 125°C)
Product Number
24WC01: 1K
24WC02: 2K
24WC04: 4K
24WC08: 8K
24WC16: 16K
Package
P: PDIP
J: SOIC, JEDEC
U: TSSOP**
R: MSOP**
L: PDIP (Lead-free, Halogen-free)
W: SOIC (Lead-free, Halogen-free)
Z: MSOP (Lead-free, Halogen-free)**
Y: TSSOP (Lead-free, Halogen-free)**
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating)**
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)**
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TE13
Tape & Reel
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Operating Voltage
Blank: 2.5V - 5.5V
1.8: 1.8V - 5.5V
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REV-E
Die Revision
24WC01: C, E, F
24WC02: C, E, F
24WC04: F
24WC08: F
24WC16: D, F
** Available for CAT24WC01, CAT24WC02 and CAT24WC04
Notes:
(1) The device used in the above example is a CAT24WC02JI-1.8TE13REV-E (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt
Operating Voltage, Tape & Reel, Die Revision E)
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© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. 1022, Rev. O
REVISION HISTORY
Date
Rev.
Reason
2/3/2004
H
Added: CAT24WC01/02/16 not recommended for
new designs. See CAT24FC01, CAT24FC02 and
CAT24FC16 data sheets
5/28/2004
I
Added Die Revision to ordering information
7/28/2004
J
Update DC operating characteristics and notes
1/27/2005
K
Added Die Revision E to ordering information
2/28/2005
L
Edit Ordering Information
3/18/2005
M
Edit Features
8/12/2005
N
Edit Features
Edit Pin Functions
Edit Reliability Characteristics
Edit D.C. Operating Characteristics
Edit A.C. Characteristics
Add Package Dimensions
Edit Ordering Information
8/22/2008
O
Archived data sheet.
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Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
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Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
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Beyond Memory ™, DPP ™, EZDim ™, LDD ™, MiniPot™ and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #:
Revison:
Issue date:
1022
O
08/22/08