Fairchild FAN3100 Single 2a high-speed, low-side gate driver Datasheet

FAN3100
Single 2A High-Speed, Low-Side Gate Driver
Features
Description




3A Peak Sink/Source at VDD = 12V


Internal Resistors Turn Driver Off If No Inputs
The FAN3100 2A gate driver is designed to drive an Nchannel enhancement-mode MOSFET in low-side
switching applications by providing high peak current
pulses during the short switching intervals. The driver is
available with either TTL (FAN3100T) or CMOS
(FAN3100C) input thresholds. Internal circuitry provides
an under-voltage lockout function by holding the output
low until the supply voltage is within the operating range.
The FAN3100 delivers fast MOSFET switching
performance, which helps maximize efficiency in highfrequency power converter designs.



Choice of TTL or CMOS Input Thresholds


6-Lead 2x2mm MLP or 5-Pin SOT23 Packages
4.5 to 18V Operating Range
2.5A Sink / 1.8A Source at VOUT = 6V
Dual-Logic Inputs Allow Configuration as
Non-Inverting or Inverting with Enable Function
13ns Typical Rise Time and 9ns Typical Fall-Time
with 1nF Load
MillerDrive™ Technology
Typical Propagation Delay Time Under 20ns with
Input Falling or Rising
Rated from –40°C to 125°C Ambient
Applications





Switch-Mode Power Supplies
High-Efficiency MOSFET Switching
Synchronous Rectifier Circuits
DC-to-DC Converters
FAN3100 drivers incorporate MillerDrive™ architecture
for the final output stage. This bipolar-MOSFET
combination provides high peak current during the Miller
plateau stage of the MOSFET turn-on / turn-off process
to minimize switching loss, while providing rail-to-rail
voltage swing and reverse current capability.
The FAN3100 also offers dual inputs that can be
configured to operate in non-inverting or inverting mode
and allow implementation of an enable function. If one or
both inputs are left unconnected, internal resistors bias
the inputs such that the output is pulled low to hold the
power MOSFET off.
The FAN3100 is available in a lead-free finish 2x2mm 6lead Molded Leadless Package (MLP), for smallest size
with excellent thermal performance, or industry-standard
5-pin SOT23.
Motor Control
Functional Pin Configurations
Figure 1. 2x2mm 6-Lead MLP (Top View)
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
Figure 2. SOT23-5 (Top View)
www.fairchildsemi.com
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
January 2011
Part Number
Input
Threshold
Package
Packing Method
Quantity / Reel
FAN3100CMPX
CMOS
6-Lead 2x2mm MLP
Tape & Reel
3000
FAN3100CSX
CMOS
5-Pin SOT23
Tape & Reel
3000
FAN3100TMPX
TTL
6-Lead 2x2mm MLP
Tape & Reel
3000
FAN3100TSX
TTL
5-Pin SOT23
Tape & Reel
3000
Package Outlines
Figure 3. 2x2mm 6-Lead MLP (Top View)
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Ordering Information
Figure 4. SOT23-5 (Top View)
Thermal Characteristics(1)
JL(2)
JT(3)
JA(4)
JB(5)
JT(6)
Units
6-Lead 2x2mm Molded Leadless Package (MLP)
2.7
133
58
2.8
42
°C/W
SOT23-5
56
99
157
51
5
°C/W
Package
Notes:
1.
2.
3.
4.
5.
6.
Estimates derived from thermal simulation; actual values depend on the application.
Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink using a 2SP2 board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
Psi_JB (JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 4. For the MLP-6 package, the board
reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the
SOT23-5 package, the board reference is defined as the PCB copper adjacent to pin 2.
Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 4.
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
www.fairchildsemi.com
2
SOT23 MLP
Pin # Pin #
1
Name
3
VDD
2
AGND
2
GND
Pin Description
Supply Voltage. Provides power to the IC.
Analog ground for input signals (MLP only). Connect to PGND underneath the IC.
Ground (SOT-23 only). Common ground reference for input and output circuits.
3
1
IN+
Non-Inverting Input. Connect to VDD to enable output.
4
6
IN-
Inverting Input. Connect to AGND or PGND to enable output.
5
4
OUT
Pad
P1
5
PGND
Gate Drive Output: Held low unless required inputs are present and VDD is above UVLO
threshold.
Thermal Pad (MLP only). Exposed metal on the bottom of the package which is
electrically connected to pin 5.
Power Ground (MLP only). For output drive circuit; separates switching noise from
inputs.
Output Logic
IN+
IN−
OUT
(7)
0
0
(7)
(7)
0
1
0
1
1
(7)
0
0
0
1
1
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Pin Definitions
Note:
7. Default input signal if no external connection is made.
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
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3
Figure 5. Simplified Block Diagram (SOT23 Pin-out)
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Block Diagrams
Figure 6. Simplified Block Diagram (MLP Pin-out)
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
-0.3
20.0
V
VDD
VDD to PGND
VIN
Voltage on IN+ and IN- to GND, AGND, or PGND
GND - 0.3 VDD + 0.3
V
VOUT
Voltage on OUT to GND, AGND, or PGND
GND - 0.3 VDD + 0.3
V
TL
Lead Soldering Temperature (10 seconds)
TJ
Junction Temperature
TSTG
Storage Temperature
ESD
Electrostatic Discharge
Protection Level
Human Body Model, JEDEC JESD22-A114
Charged Device Model, JEDEC JESD22-C101
+260
ºC
-55
+150
ºC
-65
+150
ºC
4
kV
750
V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
VDD
Supply Voltage Range
4.5
18.0
V
VIN
Input Voltage IN+, IN-
0
VDD
V
TA
Operating Ambient Temperature
-40
+125
ºC
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Absolute Maximum Ratings
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5
Unless otherwise noted, VDD = 12V, TJ = -40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
18.0
V
Supply
VDD
Operating Range
IDD
Supply Current
Inputs/EN Not Connected
VON
Turn-On Voltage
VOFF
Turn-Off Voltage
4.5
(8)
FAN3100C
0.20
0.35
mA
FAN3100T
0.5
0.8
mA
3.5
3.9
4.3
V
3.3
3.7
4.1
V
Inputs (FAN3100T)
VINL_T
IN+, IN- Logic Low Voltage, Maximum
VINH_T
IN+, IN- Logic High Voltage, Minimum
0.8
V
2.0
V
IIN+
Non-inverting Input
IN from 0 to VDD
-1
175
µA
IIN-
Inverting Input
IN from 0 to VDD
-175
1
µA
0.8
V
VHYS
IN+, IN- Logic Hysteresis Voltage
0.2
0.4
Inputs (FAN3100C)
VINL_C
IN+, IN- Logic Low Voltage
VINH_C
IN+, IN- Logic High Voltage
30
%VDD
70
%VDD
IINL
IN Current, Low
IN from 0 to VDD
-1
175
µA
IINH
IN Current, High
IN from 0 to VDD
-175
1
µA
VHYS_C
IN+, IN- Logic Hysteresis Voltage
17
%VDD
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Electrical Characteristics
Output
OUT Current, Mid-Voltage, Sinking(9)
OUT at VDD/2,
CLOAD = 0.1µF, f = 1kHz
2.5
A
ISOURCE
OUT Current, Mid-Voltage, Sourcing(9)
OUT at VDD/2,
CLOAD = 0.1µF, f = 1kHz
-1.8
A
IPK_SINK
OUT Current, Peak, Sinking(9)
CLOAD = 0.1µF, f = 1kHz
3
A
OUT Current, Peak, Sourcing
CLOAD = 0.1µF, f = 1kHz
-3
A
Output Rise Time(10)
CLOAD = 1000pF
13
20
ns
CLOAD = 1000pF
9
14
ns
ISINK
IPK_SOURCE
tRISE
tFALL
(9)
(10)
Output Fall Time
(10)
tD1, tD2
Output Prop. Delay, CMOS Inputs
tD1, tD2
(10)
IRVS
Output Prop. Delay, TTL Inputs
0 - 12VIN; 1V/ns Slew Rate
7
15
28
ns
0 - 5VIN; 1V/ns Slew Rate
9
16
30
ns
(9)
Output Reverse Current Withstand
500
mA
Note:
8. Lower supply current due to inactive TTL circuitry.
9. Not tested in production.
10. See Timing Diagrams of Figure 7 and Figure 8.
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
www.fairchildsemi.com
6
90%
Output
10%
Input
VINH
VINL
tD1
tD2
tRISE
Figure 7. Non-Inverting
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
tFALL
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Timing Diagrams
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7
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 9. IDD (Static) vs. Supply Voltage
Figure 10. IDD (Static) vs. Supply Voltage
Figure 11. IDD (No-Load) vs. Frequency
Figure 12. IDD (No-Load) vs. Frequency
Figure 13. IDD (1nF Load) vs. Frequency
Figure 14. IDD (1nF Load) vs. Frequency
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
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8
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 15. IDD (Static) vs. Temperature
Figure 16. IDD (Static) vs. Temperature
Figure 17. Input Thresholds vs. Supply Voltage
Figure 18. Input Thresholds vs. Supply Voltage
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Figure 19. Input Thresholds % vs. Supply Voltage
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
www.fairchildsemi.com
9
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 20. CMOS Input Thresholds vs. Temperature
Figure 21. TTL Input Thresholds vs. Temperature
Figure 22. UVLO Thresholds vs. Temperature
Figure 23. UVLO Hysteresis vs. Temperature
Figure 24. Propagation Delay vs. Supply Voltage
Figure 25. Propagation Delay vs. Supply Voltage
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
www.fairchildsemi.com
10
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 26. Propagation Delay vs. Supply Voltage
Figure 27. Propagation Delay vs. Supply Voltage
Figure 28. Propagation Delay vs. Temperature
Figure 29. Propagation Delay vs. Temperature
Figure 30. Propagation Delay vs. Temperature
Figure 31. Propagation Delay vs. Temperature
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
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11
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 32. Fall Time vs. Supply Voltage
Figure 33. Rise Time vs. Supply Voltage
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Figure 34. Rise and Fall Time vs. Temperature
Figure 35. Rise / Fall Waveforms with 1nF Load
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
Figure 36. Rise / Fall Waveforms with 10nF Load
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Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 37. Quasi-Static Source Current with VDD=12V
Figure 38. Quasi-Static Sink Current with VDD=12V
Figure 39. Quasi-Static Source Current with VDD=8V
Figure 40. Quasi-Static Sink Current with VDD=8V
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
VDD
470µF
Al. El.
4.7µF
ceramic
Current Probe
LECROY AP015
IN
1kHz
IOUT
1µF
ceramic
VOUT
CLOAD
0.1µF
Figure 41. Quasi-Static IOUT / VOUT Test Circuit
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
www.fairchildsemi.com
13
often occurs in synchronous rectifier applications
because the body diode is generally conducting before
the MOSFET is switched on.
Input Thresholds
The FAN3100 offers TTL or CMOS input thresholds. In
the FAN3100T, the input thresholds meet industrystandard TTL logic thresholds, independent of the VDD
voltage, and there is a hysteresis voltage of
approximately 0.4V. These levels permit the inputs to be
driven from a range of input logic signal levels for which
a voltage over 2V is considered logic high. The driving
signal for the TTL inputs should have fast rising and
falling edges with a slew rate of 6V/µs or faster, so the
rise time from 0 to 3.3V should be 550ns or less. With
reduced slew rate, circuit noise could cause the driver
input voltage to exceed the hysteresis voltage and
retrigger the driver input, causing erratic operation.
The output pin slew rate is determined by VDD voltage
and the load on the output. It is not user adjustable, but
if a slower rise or fall time at the MOSFET gate is
needed, a series resistor can be added.
In the FAN3100C, the logic input thresholds are
dependent on the VDD level and, with VDD of 12V, the
logic rising edge threshold is approximately 55% of VDD
and the input falling edge threshold is approximately
38% of VDD. The CMOS input configuration offers a
hysteresis voltage of approximately 17% of VDD. The
CMOS inputs can be used with relatively slow edges
(approaching DC) if good decoupling and bypass
techniques are incorporated in the system design to
prevent noise from violating the input voltage hysteresis
window. This allows setting precise timing intervals by
fitting an R-C circuit between the controlling signal and
the IN pin of the driver. The slow rising edge at the IN
pin of the driver introduces a delay between the
controlling signal and the OUT pin of the driver.
Figure 42. MillerDrive™ Output Architecture
Under-Voltage Lockout
The FAN3100 start-up logic is optimized to drive ground
referenced N-channel MOSFETs with a under-voltage
lockout (UVLO) function to ensure that the IC starts up
in an orderly fashion. When VDD is rising, yet below the
3.9V operational level, this circuit holds the output low,
regardless of the status of the input pins. After the part
is active, the supply voltage must drop 0.2V before the
part shuts down. This hysteresis helps prevent chatter
when low VDD supply voltages have noise from the
power switching. This configuration is not suitable for
driving high-side P-channel MOSFETs because the low
output voltage of the driver would turn the P-channel
MOSFET on with VDD below 3.9V.
Static Supply Current
In the IDD (static) typical performance graphs (Figure 9 Figure 10 and Figure 15 - Figure 16), the curve is
produced with all inputs floating (OUT is low) and
indicates the lowest static IDD current for the tested
configuration. For other states, additional current flows
through the 100k resistors on the inputs and outputs
shown in the block diagrams (see Figure 5 - Figure 6).
In these cases, the actual static IDD current is the value
obtained from the curves plus this additional current.
VDD Bypass Capacitor Guidelines
To enable this IC to turn a power device on quickly, a
local, high-frequency, bypass capacitor CBYP with low
ESR and ESL should be connected between the VDD
and GND pins with minimal trace length. This capacitor
is in addition to bulk electrolytic capacitance of 10µF to
47µF often found on driver and controller bias circuits.
MillerDrive™ Gate Drive Technology
FAN3100 drivers incorporate the MillerDrive™
architecture shown in Figure 42 for the output stage, a
combination of bipolar and MOS devices capable of
providing large currents over a wide range of supply
voltage and temperature variations. The bipolar devices
carry the bulk of the current as OUT swings between 1/3
to 2/3 VDD and the MOS devices pull the output to the
high or low rail.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply ≤5%. Often
this is achieved with a value ≥ 20 times the equivalent
load capacitance CEQV, defined here as Qgate/VDD.
Ceramic capacitors of 0.1µF to 1µF or larger are
common choices, as are dielectrics, such as X5R and
X7R, which have good temperature characteristics and
high pulse current capability.
The purpose of the MillerDrive™ architecture is to speed
up switching by providing the highest current during the
Miller plateau region when the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the
turn-on
/
turn-off
process.
For applications that have zero voltage switching during
the MOSFET turn-on or turn-off interval, the driver
supplies high peak current for fast switching even
though the Miller plateau is not present. This situation
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Applications Information
If circuit noise affects normal operation, the value of
CBYP may be increased to 50-100 times the CEQV, or
CBYP may be split into two capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10nF, mounted
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14
Layout and Connection Guidelines
The FAN3100 incorporates fast reacting input circuits,
short propagation delays, and powerful output stages
capable of delivering current peaks over 2A to facilitate
voltage transition times from under 10ns to over 100ns.
The following layout and connection guidelines are
strongly recommended:

Keep high-current output and power ground paths
separate from logic input signals and signal ground
paths. This is especially critical when dealing with
TTL-level logic thresholds.

Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve highspeed switching, while reducing the loop area that
can radiate EMI to the driver inputs and other
surrounding circuitry.

The FAN3100 is available in two packages with
slightly different pinouts, offering similar
performance. In the 6-pin MLP package, Pin 2 is
internally connected to the input analog ground and
should be connected to power ground, Pin 5,
through a short direct path underneath the IC. In the
5-pin SOT23, the internal analog and power ground
connections are made through separate, individual
bond wires to Pin 2, which should be used as the
common ground point for power and control signals.

Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output retriggering. These effects can be especially obvious
if the circuit is tested in breadboard or non-optimal
circuit layouts with long input, enable, or output
leads. For best results, make connections to all pins
as short and direct as possible.

The turn-on and turn-off current paths should be
minimized as discussed in the following sections.
Figure 43. Current Path for MOSFET Turn-On
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
closest to the VDD and GND pins to carry the higherfrequency components of the current pulses.
Figure 43 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn the
MOSFET on. The current is supplied from the local
bypass capacitor, CBYP, and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance in
the path should be minimized. The localized CBYP acts to
contain the high peak current pulses within this driverMOSFET circuit, preventing them from disturbing the
sensitive analog circuitry in the PWM controller.
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
www.fairchildsemi.com
15
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Figure 44 shows the current path when the gate driver
turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
Figure 44. Current Path for MOSFET Turn-Off
Truth Table of Logic Operation
The FAN3100 truth table indicates the operational states
using the dual-input configuration. In a non-inverting
driver configuration, the IN- pin should be a logic low
signal. If the IN- pin is connected to logic high, a disable
function is realized, and the driver output remains low
regardless of the state of the IN+ pin.
IN+
IN-
OUT
0
0
1
1
0
1
0
1
0
0
1
0
In the non-inverting driver configuration in Figure 45, the
IN- pin is tied to ground and the input signal (PWM) is
applied to IN+ pin. The IN- pin can be connected to logic
high to disable the driver and the output remains low,
regardless of the state of the IN+ pin.
Figure 45. Dual-Input Driver Enabled,
Non-Inverting Configuration
In the inverting driver application shown in Figure 46, the
IN+ pin is tied high. Pulling the IN+ pin to GND forces the
output low, regardless of the state of the IN- pin.
Figure 46. Dual-Input Driver Enabled,
Inverting Configuration
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
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16
At power up, the driver output remains low until the VDD
voltage reaches the turn-on threshold. The magnitude of
the OUT pulses rises with VDD until steady-state VDD is
reached. The non-inverting operation illustrated in
Figure 47 shows that the output remains low until the
UVLO threshold is reached, then the output is in-phase
with the input.
PGATE = QG • VGS • FSW
(2)
Dynamic Pre-drive / Shoot-through Current: A power
loss resulting from internal current consumption
under dynamic operating conditions, including pin
pull-up / pull-down resistors, can be obtained using
the IDD (no-Load) vs. Frequency graphs in Typical
Performance Characteristics to determine the
current IDYNAMIC drawn from VDD under actual
operating conditions:
PDYNAMIC = IDYNAMIC • VDD
(3)
Once the power dissipated in the driver is determined,
the driver junction rise with respect to circuit board can
be evaluated using the following thermal equation,
assuming JB was determined for a similar thermal
design (heat sinking and air flow):
TJ
= PTOTAL • JB + TB
(4)
where:
TJ
= driver junction temperature
JB = (psi) thermal characterization parameter
relating temperature rise to total power
dissipation
TB = board temperature in location defined in the
Thermal Characteristics table.
Figure 47. Non-Inverting Start-Up Waveforms
For the inverting configuration of Figure 46, start-up
waveforms are shown in Figure 48. With IN+ tied to
VDD and the input signal applied to IN–, the OUT pulses
are inverted with respect to the input. At power up, the
inverted output remains low until the VDD voltage
reaches the turn-on threshold, then it follows the input
with inverted phase.
In a typical forward converter application with 48V input,
as shown in Figure 49, the FDS2672 would be a
potential MOSFET selection. The typical gate charge
would be 32nC with VGS = VDD = 10V. Using a TTL input
driver at a switching frequency of 500kHz, the total
power dissipation can be calculated as:
PGATE = 32nC • 10V • 500kHz = 0.160W
PDYNAMIC = 8mA • 10V = 0.080W
PTOTAL = 0.24W
(5)
(6)
(7)
The 5-pin SOT23 has a junction-to-lead thermal
characterization parameter JB = 51°C/W.
In a system application, the localized temperature
around the device is a function of the layout and
construction of the PCB along with airflow across the
surfaces. To ensure reliable operation, the maximum
junction temperature of the device must be prevented
from exceeding the maximum rating of 150°C; with 80%
derating, TJ would be limited to 120°C. Rearranging
Equation 4 determines the board temperature required
to maintain the junction temperature below 120°C:
Figure 48. Inverting Start-Up Waveforms
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
power. It is important to determine the driver power
dissipation and the resulting junction temperature in the
application to ensure that the part is operating within
acceptable temperature limits.
TB,MAX = TJ - PTOTAL • JB
(8)
TB,MAX = 120°C – 0.24W • 51°C/W = 108°C
(9)
For comparison purposes, replace the 5-pin SOT23
used in the previous example with the 6-pin MLP
package with JB = 2.8°C/W. The 6-pin MLP package
can operate at a PCB temperature of 119°C, while
maintaining the junction temperature below 120°C. This
illustrates that the physically smaller MLP package with
thermal pad offers a more conductive path to remove
the heat from the driver. Consider the tradeoffs between
reducing overall circuit size with junction temperature
reduction for increased reliability.
The total power dissipation in a gate driver is the sum of
two components; PGATE and PDYNAMIC:
PTOTAL = PGATE + PDYNAMIC
(1)
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit
time) to switch the load MOSFET on and off at the
switching frequency. The power dissipation that
results from driving a MOSFET at a specified gate© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
source voltage, VGS, with gate charge, QG, at
switching frequency, fSW , is determined by:
Operational Waveforms
www.fairchildsemi.com
17
Figure 49. Forward Converter, Primary-Side Gate Drive (MLP Package Shown)
Figure 50. Driver for Two-Transistor Forward Converter Gate Transformer
FAN3100 — Single 2A High-Speed, Low-Side Gate Driver
Typical Application Diagrams
Figure 51. Secondary Synchronous Rectifier Driver
Figure 52. Programmable Time Delay Using CMOS Input
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
www.fairchildsemi.com
18
Gate
(11)
Drive
(Sink/Src)
Input
Threshold
Part
Number
Type
FAN3100C
Single 2A
+2.5A / -1.8A
CMOS
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
FAN3100T
Single 2A
+2.5A / -1.8A
TTL
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
FAN3226C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3226T
Dual 2A
+2.4A / -1.6A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3227C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3227T
Dual 2A
+2.4A / -1.6A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3228C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
FAN3228T
Dual 2A
+2.4A / -1.6A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8, MLP8
FAN3229C
Dual 2A
+2.4A / -1.6A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
FAN3229T
Dual 2A
+2.4A / -1.6A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8, MLP8
FAN3223C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3223T
Dual 4A
+4.3A / -2.8A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3224C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3224T
Dual 4A
+4.3A / -2.8A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3225C
Dual 4A
+4.3A / -2.8A
CMOS
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
FAN3225T
Dual 4A
+4.3A / -2.8A
TTL
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
Logic
Package
FAN3100 — Single 2A High-Speed, Low-Side MOSFET Driver
Table 1. Related Products
Note:
11. Typical currents with OUT at 6V and VDD = 12V.
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
www.fairchildsemi.com
19
FAN3100 — Single 2A High-Speed, Low-Side MOSFET Driver
Physical Dimensions
Figure 53. 2x2mm, 6-Lead Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
www.fairchildsemi.com
20
3.00
2.80
5
SYMM
CL
0.95
0.95
A
4
B
3.00
2.60
1.70
1.50
1
2
2.60
3
(0.30)
1.00
0.50
0.30
0.95
1.90
0.20
C A B
0.70
TOP VIEW
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.30
0.90
FAN3100 — Single 2A High-Speed, Low-Side MOSFET Driver
Physical Dimensions (Continued)
1.45 MAX
0.15
0.05
0.22
0.08
C
0.10 C
NOTES: UNLESS OTHEWISE SPECIFIED
GAGE PLANE
A) THIS PACKAGE CONFORMS TO JEDEC
MO-178, ISSUE B, VARIATION AA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) MA05Brev5
0.25
8°
0°
0.55
0.35
0.60 REF
SEATING PLANE
Figure 54. 5-Lead SOT-23
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
www.fairchildsemi.com
21
FAN3100 — Single 2A High-Speed, Low-Side MOSFET Driver
© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
www.fairchildsemi.com
22