ETC1 BCRT-ACA Bcrt bus controller/remote terminal/monitor Datasheet

UT1553B RTI Remote Terminal Interface
FEATURES
❐ Operational status available via dedicated lines or
❐ Complete MIL-STD-1553B Remote Terminal
❐ ASD/ENASC (formerly SEAFAC) tested and
approved
❐ Available in ceramic 84-lead leadless chip carrier and
84-pin pingrid array
❐ Full military operating temperature range, -55°C to
+125°C, screened to the specific test methods listed in
Table I of MIL-STD-883, Method 5004, Class B
❐ JAN-qualified devices available
MODE CODE/
SUB ADDRESS
DECODER
CHANNEL
A
IN
A
OUT
IN
B
OUTPUT MULTIPLEXING AND
SELF TEST WRAP-AROUND LOGIC
❐
❐
MIL-STD-1553B SERIAL BUS TRANSCEIVER I/O
❐
❐
interface compliance
Dual-redundant data bus operation supported
Internal illegalization of selected mode code
commands
External illegal command definition capability
Automatic DMA control and address generation
internal status register
MEMORY
ADDRESS
CONTROL
OUTPUT EN
COMMAND
RECOGNITION
LOGIC
MEMORY
ADDRESS
OUTPUTS
DECODER
CHANNEL
B
CONTROL
INPUTS
CONTROL
AND
ERROR LOGIC
CONTROL
OUTPUTS
TIMEOUT
TIMERON
MUX
ENCODER
OUT
HOST
SYSTEM
ADDRESS
INPUTS
ILLEGAL
COMMAND
DATA
TRANSFER
LOGIC
CLOCK AND
RESET LOGIC
12MHz
RESET
16
2MHz
DATA I/O BUS
Figure 1. UT1553B RTI Functional Block Diagram
RTI-1
Table of Contents
1.0
ARCHITECTURE AND OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
RTI-2
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1.1 Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1.2 Transparent Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Mode Codes and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
MIL-STD-1553B Subaddress and Mode Codes . . . . . . . . . . . . . . . . . . . . . . . .9
Remote Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.0
MEMORY MAP EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.0
PIN IDENTIFICATION AND DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.0
MAXIMUM AND RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . 21
5.0
DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.0
AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.0
PACKAGE OUTLINE DRAWINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.0 ARCHITECTURE AND OPERATION
The UT1553B RTI is an interface device linking a MILSTD-1553 serial data bus and a host microprocessor system.
The RTI’s MIL-STD-1553B interface includes encoding/
decoding logic, error detection, command recognition,
memory address control, clock, and reset circuits.
Decoders
The UT1553B RTI contains two separate free-running
decoders to insure that all redundancy requirements of MILSTD-1553B are met. Each decoder receives, decodes, and
verifies biphase Manchester II data. Proper frequency and
edge skew are also verified.
Command Recognition Logic
The command recognition logic monitors the output of both
decoders at all times. Recognition of a valid command
causes a reset of present interface activity followed by
execution of the command. This procedure meets the
requirement for superseding valid commands.
Encoder
The encoder receives serial data from the data transfer logic,
converts it to Manchester II form with proper
synchronization and parity, and passes it to the output and
self-test logic.
Data Transfer Logic
The data transfer logic provides double-buffered 16-bit
parallel-to-serial and serial-to-parallel conversion during
reception and transmission of data.
Memory Address Control
The memory address control logic controls the output of the
three-state address lines during memory access. In DMA
system implementations, the memory address control
provides RTI-generated addresses. In a pseudo-dual-port
memory configuration, the memory address control logic
provides either RTI-generated or host system addressing.
Control and Error Logic
The control and error logic performs the following four
major functions:
-
Interface control for proper processing of MILSTD-1553B commands
Error checking of both MIL-STD-1553B data and
RTI operation
Memory control (DMA or pseudo-dual-port) for
proper data transfer
Operational status and control signal generation
Output Multiplexing and Self-Test Logic
This logic directs the output of the encoder to one of four
places:- Channel A outputs
- Channel B outputs
- Channel A decoders during self-test
- Channel B decoders during self-test
Clock and Reset Logic
The UT1553B RTI requires a 12MHz input clock to operate
properly. The RTI provides a 2MHz output for the system
designer to use. The device provides a hardware reset pin
as well as software-generated reset.
Timer Logic
The UT1553B RTI has a built-in 730ms timer that is
activated when the encoder is about to transmit. The timer
is reset upon receipt of a valid command, master reset, or a
time-out condition.
1.1 HOST INTERFACE
Configure the RTI into the host system for either a direct
memory or transparent memory access. The following
sections discuss the system configuration for each method
of memory management.
1.1.1 Direct Memory Access
In the direct memory access configuration the RTI and host
arbitrate for the shared 2K x 16 memory space. To request
access to memory the RTI asserts direct memory request
output (DMARQ); the system bus arbiter grants the RTI
access to memory by asserting the direct memory access
grant signal (MEMCK). The system arbiter should not assert
the MEMCK signal before the RTI has requested access to
memory (i.e., DMARQ asserted).
Once granted access to memory, the RTI address out
(ADDR OUT(10:0)), RAM chip select (RCS), RAM read/
write (RRD/RWR), and Data bus (DATA I/O(15:0)) provide
the interface signals to control the memory access. Figure
2 shows an example of a direct memory access system
configuration; for clarity the interface buffers and logic are
excluded. The host microprocessor also gains access to
memory by arbitration.
Take care to insure that bus contention does not occur
between the host and RTI Address buses or memory control
signals. To place the RTI Address Out bus in a high
impedance state negate the ADOEN input pin. Also note
that outputs RCS and RRD/RWR are not three-state outputs.
When the RTI is not writing to memory, bidirectional Data
bus DATA I/O(15:0) is an input (i.e., not actively driving
the bus).
RTI-3
Shared
Memory
Host
Computer
CONTROL
CONTROL
DATA(15:0)
RTI
UT1553B
ADDR(10:0)
DMA
CONTROLLER
Figure 2. Direct Memory Access Configuration
The host microprocessor gains access to the RTI internal
registers by controlling input pins CS, CTRL, ADDR IN
(10:0), and RD/WR. During message processing the host
microprocessor should limit access to RTI internal registers.
1.1.2 Transparent Memory Access
Configured in the transparent memory mode the host
microprocessor accesses shared memory through the RTI.
Arbitration for access to the bus is performed as discussed
in section 1.1.1 of this document.
When granted access to memory, the RTI asserts memory
control signals ADDR OUT(10:0), RCS, and RRD/RWR.
For host-controlled memory accesses the RAM memory
address from the host is propagated from the Address In bus
ADDR IN (10:0) to the Address Out bus ADDR OUT (10:0).
Memory control signals RD/WR and CS are also propagated
through the RTI as RRD/RWR and RCS. Input CTRL is
negated during all transparent memory accesses to prevent
the RTI from inadvertently performing an internal register
access or software reset. While CS is asserted, the RTI’s
bidirectional Data bus DATA I/O (15:0) is an input (i.e., not
actively driving bus).
The host microprocessor gains access to the RTI internal
registers by controlling input pins CS, CTRL, ADDR IN
(10:0), and RD/WR. During message processing the host
microprocessor should limit access to RTI internal registers.
The host should not assert CS while the RTI is performing
a memory access.
1.2 Internal Register Description
The RTI uses three internal registers to allow the host to
control the RTI operation and monitor its status. The host
uses the following inputs Control (CTRL), Chip Select
(CS), Read/Write (RD/WR), and ADDR IN (0) to read the
16-bit System Register or write to the 8-bit Control Register.
The Control Register toggles bits in the MIL-STD-1553B
status word, enables biphase inputs, selects terminal active
flag, and puts the part in self-test. The System Register
supplies operational status of the UT1553B RTI to the host.
The Last Command Register saves the command word for
a Transmit Last Command mode code, along with
operational status from the System Register.
DATA(15:0)
Host
Computer
CONTROL
DATA I/O (15:0)
ADDR IN (10:0)
RTI
UT1553B
CONTROL
Shared
Memory
ADDR OUT (10:0)
DMA
CONTROLLER
Figure 3. Transparent Memory Access Configuration
Control Register (Write Only)
RTI-4
The 8-bit write-only Control Register manages the operation of the RTI. Write to the Control Register by applying a logic zero
to CS, CTRL, RD/WR, and ADDR IN (0); if ADDR IN (0) is a logic one a master reset occurs. Data is loaded into the Control
Register via I/O pins DATA(7:0). Control Register writes must occur 50ns before the rising edge of COMSTR to latch data in
the outgoing status word.
Bit
Initial
Number
Condition
Description
0
[0]
Channel A Enable. A logic one enables Channel A biphase inputs.
1
[0]
Channel B Enable. A logic one enables Channel B biphase inputs.
2
[0]
Terminal Flag. A logic one sets the Terminal Flag bit of the Status Register.
3
[0]
System Busy. A logic one sets the Busy bit of the System Register and inhibits
RTI access to memory. No data words are retrieved or stored; command word is
stored.
4
[0]
Subsystem Busy. A logic one sets the Subsystem Flag bit of the Status Register.
5
[0]
Self-Test Channel Select. This bit selects which channel the internal self-test
checks; a logic one selects Channel A and a logic zero selects Channel B.
6
[0]
Self-Test Enable. A logic one sets the RTI in the internal self-test mode and inhibits normal operation. Internal testing is not visible on biphase output
channels.
7
[0]
Service Request. A logic one sets the Service Request bit of the Status Register.
CONTROL REGISTER (WRITE ONLY)
X
X
X
X
X
X
X
X
SRV
RQ
SELF
TEST
SELF
CH
SUBS
BUSY
TF
CH B
EN
CH A
EN
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
LSB
MSB
[ ] defines reset state
Figure 4. Control Register
System Register (Read Only)
The 16-bit read-only System Register provides the RTI system status. Read the System Register by applying a logic zero to
CS, CTRL, ADDR IN (0), and a logic one to RD/WR. The 16-bit contents of the System Register are read from data I/O pins
DATA(15:0).
Bit
Initial
Number
Condition
Description
0
[0]
MCSA(0). The LSB of the mode code or subaddress as indicated by the
logic state of bit 5.
1
[0]
MCSA(1). Mode code or subaddress as indicated by the state of bit 5.
2
[0]
MCSA(2). Mode code or subaddress as indicated by the state of bit 5.
3
[0]
MCSA(3). Mode code or subaddress as indicated by the state of bit 5.
4
[0]
MCSA(4). Mode code or subaddress as indicated by the state of bit 5.
5
[0]
MC/SA. A logic one indicates that bits 4 through 0 are the subaddress of
the last command word, and that the last command word was a normal
transmit orreceive command. A logic zero indicates that bits 4 through 0
are a mode code, and that the last command was a mode code.
6
[1]
Channel A/B. A logic one indicates that the most recent command arrived
onChannel A; a logic zero indicates that it arrived on Channel B.
RTI-5
7
[0]
Channel B Enabled. A logic one indicates that Channel B is available for
both reception and transmission.
8
[0]
Channel A Enabled. A logic one indicates that Channel A is available for
both reception and transmission.
9
[1]
Terminal Flag Enabled. A logic one indicates that the Bus Controller has
not issued an Inhibit Terminal Flag mode code. A logic zero indicates that
the Bus Controller, via the above mode code, is overriding the host system’s ability to set the Terminal Flag bit of the status word.
10
[0]
Busy. A logic one indicates the Busy bit is set. This bit is reset when the
SystemBusy bit in the Control Register is reset.
11
[0]
Self-Test. A logic one indicates that the RTI is in the self-test mode. This
bit isreset when the self-test is terminated.
12
[0]
TA Parity Error. A logic one indicates the wrong Terminal Address parity;
it causes the biphase inputs to be disabled and a message error condition.
This bit is reset by reloading the terminal address latch with correct parity.
13
[0]
Message Error. A logic one indicates that a message error has occurred
since the last System Register read. This bit is not reset until the System
Register has been examined and the message error condition is removed.
14
[0]
Valid Message. A logic one indicates that a valid message has been
received since the last System Register read. This bit is not reset until the
System Register has been examined.
15
[0]
Terminal Active. A logic one indicates the device is executing a transmit or
receive operation. The state of this bit is the logical NAND of the external
XMIT and RCV pins.
SYSTEM REGISTER (READ ONLY)
TERM
ACTV
VAL
MESS
MESS
ERR
TAPA
ERR
SELFTEST
BUSY
TFEN
CH A
EN
CH B
EN
CHNL
A/B
[0]
[0]
[0]
[0]
[0]
[0]
[1]
[0]
[0]
[1]
MSB
[0]
MCSA
4
MCSA
3
[0]
[0]
MCSA MCSA
2
1
[0]
[0]
MCSA
0
[0]
LSB
[ ] defines reset state
Figure 5. System Registers
RTI-6
MC/
SA
Last Command Register (Read Only)
The 16-bit read-only Last Command Register provides the host with last command and operational status information. The
RTI transmits the lower 11 bits of this register along with terminal address upon receipt of a Transmit Last Command mode
code. Read the Last Command Register by applying a logic zero to CS, CTRL, and a logic one to RD/WR and ADDR IN (0).
The 16-bit contents of the Last Command Register are read from data I/O pins DATA(15:0).
Bit
Initial
Number
Condition
Description
0 through 10
[all 1s]
Least significant 11 bits of the last command word.
11
[0]
Busy Bit. System Register bit 10.
12
[0]
Self-test. System Register bit 11.
13
[1]
Terminal Flag Enabled. System Register bit 9.
14
[1]
Channel A/B. System Register bit 6.
15
[1]
Illegal Command. The RTI illegalized the last command.
1.3 Mode Codes and Subaddresses
The UT1553B RTI provides subaddress and mode code
decoding meeting MIL-STD-1553B. In addition, the device
has automatic internal illegal command decoding for
reserved MIL-STD-1553B mode codes. Upon command
word validation and decode, status pins MCSA(4:0) and
MC/SA become valid. Status pin MC/SA will indicate
whether the data pins MCSA(4:0) are mode code or
subaddress information. Status Register bits 5 through 0
contain the same information as pins MCSA(4:0) and MC/
SA.
Mode codes which involve data transfer are processed like
receive and transmit commands. The RTI will not generate
DMA request for Transmit Status Word and Transmit Last
Command mode codes since the information is stored
internal to the RTI.
The system designer can use signals MCSA(4:0), MC/SA,
BRDCST, XMIT, and RCV to illegalize mode codes,
subaddresses, and other message formats via the Illegal
Command (ILL COMM) input (see figure 23 on
page 36).
For example, the RTI will accept and respond to a Reset
Remote Terminal mode code; however it will not perform
a reset operation. The host must interpret the mode code and
take appropriate action.
The RTI will internally decode the following mode codes
as illegal:
-
Dynamic Bus Control
Selected Transmitter Shutdown
Override Selected Transmitter Shutdown
All Reserved Mode Codes
If the RTI receives one of the above mode codes, the RTI
responds by transmitting a status word with the Message
Error bit set to logic one.
The following mode codes require assistance from the host:
- Synchronize
- Initiate Self-Test
- Reset Remote Terminal
The RTI does not define or interpret the following data
words associated with mode code commands:
- Transmit Vector Word
- Synchronize With Data Word
- Transmit Bit Word
The RTI will accept and respond to mode code with data;
the host must interpret or define the data word. The RTI will
store or retrieve the data required for mode code command
from block #1 of the receive or transmit page
.
RTI-7
RTI MODE CODE HANDLING PROCEDURE
T/R
Mode Code
Function
Operation
0
10100
Selected Transmitter Shutdown 2
1.
2.
3.
4.
0
10101
Override Selected Transmitter
Shutdown 2
1. Command word stored
2. MES ERR pin asserted
3. Message error latch set in System Register
4. Status word transmitted
0
10001
Synchronize (w/data)
1. Command word stored
2. Data word stored
3. Status word transmitted
1
00000
Dynamic Bus Control 2
1. Command word stored
2. MES ERR pin asserted
3. Message error latch set in System Register
4. Status word transmitted
1
00001
Synchronize 1
1. Command word stored
2. Status word transmitted
1
00010
Transmit Status Word 3
1. Command word stored
2. Status word transmitted
1
00011
Initiate Self-Test 1
1. Command word stored
2. Status word transmitted
1
00100
Transmitter Shutdown
1. Command word stored
2. Alternate bus shutdown
3. Status word transmitted
1
00101
Override Transmitter Shutdown
1. Command word stored
2. Alternate bus enabled
3. Status word transmitted
1
00110
Inhibit Terminal Flag Bit
1. Command word stored
2. Terminal Flag bit set to zero and disabled
3. Status word transmitted
1
00111
Override Inhibit Terminal Flag Bit
1. Command word stored Bit
2. Terminal Flag bit enabled, but not set to logic one
3. Status word transmitted
1
01000
Reset Remote Terminal 1
1. Command word stored
2. Status word transmitted
1
10010
Transmit Last Command Word 3
1. Status word transmitted
2. Last command word transmitted
1
10000
Transmit Vector Word
1. Command word stored
2. Status word transmitted
3. Data word transmitted
1
10011
Transmit BIT Word
1. Command word stored
2. Status word transmitted
3. Data word transmitted
Command word stored
MES ERR pin asserted
Message error latch set in System Register
Status word transmitted
Notes:
1. Further host interaction required for mode code operation.
2. Reserved mode code; A) MES ERR pin asserted, B) Message Error bit set, C) status word transmitted (ME bit set to logic one).
3.Status word not affected.
RTI-8
1.4 MIL-STD-1553B Subaddress and Mode Code Definitions
Subaddress Field
Binary (Decimal)
00000 (00)
00001 (01)
00010 (02)
00011 (03)
00100 (04)
00101 (05)
00110 (06)
00111 (07)
01000 (08)
01001 (09)
01010 (10)
01011 (11)
01100 (12)
01101 (13)
01110 (14)
01111 (15)
10000 (16)
10001 (17)
10010 (18)
10011 (19)
10100 (20)
10101 (21)
10110 (22)
10111 (23)
11000 (24)
11001 (25)
11010 (26)
11011 (27)
11100 (28)
11101 (29)
11110 (30)
11111 (31)
Table 1. Subaddress and Mode Code Definitions Per MIL-STD-1553B
Message Format
Receive
Transmit
Description
1
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
1
1
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
1
Mode Code Indicator
Mode Code Indicator
Note:
1. Refer to mode code assignments per MIL-STD-1553B
1.5 Remote Terminal Address
Assign the RTI remote terminal address by either a software
or hardware exercise. The host assigns the RTI remote
terminal address by performing a Control Register write;
the Terminal Address bus (TA(4:0)) is strobed into the RTI
Remote Terminal Address Register upon completion of the
Control Register write. To assign the RTI remote terminal
address via hardware, use the TALEN/PARITY input pin
operating in the terminal latch address enable mode. The
Terminal Address bus is latched into the RTI while the
TALEN is asserted (i.e., logic low). Valid remote terminal
addresses (RTA) include decimal 0 through 31 if Broadcast
is disabled, 0 through 30 if Broadcast is enabled
Parity Checker
An address parity check is performed to insure the remote
terminal address applied to TA(4:0) was properly latched
into the Remote Terminal Address Register. To perform a
parity check, enable the RTI parity circuit via EXT TEST
and EXT TST CH SEL A/B input pins. The parity bit is
entered through the TALEN/PARITY input pin operating in
the parity mode. Input pins EXT TEST and EXT TST CH
SEL A/B control dual-function input pin TALEN/PARITY;
see table 2 for description of operation.
If a parity error exists, the Parity Error bit of the System
Register is set to a logic one, biphase Channels A and B are
disabled (set to logic zero), the Message Error bit set to logic
one, and the message error pin is asserted.
RTI-9
Table 2. Parity Checking
STATE #
EXT TEST
EXT TST CH SEL A/B
Function of TALEN/PARITY
0
0
0
Terminal Address Latch Enable. Active low
signal used to latch TA(4:0) into RTI. Internal
parity checker disabled.
1
0
1
Parity. Internal remote terminal address parity
checker enabled. TALEN/PARITY pin functions as parity bit for TA(4:0) bus. Proper operation requires odd parity.
2
1
0
Terminal Address Latch Enable. Do not assert
EXT TST during reset, otherwise self-test is
invoked.
3
1
1
Terminal Address Latch Enable. Do not assert
EXT TST during reset, otherwise self-test is
invoked.
The following are examples of sequences used to enter
remote terminal addresses into the RTI.
Example 1.
Hardware-Controlled Remote Terminal
Address (parity check disabled):
STATE 0, 2, or 3 (i.e., 00, 10, or 11)
TALEN - asserted (i.e., logic low)
TA(4:0) - valid RTA
Example 2.
Software-Controlled Remote Terminal
Address (parity check disabled):
EXT TEST and EXT TST CH SEL A/B
in STATE 0, 2, or 3 (i.e., 00, 10, or 11)
CTRL - logic zero
CS - logic zero
RD/WR - logic zero
ADDR IN (0) - logic zero
TALEN - logic one
TA(4:0) - valid RTA
Example 3.
Software Controlled Remote Terminal
Address (parity check enabled):
EXT TEST and EXT TST CH SEL A/B
in STATE 1 (i.e., 01)
CTRL - logic zero
CS - logic zero
RD/WR - logic zero
ADDR IN (0) - logic zero
PARITY - input must provide odd
parity
for the TA(4:0) bus
TA(4:0) - valid RTA
For examples 1 and 2, enabling the parity check circuit
(STATE 1) after the remote terminal address is stored results
in a parity check of the data loaded into the Remote Terminal
Address Register.
RTI-10
1.6 Internal Self-Test
Setting bit 6 of the Control Register to a logic one enables
the internal self-test. Disable Channels A and B at this time
to prevent bus activity during self-test by setting bits 0 and
1 of the Control Register to a logic zero. Normal operation
is inhibited when internal self-test is enabled. The RTI’s
self-test capability is based on the fact that the MIL-STD1553B status word sync pulse is identical to the command
word sync pulse. Thus, if the status word from the encoder
is fed back to the decoder, the RTI will recognize the
incoming status word as a command word and thus cause
the RTI to transmit another status word. After the host
invokes self-test, the RTI self-test logic forces a status word
transmission even though the RTI has not received a
command word. The status word is sent to decoder A or B
depending on the channel the host selected for self-test. The
host controls the self-test by periodically changing the bit
patterns in the status word being transmitted. Writing to the
Control Register bits 2, 3, 4, and 8 changes the status word.
Monitor the self-test by sampling either the System Register
or the external status pins (i.e. Command Strobe
(COMSTR), Transmit (XMIT), Receive (RCV)). For a more
detailed explanation of internal self-test, consult the UTMC
publication RTI Internal Self-Test Routine.
1.7 Power-up Master Reset
Reset the RTI by invoking either a hardware or software
master reset after power-up to place the device in a known
state. The master reset clears the decoder and encoder
registers, the command recognition logic, the control and
error logic (which includes the Status, Control and System
Registers), the data transfer logic, and the memory address
control logic. After reset, configure the device for operation
via a Control Register write.
Perform a hardware reset by asserting the MRST input pin
for a minimum of 500ns. During reset negate the EXT TEST
pin (i.e., logic low); assertion of the EXT TEST pin forces
the RTI to enter the external self-test mode of operation.
Software reset the RTI by simultaneously applying a logic
zero to input pins CS, RD/WR, and CTRL while the least
significant bit of the address input bus is a logic one (ADDR
IN (0)=0).
1.8 Encoder and Decoder
The RTI interfaces directly to a bus transmitter/receiver via
the RTI Manchester II encoder/decoder. The UT1553B RTI
receives the command word from the MIL-STD-1553B bus
and processes it either by the primary or secondary decoder.
Each decode checks for the proper sync pulse and
Manchester waveform, edge skew, correct number of bits,
and parity. If the command is a receive command, the RTI
processes each incoming data word for correct word count
and contiguous data. If an invalid message error is detected,
the message error pin is asserted, the RTI ceases processing
the remainder (if any) of the message, and it then suppresses
status word transmission. Upon command validation
recognition, the external status outputs are enabled.
Reception of illegal commands does not suppress status
word transmission.
A timer precludes transmission greater than 730ms by the
assertion of fail-safe timer (TIMERON). This timer is reset
upon receipt of another valid command.
1.9 Illegal Command Decoding
The host has the option of asserting the ILL COMM pin to
illegalize a received command word. On receipt of an illegal
command, the RTI sets the message error bit in the status
BIPHASE IN
CS
COMMAND WORD
P
DS
word, sets the Message Error output, and sets the message
error latch in the System Register.
Use the following RTI outputs to externally decode an
illegal command, Mode Code or Subaddress indicator (MC/
SA), Mode Code or Subaddress bus MCSA(4:0), Command
Strobe (COMSTR), Broadcast (BRDCST), etc. (See figure
6 pages 11-12).
To illegalize a transmit command the ILL COMM pin is
asserted 3.3ms after STATUS goes to a logic one. Assertion
of the ILL COMM pin within 3.3ms allows the RTI to
respond with the Message Error bit of the outgoing status
word at a logic one.
For an illegal receive command, the ILL COMM pin is
asserted within 18.2ms after the COMSTR transitions to a
logic zero in order to suppress data words from being stored
(suppress DMARQ assertions). In addition, the ILL COMM
pin must be at a logic one throughout the reception of the
message until STATUS is asserted.
If the illegal command is mode code 2, 4, 5, 6, 7, or 18,
assert the ILL COMM pin within 664ns after Command
Strobe (COMSTR) transitions to logic zero. Asserting the
ILL COMM pin within the 664 nanoseconds inhibits the
mode code function.
The above timing conditions also apply when the host
externally decodes an illegal broadcast command. The host
must remove the illegal command condition so that the next
command is not falsely decoded as illegal. These
requirements are easily met if the COMSTR output is used
to qualify the ILL COMM input to the RTI.
DATA WORD
P
DS
DATA WORD
P
COMSTR
RCV
18.2µs
ILL COMM
DMA Activity Suppressed
STATUS
SS
BIPHASE OUT
STATUS WORD
P
Note:
1. Illegal command condition; status word Message Error bit set to logic one, RTIMES ERR pin set to a logic one, RTI Status Register Message
Error bit set to logic one.
Figure 6a. Illegal Receive Command Decoding
RTI-11
BIPHASE IN
CS
COMMAND WORD
P
COMSTR
XMIT
1.0µs (min)
ILL COMM
3.3µs
DMA Activity Suppressed
STATUS
BIPHASE OUT
SS
STATUS WORD
P
Note:
1. Illegal command condition; status word Message Error bit set to logic one, RTI MES ERR pin set to a logic one, RTI Status Register
Message Error bit set to logic one.
Figure 6b. Illegal Transmit Command Decoding
BIPHASE IN
CS
COMMAND WORD
P
COMSTR
MC/SA
664ns
ILL COMM
Note:
1. To illegalize mode codes 2, 4, 5, 6, 7, or 18 assert ILL COMM within 664ns of COMSTR’s transition to logic zero. Asserting
the ILL COMM within 664ns inhibits the mode code function.
Figure 6c. Mode Code Command Decoding
2.0 MEMORY MAP EXAMPLE
The RTI is capable of addressing 2048 x 16 of external
memory for message storage. The 2K memory space is
divided into two 1K pages and subdivided into 32 blocks of
32 x 16:
Page 1 (Receive): 32 blocks for receive messages
(32 x 16)
Page 2 (Transmit): 32 blocks for transmit messages
(32 x 16)
Address Decode
The RTI derives addresses (i.e., data pointers) for external
memory directly from the 11 least significant bits of the
command word. The address data pointer corresponds to
ADDR OUT (10:0) during RTI memory accesses.
T/R = ADDR OUT (10)
SUBADDRESS/MODE = ADDR OUT (9:5) WORD
COUNT/MODE CODE = ADDR OUT (4:0)
RTI-12
The T/R bit of the command word becomes the most
significant bit of the data pointer; the T/R bit serves to divide
the RAM into transmit and receive pages of 1K each. The
5-bit subaddress/mode field is used to select 1 of 32 possible
message storage blocks within the transmit or receive
message page. The 5-bit word count/mode code field acts
as a data pointer to select one of 32 locations within the
message storage block. Multiple word messages are stored
from top to bottom within the message storage block.
For mode commands, the address data pointer always
contains 00000 in the MC/SA field, regardless of whether
00000 or 11111 was received. Forcing the mode code field
to 00000 reserves the first message storage block on both
pages (receive and transmit) for mode code messages that
require data. The 5-bit mode code specifies which of the 32
locations within the message storage block to access.
For “wrap-around” applications (transmission of data
previously received), force the RTI to store and receive
messages on one memory page. To accomplish one-page
operation do not use the T/R output pin. Eliminating the T/
R limits the RTI access to only one page and the RTI will
not differentiate between receive and transmit pages.
Table 3. RTI Memory Map
1: Receive Memory Map
Block #
1
2
Operation
Mode Code 1
Subaddress 1
3
Subaddress 2
4
Subaddress 3
5
2: Transmit Memory map
Address Field (hex)
000 to 01F
020 to 03F
Block #
1
2
Operation
Mode Code 1
Subaddress 1
Address Field (hex)
400 to 41F
420 to 43F
040 to 05F
3
Subaddress 2
440 to 45F
060 to 07F
4
Subaddress 3
460 to 47F
Subaddress 4
080 to 09F
5
Subaddress 4
480 to 49F
6
Subaddress 5
0A0 to 0BF
6
Subaddress 5
4A0 to 4BF
7
Subaddress 6
0C0 to 0DF
7
Subaddress 6
4C0 to 4DF
8
Subaddress 7
0E0 to 0FF
8
Subaddress 7
4E0 to 4FF
9
Subaddress 8
100 to 11F
9
Subaddress 8
500 to 51F
10
Subaddress 9
120 to 13F
10
Subaddress 9
520 to 53F
11
Subaddress 10
140 to 15F
11
Subaddress 10
540 to 55F
12
Subaddress 11
160 to 17F
12
Subaddress 11
560 to 57F
13
Subaddress 12
180 to 19F
13
Subaddress 12
580 to 59F
14
Subaddress 13
1A0 to 1BF
14
Subaddress 13
5A0 to 5BF
15
Subaddress 14
1C0 to 1DF
15
Subaddress 14
5C0 to 5DF
16
Subaddress 15
1E0 to 1FF
16
Subaddress 15
5E0 to 5FF
17
Subaddress 16
200 to 21F
17
Subaddress 16
600 to 61F
18
Subaddress 17
220 to 23F
18
Subaddress 17
620 to 63F
19
Subaddress 18
240 to 25F
19
Subaddress 18
640 to 65F
20
Subaddress 19
260 to 27F
20
Subaddress 19
660 to 67F
21
Subaddress 20
280 to 29F
21
Subaddress 20
680 to 69F
22
Subaddress 21
2A0 to 2BF
22
Subaddress 21
6A0 to 6BF
23
Subaddress 22
2C0 to 2DF
23
Subaddress 22
6C0 to 6DF
24
Subaddress 23
2E0 to 2FF
24
Subaddress 23
6E0 to 6FF
25
Subaddress 24
300 to 31F
25
Subaddress 24
700 to 71F
26
Subaddress 25
320 to 33F
26
Subaddress 25
720 to 73F
27
Subaddress 26
340 to 35F
27
Subaddress 26
740 to 75F
28
Subaddress 27
360 to 37F
28
Subaddress 27
760 to 77F
29
Subaddress 28
380 to 39F
29
Subaddress 28
780 to 79F
30
Subaddress 29
3A0 to 3BF
30
Subaddress 29
7A0 to 7BF
31
Subaddress 30
3C0 to 3DF
31
Subaddress 30
7C0 to 7DF
32
Unused
3E0 to 3FF
32
Unused
7E0 to 7FF
Notes:
1. Receive mode codes with data:
- Synchronize with data
- Selected Transmitter Shutdown (Illegal)
- Override Selected Transmitter Shutdown (Illegal)
2. Transmit mode codes with data:
- Transmit Vector Word
- Transmit Bit Word
RTI-13
3.0 PIN IDENTIFICATION AND DESCRIPTION
BIPHASE
OUT
BIPHASE
IN
TERMINAL
ADDRESS
MODE/CODE
SUBADDRESS
STATUS
SIGNALS
CONTROL
SIGNALS
BIPHASE OUT A O
27 (L8)
BIPHASE OUT A Z
28 (K8)
BIPHASE OUT B O
32 (L11)
BIPHASE OUT B Z
30 (L10)
BIPHASE IN A O
BIPHASE IN A Z
37 (H10)
39 (G9)
BIPHASE IN B O
33 (K10)
BIPHASE IN B Z
34 (J10)
TA0
64 (C6)
TA1
62 (A7)
TA2
60 (B7)
TA3
58 (B8)
TA4
56 (B9)
TALEN/PARITY
52 (C10)
MCSA0
14 (L2)
MCSA1
16 (K4)
MCSA2
17 (L4)
MCSA3
18 (J5)
MCSA4
19 (K5)
MES ERR
49 (D10)
TIMERON
41 (G11)
COMSTR
22 (J6)
MC/SA
21 (K6)
RCV
51 (B11)
XMIT
38 (H11)
RRD/RWR
45 (E11)
RCS
43 (F9)
STATUS
23 (J7)
CH A/B
26 (L6)
BRDCST
36 (J11)
UT1553B
RTI
(K3) 13
(K1) 9
(H2) 7
(G3) 5
(G1) 3
(F3) 1
(E1) 8
(F2) 8
(D2) 7
(B1) 7
(B2) 7
ADDR IN 0
ADDR IN 1
ADDR IN 2
ADDR IN 3
ADDR IN 4
ADDR IN 5
ADDR IN 6
ADDR IN 7
ADDR IN 8
ADDR IN 9
ADDR IN 10
ADDRESS BUS
ADDR IN(10:0)
(A1)
(B3)
(A2)
(A3)
(B4)
(A4)
(C5)
(B5)
(A5)
(A6)
(C7)
(B6)
(A8)
(A9)
(A10)
(A11)
74
73
72
71
70
69
68
67
66
65
63
61
59
57
55
53
DATA I/O 0
DATA I/O 1
DATA I/O 2
DATA I/O 3
DATA I/O 4
DATA I/O 5
DATA I/O 6
DATA I/O 7
DATA I/O 8
DATA I/O 9
DATA I/O 10
DATA I/O 11
DATA I/O 12
DATA I/O 13
DATA I/O 14
DATA I/O 15
DATA BUS
DATA(15:0)
(L1)
(J2)
(J1)
(H1)
(G2)
(F1)
(E3)
(E2)
(D1)
(C1)
(C2)
11
10
8
6
4
2
84
82
80
78
76
ADDR OUT 0
ADDR OUT 1
ADDR OUT 2
ADDR OUT 3
ADDR OUT 4
ADDR OUT 5
ADDR OUT 6
ADDR OUT 7
ADDR OUT 8
ADDR OUT 9
ADDR OUT 10
ADDRESS BUS
ADDR OUT
(10:0)
(L9) 29
(K9) 31
EXT TEST
TEST
EXT TST CH SEL A/B
(D11) 48
(F11) 47
MEMCK
DMARQ
DMA
BCEN
25 (K7)
(B10) 54
VDD
POWER
CS
44 (E9)
46 (E10)
50 (C11)
VSS
VSS
GROUND
RD/WR
CTRL
(K2) 12
(F10) 42
(K11) 35
12MHz
CLOCK
ADOEN
ILL COMM
15 (L3)
20 (L5)
(L7) 24
(G10) 40
2MHz
MRST
RESET
Note:
Pingrid array numbers are in parentheses. LCC pin numbers are not in parentheses.
Figure 7. UT1553B RTI Pin Description
RTI-14
Legend for TYPE and ACTIVE fields:
TI = TTL input
TUI = TTL input (pull-up)
TDI = TTL input (pull-down)
TO = TTL output
TTO = Three-state TTL output
TTB = Three-state TTL bidirectional
[ ] - Values in parentheses indicate the initialized state of
output pin.
DATA BUS
NAME
PIN NUMBER
LCC
PGA
TYPE
ACTIVE
DESCRIPTION
DATA I/O 15
53
A11
TTB
--
Bit 15 (MSB) of the bidirectional Data
bus.
DATA I/O 14
55
A10
TTB
--
Bit 14 of the bidirectional Data bus.
DATA I/O 13
57
A9
TTB
--
Bit 13 of the bidirectional Data bus.
DATA I/O 12
59
A8
TTB
--
Bit 12 of the bidirectional Data bus.
DATA I/O 11
61
B6
TTB
--
Bit 11 of the bidirectional Data bus.
DATA I/O 10
63
C7
TTB
--
Bit 10 of the bidirectional Data bus.
DATA I/O 9
65
A6
TTB
--
Bit 9 of the bidirectional Data bus.
DATA I/O 8
66
A5
TTB
--
Bit 8 of the bidirectional Data bus.
DATA I/O 7
67
B5
TTB
--
Bit 7 of the bidirectional Data bus.
DATA I/O 6
68
C5
TTB
--
Bit 6 of the bidirectional Data bus.
DATA I/O 5
69
A4
TTB
--
Bit 5 of the bidirectional Data bus.
DATA I/O 4
70
B4
TTB
--
Bit 4 of the bidirectional Data bus.
DATA I/O 3
71
A3
TTB
--
Bit 3 of the bidirectional Data bus.
DATA I/O 2
72
A2
TTB
--
Bit 2 of the bidirectional Data bus.
DATA I/O 1
73
B3
TTB
--
Bit 1 of the bidirectional Data bus.
DATA I/O 0
74
A1
TTB
--
Bit 0 (LSB) of the bidirectional Data bus.
TYPE
ACTIVE
INPUT ADDRESS BUS
NAME
PIN NUMBER
LCC
PGA
75
B2
DESCRIPTION
TI
--
Bit 10 (MSB) of the Address Input bus.
ADDR IN 9
77
B1
TI
--
Bit 9 of the Address Input bus.
ADDR IN 8
79
D2
TI
--
Bit 8 of the Address Input bus.
ADDR IN 7
81
F2
TI
--
Bit 7 of the Address Input bus.
ADDR IN 6
83
E1
TI
--
Bit 6 of the Address Input bus.
ADDR IN 5
1
F3
TI
--
Bit 5 of the Address Input bus.
ADDR IN 4
3
G1
TI
--
Bit 4 of the Address Input bus.
ADDR IN 3
5
G3
TI
--
Bit 3 of the Address Input bus.
ADDR IN 2
7
H2
TI
--
Bit 2 of the Address Input bus.
ADDR IN 1
9
K1
TI
--
Bit 1 of the Address Input bus.
ADDR IN 0
13
K3
TI
--
Bit 0 (LSB) of the Address Input bus.
ADDR IN 10
RTI-15
OUTPUT ADDRESS BUS
NAME
PIN NUMBER
LCC
PGA
76
C2
TYPE
ACTIVE
DESCRIPTION
TTO
--
Bit 10 (MSB) of the Address Output bus.
ADDR OUT 9
78
C1
TTO
--
Bit 9 of the Address Output bus.
ADDR OUT 8
80
D1
TTO
--
Bit 8 of the Address Output bus.
ADDR OUT 7
82
E2
TTO
--
Bit 7 of the Address Output bus.
ADDR OUT 6
84
E3
TTO
--
Bit 6 of the Address Output bus.
ADDR OUT 5
2
F1
TTO
--
Bit 5 of the Address Output bus.
ADDR OUT 4
4
G2
TTO
--
Bit 4 of the Address Output bus.
ADDR OUT 3
6
H1
TTO
--
Bit 3 of the Address Output bus.
ADDR OUT 2
8
J1
TTO
--
Bit 2 of the Address Output bus.
ADDR OUT 1
10
J2
TTO
--
Bit 1 of the Address Output bus.
ADDR OUT 0
11
L1
TTO
--
Bit 0 (LSB) of the Address Output bus.
TYPE
ACTIVE
ADDR OUT 10
REMOTE TERMINAL ADDRESS INPUTS
NAME
PIN NUMBER
LCC
PGA
56
B9
DESCRIPTION
TUI
--
Remote Terminal Address bit 4 (MSB).
TA3
58
B8
TUI
--
Remote Terminal Address bit 3.
TA2
60
B7
TUI
--
Remote Terminal Address bit 2.
TA1
62
A7
TUI
--
Remote Terminal Address bit 1.
TA0
C6
64
TUI
--
Remote Terminal Address bit 0.
TALEN/PARITY
52
C10
TUI
--
Remote Terminal Address Latch Enable/
Remote Terminal Parity Input. Function
of input is defined by he state of pin EXT
TEST and EXT TST CH SEL A/B. For
EXT TEST = 0, EXT TST CH SEL A/B
= 1, TALEN/PARITY must provide odd
parity for the Remote Terminal Address.
For all other states of EXT TEST and
EXT TST CH SEL A/B (i.e., 00, 10, 11)
TALEN/PARITY functions as an active
low address strobe.
TA4
;
RTI-16
MODE CODE/SUBADDRESS OUTPUTS
TYPE
NAME
ACTIVE
PIN NUMBER
LCC
PGA
DESCRIPTION
MC/SA
21
K6
TO
--
MCSA4 19
K5
TO
--
Mode Code/Subaddress 4. If MC/SA is low,
this pin represents the most significant bit of
the the most recent command word (the MSB
of the mode code). If MC/SA is high, this pin
represents the MSB of the subaddress.
MCSA3 18
J5
TO
--
Mode Code/Subaddress 3.
MCSA2 17
L4
TO
--
Mode Code/Subaddress 2.
MCSA1 16
K4
TO
--
Mode Code/Subaddress 1.
MCSA0 14
L2
TO
--
Mode Code/Subaddress 0. If MC/SA is low,
this pin represents the least significant bit of
the the most recent command word. If MC/SA
is high, this pin represents the LSB of the subaddress
Mode Code/Subaddress Indicator. If MC/SA is
low, it indicates that the most recent command
word is a mode code command. If MC/SA is
high, it indicates that the most recent command
word is for a subaddress. This output indicates
whether the mode code/subaddress outputs
(i.e., MCSA(4:0)) contain mode code or subaddress information.
BIPHASE INPUTS
NAME
BIPHASE IN A Z
PIN NUMBER
LCC
PGA
39
G9
DESCRIPTION
TI
--
Receiver - Channel A, Zero Input. Idle low
Manchester input from the 1553 bus transceiver.
BIPHASE IN A O
37
H10
TI
--
Receiver - Channel A, One Input. This input is
thecomplement of BIPHASE IN A Z.
BIPHASE IN B Z
34
J10
TI
--
Receiver - Channel B, Zero Input. Idle low
Manchester input from the 1553 bus transceiver.
BIPHASE IN B O
33
K10
TI
--
Receiver - Channel B, One Input. This input is
the complement of BIPHASE IN B Z.
RTI-17
BIPHASE OUTPUTS
PIN NUMBER
LCC
PGA
28
K8
NAME
BIPHASE OUT A Z
TYPE
ACTIVE
DESCRIPTION
TO
--
Transmitter - Channel A, Zero Output. This
Manchester-encoded data output is connected
to the 1553 bus transmitter input. The output is
idle low.
BIPHASE OUT A O
27
L8
TO
--
Transmitter - Channel A, One Output. This
output is the complement of BIPHASE OUT
A Z. The output is idle low.
BIPHASE OUT B Z
30
L10
TO
--
Transmitter - Channel B, Zero Output. This
Manchester-encoded data output is connected
to the 1553 bus transmitter. The output is idle
low.
BIPHASE OUT B O
32
L11
TO
--
Transmitter - Channel B, One Output. This
output is the complement of BIPHASE OUT
B Z. The output is idle low.
MASTER RESET AND CLOCK
NAME
PIN NUMBER
LCC
PGA
TYPE
ACTIVE
DESCRIPTION
MRST
40
G10
TUI
AL
Master Reset. Initializes all internal functions of the
RTI. MRST must be asserted 500 nanoseconds
before normal RTI operation. (500ns minimum).
12MHz
35
K11
TI
--
12MHz Input Clock. This is the RTI system clock
that requires an accuracy greater than 0.01% with a
duty cycle from 50% ±10%.
2MHz
24
L7
TO
--
2MHz Clock Output. This is a 2MHz output generated by the 12MHz input clock. This clock is
stopped when MRST is low.
POWER AND GROUND
NAME
VDD
VSS
RTI-18
PIN NUMBER
LCC
PGA
54
B10
12
42
K2
F10
TYPE
ACTIVE
DESCRIPTION
PWR
--
+5VDC. Power supply must be +5VDC ±10%.
GND
GND
---
Ground reference. Zero VDC logic ground.
CONTROL PINS
NAME
PIN NUMBER
LCC
PGA
TYPE
ACTIVE
DESCRIPTION
CS
44
E9
TI
AL
Chip Select. Active low input for host access of
transparent memory or the RTI internal registers. In
the transparent memory configuration CS is propagated through the RTI to the RCS output.
CTRL
50
C11
TI
AL
Control. The host processor uses the active low
CTRL input signal in conjunction with CS and RD/
WR to access the RTI internal registers. CTRL is
also used in the software assignment of the terminal
address and programmed reset.
ADOEN
15
L3
TI
AL
Address Output Enable. When ADOEN is low the
Address Out bus (ADDR OUT (15:0)) is active. If
ADOEN = 1 the Address Out bus is high impedance.
RD/WR
46
E10
TI
--
Read/Write. The host processor uses a high level on
this input in conjunction with CS and CTRL to read
the RTI internal registers. A low level on this input is
used in conjunction with CS and CTRL to write to
internal RTI registers. In the transparent memory
configuration RD/WR is propagated through the RTI
to the RRD/RWR output.
BCEN
25
K7
TUI
AL
Broadcast Enable. Active low input enables broadcast commands.
ILL COMM
20
L5
TDI
AH
Illegal Command. The host processor uses the ILL
COMM input to inform the RTI that the present
command is illegal. ILL COMM is used in conjunction with MCSA(4:0) and MC/SA to define system
dependent illegal commands.
RTI-19
STATUS OUTPUTS
NAME
PIN NUMBER
LCC
PGA
TYPE
ACTIVE
DESCRIPTION
RCS
43
F9
TO
AL
RRD/RWR
45
E11
TO
--
RAM Read/Write. High output enables memory
read, low output enables memory write, used in
conjunction with RCS). Normally high output.
COMSTR
22
J6
TO
AL
Command Strobe. COMSTR is an active low
output of 500ns duration identifying receipt of a
valid command.
TIMERON
41
G11
TO
AL
Fail-safe Timer. The TIMERON output pulses
low for 730ms when the RTI begins transmitting (i.e., rising edge of STATUS) to provide a
fail-safe timer meeting the requirements of
MIL-STD-1553B. This pulse is reset when
COMSTR goes low or during Master Reset. in
the external self-test mode TIMERON does not
recognize COMSTR and resets after 730ms.
MES ERR
49
D10
TO
AH
Message Error. The active high MES ERR output signals that the Message Error bit in the Status Register has been set due to receipt of an
invalid command or an error during message
sequence. MES ERR will reset to logic zero on
receipt of next valid command.
CH A/B
26
L6
TO
--
Channel A/B. Output identifying the channel on
which the most recent valid command was
received. Channel A = 1, Channel B = 0.
XMIT
38
H11
TO
AL
Transmit. Active low output identifies a
transmit command message transfer by the RTI
is in progress.
RCV
51
B11
TO
AL
Receive. Active low output identifies a receive
command message transfer by the RTI is in
progress.
BRDCST
36
J11
TO
AL
Broadcast. BRDCST is an active low output
that identifies receipt of a valid broadcast command.
STATUS
23
J7
TO
AH
Status. Active high output pulse indicating that
the RTI is in the process of transmitting a status
word.
RTI-20
RAM Chip Select. Active low output used to
enable memory for access.
BUS ARBITRATION
NAME
DMARQ
PIN NUMBER
LCC
PGA
47
F11
TYPE
ACTIVE
DESCRIPTION
TO
AH
Direct Memory Access Request. Active high
output requesting RTI access to memory.
MEMCK
48
D11
TI
AL
Memory Clock (DMA Grant). Active low input
signaling the RTI that a memory access is
granted. Internal to the RTI, receipt of MEMCK
generates RAM chip select and RAM read/write
signals.
EXT TST
29
L9
TDI
--
External Self-test Enable. Multi-function input
pin. In self-test mode forcing this pin high
allows the monitoring of self-test activity at the
bus stub. When the RTI is not in self-test this
pin defines the function of TALEN/PARITY.
EXT TST CH SEL
A/B
31
K9
TUI
--
External Self-test Channel Select. A/B Multifunction input pin. In self-test mode forcing this
pin high selects the channel on which the selftest is performed (Channel A = 1, Channel B =
0). When the RTI is not in self-test this pin
defines the function of TALEN/PARITY.
4.0 OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
(referenced to VSS)
1
SYMBOL
PARAMETER
LIMITS
UNIT
VDD
DC supply voltage
-0.3 to +7.0
V
VIO
Voltage on any pin
-0.3 to VDD+0.3
V
II
DC input current
±10
mA
TSTG
Storage temperature
-65 to +150
°C
PD
Maximum power dissipation
300
mW
TJ
Maximum junction temperature
+175
°C
ΘJC
Thermal resistance, junction-to-case
20
°C/W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not
recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
SYMBOL
PARAMETER
LIMITS
UNIT
VDD
DC supply voltage
4.5 to 5.5
V
VIN
DC input voltage
0 to VDD
V
TC
Temperature range
-55 to +125
°C
FO
Operating frequency
12 ± .01%
MHz
RTI-21
5.0 DC ELECTRICAL CHARACTERISTICS
(VDD = 5.0V ± 10%; -55°C < TC < +125°C)
SYMBOL
VIL
PARAMETER
Low-level input voltage
CONDITION
MINIMUM
VIH
High-level input voltage
IIN
Input leakage current
TTL inputs
Inputs with pull-down resistors
Inputs with pull-up resistors
VIN = VDD or VSS
VIN = VDD
VIN = VSS
VOL
Low-level output voltage
IOL = 4mA
VOH
High-level output voltage
IOH = -400µA
2.4
IOZ
Three-state output
leakage current
VO = VDD or VSS
-10
IOS
Short-circuit output current 1, 2
VDD = 5.5V, VO = VDD
VDD = 5.5V, VO = 0V
-90
MAXIMUM
0.8
2.0
UNIT
V
V
-10
110
-2750
10
2750
-110
µA
µA
µA
0.4
V
V
+10
µA
90
mA
mA
CIN
Input capacitance 3
ƒ = 1MHz @ 0V
10
pF
COUT
Output capacitance 3
ƒ = 1MHz @ 0V
15
pF
CIO
Bidirect I/O capacitance 3
ƒ = 1MHz @ 0V
25
pF
IDD
Average operating current 1, 4
ƒ = 12MHz, CL = 50pF
50
mA
QIDD
Quiescent current
Note 5
1.5
mA
Notes:
1. Supplied as a design limit but not guaranteed or tested.
2. Not more than one output may be shorted at a time for a maximum duration of one second.
3. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.
4. Includes current through input pull-ups. Instantaneous surge currents on the order of 1 ampere can occur during output switching.
Voltage supply should be adequately sized and decoupled to handle a large surge current.
5. All inputs with internal pull-ups or pull-downs should be left open circuit. All other inputs tied high or low.
10 11 12 13 14
5
1
5
SUBADDRESS/MODE
CODE
DATA WORD
ADDRESS
DATA
P
1
1
1
SERVICE REQUEST
SYNC
REMOTE TERMINAL
RESERVED
Figure 8. MIL-STD-1553B Word Formats
RTI-22
DATA WORD COUNT/
MODE CODE
1
INSTRUMENTATION
5
STATUS WORD
1
P
16
MESSAGE ERROR
SYNC
5
1
1
1
1
1
1
PARITY
T/R
20
TERMINAL FLAG
REMOTE TERMINAL
ADDRESS
15 16 17 18 19
DYNAMIC BUS CONTROL ACCEPTANCE
SYNC
9
SUBSYSTEM FLAG
COMMAND
WORD
45678
BUSY
123
BROADCAST COMMAND RECEIVED
BIT TIMES
6.0 AC ELECTRICAL CHARACTERISTICS
3, 4
(Over recommended operating conditions)
INPUT
VIH MIN
VIL MAX
1
VIH MIN
VIL MAX
2
tb
ta
IN-PHASE
OUTPUT
OUT-OF-PHASE
OUTPUT
1
2
1
2
VOH MIN
VOL MAX
td
tc
VOH MIN
VOL MAX
te
VOH MIN
VOL MAX
BUS
tf
tg
th
SYMBOL
PARAMETER
ta
INPUT↑
to response↑
tb
INPUT↓
INPUT↑
INPUT↓
INPUT↓
INPUT↓
INPUT↑
INPUT↑
to response↓
to response↓
to response↑
to data valid
to high Z
to high Z
to data valid
tc
td
te
tf
tg
th
Notes:
1. Timing measurements made at (VIH MIN + VIL MAX)/2.
2. Timing measurements made at (VOL MAX + VOH MIN)/2.
3. Based on 50pF load.
Figure 9a. Typical Timing Measurements
5V
IREF (source)
3V
90%
∑
90%
VREF
10%
50pF
10%
0V
IREF (sink)
Note:
30pF including scope probe and test socket
< 2ns
< 2ns
Input Pulses
Figure 9b. AC Test Loads and Input Waveforms
RTI-23
t10a
DMARQ
t10b
t10e
MEMCK
t10d
RCS
t10c
RRD/RWR
t10i
t10h
t10g
t10f
DATA BUS
ADDR OUT BUS
Figure 10. RTI Memory Write
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
t10a
ADDR OUT valid to DMARQ active 3
883
992
ns
t10b
DMARQ active to MEMCK active 2, 3
0
-
ns
t10c
MEMCK active to RCS active 4
-
67
ns
t10d
MEMCK inactive to RCS inactive 4
-
61
ns
t10e
MEMCK pulse width 1, 2, 4
83
-
ns
t10f
MEMCK active to DATA bus valid 4
-
115
ns
t10g
MEMCK inactive
to DATA bus high
impedance 3
5
101
ns
t10h
MEMCK active to RRD/RWR active
-
61
ns
t10i
MEMCK inactive to RRD/RWR inactive
-
58
ns
Notes:
1. Allows a 20ns data valid set-up time before RCS and RRD/RWR go high.
2. The sum tb + te must not exceed 18.8ms.
3. Supplied as a design limit, but not guaranteed or tested.
4. Guaranteed by test.
RTI-24
t11a
DMARQ
t11h
t11b
t11e
MEMCK
t11d
RCS
t11c
t11g
t11f
DATA BUS
ADDR OUT BUS
Figure 11. RTI Memory Read
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
883
992
ns
t11a
ADDR OUT valid to DMARQ active 3
t11b
DMARQ active to MEMCK active 3
0
14.9
µs
t11c
MEMCK active to RCS active 4
-
67
ns
t11d
MEMCK inactive to RCS inactive 4
-
61
ns
t11e
MEMCK pulse width 1, 2, 4
50
-
ns
t11f
Input DATA valid to MEMCK inactive 4
45
-
ns
t11g
Input DATA valid after RCS inactive 4
5
-
ns
t11h
DMARQ active to MEMCK inactive 4
-
18.3
µs
Notes:
1. Allows a 20ns data valid set-up time before RCS and RRD/RWR go high.
2. The sum tb + te must not exceed 18.8ms.
3. Supplied as a design limit, but not guaranteed or tested.
4. Guaranteed by test.
RTI-25
ADDR IN (0)
t12c
t12d
WRITE CONTROL
(CNTRL + CS + RD/WR)
Logical OR
t12b
t12a
DATA BUS
Figure 12. Control Register Write Timing
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
t12a
Input DATA valid before WRITE 3
CONTROL inactive (set-up time)
20
-
ns
t12b
Input DATA valid after WRITE 3
CONTROL inactive (hold-time)
25
-
ns
t12c
ADDR IN1,valid
before WRITE CONTROL
asserts 3
20
-
ns
t12d
ADDR IN 2,
valid after WRITE CONTROL
negates 3
20
-
ns
Notes:
1. Set-up time required to prevent inadvertent software reset.
2. Hold-time required to prevent inadvertent software reset.
3. Guaranteed by test.
RTI-26
ADDR IN (0)
READ CONTROL
(CNTRL + CS )
Logical OR 1, 2
t13b
t13c
DATA BUS
t13a
Figure 13. System and Last Command Register Read Timing
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
t13a
DATA bus valid after READ CONTROL
valid whilve ADDR IN (0) = 0 or 1
-
132
ns
t13b
DATA bus valid after ADDR IN (0) = 0 or
1 while READ CONTROL = 0
-
70
ns
t13c
READ CONTROL 3negation to DATA bus
high impedance
-
101
ns
Notes:
1. ADDR IN (0) = 0 System Register read.
2. ADDR IN (0) = 1 Last Command Register read.
3. Supplied as a design limit but not guaranteed or tested.
RTI-27
TIMERON
t14c
t14a
STATUS
t14b
BIPHASE OUT
t14d
COMSTR
Figure 14. RT Fail-Safe Timer Signal Relationships
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
t14a
STATUS active to TIMERON active 1
4
31
ns
t14b
TIMERON active to first BIPHASE OUT
transition 1
1.2
-
ms
t14c
TIMERON low pulse width 1
-
732
ms
t14d
COMSTR active to TIMERON reset 1
-
31
ns
Note:
1. Supplied as a design limit, but not guaranteed or tested.
RTI-28
CS
t15b
RCS
t15a
RD/WR
t15dv
t15c
RRD/RWR
ADDR IN BUS
t15e
t15f
ADDR OUT BUS
t15g
t15h
ADOEN
t15i
t15j
MEMCK
Figure 15. RTI Propagation Delays
SYMt15a
t15b
MINIMUM
PARAMETER
CS active to RCS active 2
CS negation to RCS negation
2
2
t15c
RD/WR active to RRD/RWR active
t15d
RD/WR negation to RRD/RWR negation 2
t15e
CS active to ADDR OUT valid
2
2
MAXIMUM
UNITS
-
48
ns
-
40
ns
-
45
ns
-
35
ns
6
52
ns
-
44
ns
t15f
ADDR IN valid to ADDR OUT valid
t15g
ADOEN negation
to ADDR OUT high
impedance 1
-
42
ns
t15h
ADOEN active to ADDR OUT active 2
6
50
ns
t15i
CS active to MEMCK active1
(MEMCK not recognized)
13
-
ns
t15j
CS negation to MEMCK
active
(MEMCK recognized) 1
10
-
ns
Note:
1. Supplied as a design limit, but not guaranteed or tested.
2. Guaranteed by test.
RTI-29
3
BIPHASE IN
COMMAND
P
t16a
t16b
COMSTR
RCV
XMIT
t16c
CH A/B
BRDCST
MC/SA
MCSA(4:0)
ADDR OUT 1
MESS ERR
t16d
t16e
Figure 16. Command Word Validation
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
t16a
Command word parity
to COMSTR and
RCV or XMIT active 4
3.58
3.67
µs
t16b
COMSTR pulse width 4
499
502
ns
t16c
Command word parity to CH A/B valid 4
2.58
2.66
µs
t16d
Status output
signals valid to COMSTR
active 2, 4
430
-
ns
t16e
MES ERR reset after COMSTR active 4
745
750
ns
Notes:
1. ADOEN is asserted (i.e., logic low).
2. Status signals include BRDCST, MC/SA, MCSA(4:0), and ADDR OUT.
3. Measured from mid-bit parity crossing.
4. Supplied as a design limit, but not guaranteed or tested.
RTI-30
1
BIPHASE IN
DATA
P
t17a
2
SYNC
BIPHASE OUT
STATUS
P
t17b
DMARQ
t17c
t17d
STATUS
RCV
t17e
ADDR OUT
Figure 17. Receive Command Message Processing
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
t17a
Data word 1,
parity bit to status word
response 3
8.80
9.37
µs
t17b
Data word parity bit to DMARQ active 2, 3
3.58
3.68
µs
t17c
STATUS active to BIPHASE OUT active 3
1.24
1.25
µs
t17d
STATUS pulse width 3
4.48
4.98
µs
t17e
ADDR OUT valid before DMARQ (H) 3
0.90
-
µs
Notes:
1. Measured from last data word mid-bit parity crossing.
2. Measured from transmitted status word sync field mid-bit crossing.
3. Supplied as a design limit, but not guaranteed or tested.
RTI-31
BIPHASE
20
0 20
0
t18a
DMARQ
t18b
t18c
XMIT
Figure 18. Transmitted Data Timing
SYM-
PARAMETER
* t18a
DMARQ active to sync field of transmitted
data word
* t18b
DMARQ active to DMARQ active
* t18c
XMIT negation after last DMARQ active
Note:
* Supplied as a design limit but not guaranteed or tested.
RTI-32
UNITS
MINIMUM
MAXIMUM
17.15
17.18
µs
-
19.2
µs
460
500
µs
1
BIPHASE IN
DATA/CMD
P
t19a
BIPHASE
2
STATUS
SYNC
t19b
P
COMSTR
t19c
STATUS
t19e
XMIT
MES ERR
t19d
t19f
t19g
Figure 19. Mode Command Message Processing
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
* t19a
Response time
BIPHASE IN to BIPHASE OUT 2
3.58
3.67
µs
* t
19b
Command word parity bit to COMSTR assertion 1
8.80
9.37
µs
* t
19c
STATUS active to BIPHASE OUT active
1.24
1.25
µs
* t
19d
STATUS pulse width
4.48
4.98
µs
* t
19e
Command word parity bit to XMIT assertion
3.58
3.67
µs
* t
19f
XMIT pulse width for mode code reception
1.00
-
µs
* t
19g
Command word parity bit to MES ERR assertion
6.57
6.68
µs
Notes:
1. Measured from data or command word mid-bit parity crossing.
2. Measured from transmitted status word sync field mid-bit crossing.
* Supplied as a design limit but not guaranteed or tested.
RTI-33
1
BIPHASE IN
DATA
P
t20a
MES ERR
1
BIPHASE IN
RCV CMD
P
XMIT CMD
P
t20b
MES ERR
Figure 20. Message Error
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
* t20a
Data word parity bit to MES ERR
assertion 1
23.50
23.63
µs
* t
20b
Command word parity bit to MES ERR
assertion RT to RT transfer 2
55.4
55.5
µs
Notes:
1. Measured from last data word mid-bit parity crossing.
2. No response from transmitter.
* Supplied as a design limit but not guaranteed or tested.
RTI-34
ADDR IN (10:0)
DATA(15:0)
HOST
SUBSYSTEM
UT1553B
RTI
CONTROL
UT63M125
1553 TRANSCEIVER
1553 BUS A
1553 BUS B
Figure 21. RTI General System Diagram (Idle low interface)
IN O
IN Z
RXOUT
RXOUT
BIPHASE
CHANNEL A
TXIN-
CHANNEL A
TXIN
TXIN
OUT O
OUT Z
UTMC
63M125
RTI
BIPHASE
CHANNEL B
RXOUT
RXOUT
IN O
IN Z
TXINHB
OUT O
OUT Z
CHANNEL B
TXIN
TXIN
TIMERON
LOGIC
CH A/B
Figure 22. RTI Transceiver Interface Diagram
RTI-35
RTI
MC/SA
MCSA0
MCSA1
MCSA2
MCSA3
MCSA4
ILLEGAL
COMMAND
DECODER
COMSTR
BRDCST
RCV
XMIT
ILL COMM
Figure 23. Mode Code/Subaddress Illegalization Circuit
BIPHASE IN C
COMMAND
P D
DATA
P D
DATA
P
COMSTR
RC
DMARQ
MEMCK
RC
RRD/RWR
ADDR OUT BUS
DATA
BUS
VALID
VALID
STATUS
BIPHASE OUT
SS
Figure 24. Receive Command with Two Data Words
RTI-36
STATUS WORD
P
BIPHASE IN CS COMMAND
P
COMSTR
XMIT
DMARQ
MEMCK
RCS
RRD/RWR
ADDR OUT BUS
VALID
DATA
BUS
VALID
STATUS
BIPHASE OUT
SS
STATUS WORD
P DS
DATA WORD
P DS
DATA WORD
Figure 25. Transmit Command with Two Data Words
RTI-37
PACKAGE OUTLINE DRAWINGS
L
K
J
H
G
F
E
D
C
B
A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DATA I/O 0
DATA I/O 2
DATA I/O 3
DATA I/O 5
DATA I/O 8
DATA I/O 9
TA 1
DATA I/O 12
DATA I/O 13
DATA I/O 14
DATA I/O 15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
ADDR IN 9
ADDR IN 10
DATA I/O 1
DATA I/O 4
DATA I/O 7
DATA I/O 11
TA 2
TA 3
TA 4
VDD
RCV
L
L
L
L
L
L
L
L
L
L1
L1
K
K
K
K
K
K
K
K
K
K1
K1
J
J
J
J
J
J1
J1
H
H
H1
H1
G
G
G
G
G1
G1
F
F
F
F
F1
F1
E
E
E
E
E1
E1
D
D
D1
D1
C
C
C1
C1
B
B
B
A
A
1
2
C
C
C
B
B
B
B
B
B
B1
B1
A
A
A
A
A
A
A
A1
A1
3
4
5
6
7
8
9
10
11
F1
F2
F3
F9
F10
F11
ADDR OUT 5
ADDR IN 7
ADDR IN 5
RCS
VSS
DMARQ
ADDR OUT 8
ADDR IN 8
MES ERR
MEMCK
G1
G2
G3
G9
G10
G11
ADDR IN 4
ADDR OUT 4
ADDR IN 3
BIPHASE IN A Z
MRST
TIMERON
ADDR IN 6
ADDR OUT 7
ADDR OUT 6
CS
RD/WR
RRD/RWR
H1
H2
H10
H11
ADDR OUT 3
ADDR IN 2
BIPHASE IN A O
XMIT
C1
C2
C5
C6
C7
C10
C11
ADDR OUT 9
ADDR OUT 10
DATA I/O 6
TA 0
DATA I/O 10
TALEN/PARITY
CTRL
D1
D2
D10
D11
E1
E2
E3
E9
E10
E11
J1
J2
J5
J6
J7
J10
J11
ADDR OUT 2
ADDR OUT 1
MCSA 3
COMSTR
STATUS
BIPHASE IN B Z
BRDCST
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
ADDR IN 1
VSS
ADDR IN 0
MCSA 1
MCSA 4
MC/SA
BCEN
BIPHASE OUT A Z
EXT TST CH SEl A/B
BIPHASE IN B O
12MHz
Figure 26a. UT1553B RTI Pingrid Array Configuration
(Bottom View)
RTI-38
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
ADDR OUT 0
MCSA 0
ADOEN
MCSA 2
ILL COMM
CH A/B
2MHz
BIPHASE OUT A
EXT TEST
BIPHASE OUT B
BIPHASE OUT B
11 10
9
8
7
6
5
4
3
2
1
84 83 82 81 80 79 78 77 76 75
12
74
13
73
14
72
15
71
16
70
17
69
18
68
19
67
20
66
21
65
22
64
23
63
24
62
25
61
26
60
27
59
28
58
29
57
30
56
31
55
32
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
ADDR IN 5
ADDR OUT 5
ADDR IN 4
ADDR OUT 4
ADDR IN 3
ADDR OUT 3
ADDR IN 2
ADDR OUT 2
ADDR IN 1
ADDR OUT 1
ADDR OUT 0
VSS
ADDR IN 0
MCSA0
ADOEN
MCSA1
MCSA2
MCSA3
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
MCSA 4
38
ILL COMM
39
MC/SA
40
COMSTR
41
STATUS
42
2MHz
BCEN
43
CH A/B
44
BIPHASE OUT A O 45
BIPHASE OUT A Z 46
EXT TEST
47
BIPHASE OUT B Z 48
EXT TST CH SEL A/B49
BIPHASE OUT B O 50
BIPHASE IN B O
51
BIPHASE IN B Z
52
12MHz
53
BRDCST
54
BIPHASE IN A O
XMIT
BIPHASE IN A Z
MRST
TIMERON
VSS
RCS
CS
RRD/RWR
RD/WR
DMARQ
MEMCK
MES ERR
CTRL
RCV
TALEN/PARITY
DATA I/O 15
VDD
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DATA I/O 14
TA4
DATA I/O 13
TA3
DATA I/O 12
TA2
DATA I/O 11
TA1
DATA I/O 10
TA0
DATA I/O 9
DATA I/O 8
DATA I/O 7
DATA I/O 6
DATA I/O 5
DATA I/O 4
DATA I/O 3
DATA I/O 2
73
74
75
76
77
78
79
80
81
82
83
84
DATA I/O 1
DATA I/O 0
ADDR IN 10
ADDR OUT 10
ADDR IN 9
ADDR OUT 9
ADDR IN 8
ADDR OUT 8
ADDR IN 7
ADDR OUT 7
ADDR IN 6
ADDR OUT 6
Figure 26b. UT1553B RTI Chip Carrier Configuration
(Top View)
RTI-39
Package Selection Guide
RTI
24-pin DIP
(single cavity)
36-pin DIP
(dual cavity)
68-pin PGA
84-pin PGA
144-pin PGA
84-lead LCC
36-lead FP
(dual cavity)
(50-mil ctr)
84-lead FP
132-lead FP
RTMP
RTR
Product
BCRT BCRTM BCRTMP
RTS
XCVR
X
X
X
X
X
X
X
X1
X
X1
X
X
X
X
X
X
X
NOTE:
1. 84LCC package is not available radiation-hardened.
Packaging-1
D
1.565 ± 0.025
A
0.130 MAX.
-A-
Q
0.050 ± 0.010
0.040 REF.
0.080 REF.
(2 Places)
A
L
0.130 ±0.010
0.100 REF.
(4 Places)
E
1.565 ± 0.025
-B-
PIN 1 I.D.
(Geometry Optional)
e
0.100
TYP.
TOP VIEW
-CA
(Base Plane)
b
0.018 ± 0.002
0.030 C A B
0.010 C 2
R
SIDE VIEW
P
N
M
L
K
J
D1/E1
1.400
H
G
F
E
D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW
0.003 MIN. TYP.
Notes:
1. True position applies to pins at base plane (datum C).
2. True position applies at pin tips.
3. All package finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
144-Pin Pingrid Array
Packaging-2
1
D/E
1.525 ± 0.015 SQ.
D1/E1
0.950 ± 0.015 SQ.
A
0.110
0.006
A
PIN 1 I.D.
(Geometry
Optional)
e
0.025
SEE DETAIL A
A
LEAD KOVAR
TOP VIEW
C
0.005 + 0.002
- 0.001
L
0.250
MIN.
REF.
S1
0.005 MIN. TYP.
SIDE VIEW
0.018 MAX. REF.
0.014 MAX. REF.
(At Braze Pads)
DETAIL A
BOTTOM VIEW A-A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
132-Lead Flatpack (25-MIL Lead Spacing)
Packaging-3
A
0.115 MAX.
D/E
1.150 ± 0.015 SQ.
A1
0.080 ± 0.008
A
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
SIDE VIEW
L/L1
0.050 ± 0.005 TYP.
h
0.040 x 45_
REF. (3 Places)
B1
0.025 ± 0.003
e
0.050
J
0.020 X 455 REF.
e1
0.015 MIN.
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW A-A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
84-LCC
Packaging-4
A
D/E
1.810 ± 0.015 SQ.
D1/E1
1.150 ± 0.012 SQ.
A
0.110
0.060
PIN 1 I.D.
(Geometry
Optional)
A
e
0.050
b
0.016 ± 0.002
SEE DETAIL A
A
LEAD KOVAR
C
0.007 ± 0.001
TOP VIEW
L
0.260
MIN.
REF.
S1
0.005 MIN. TYP.
SIDE VIEW
0.018 MAX. REF.
0.014 MAX.
REF.
(At Braze Pads)
BOTTOM VIEW A-A
DETAIL A
Notes:
1. All package finishes are per MIL-M-38510.
2. Letter designations are for cross-reference to MIL-M-38510.
84-Lead Flatpack (50-MIL Lead Spacing)
Packaging-5
D
1.100 ± 0.020
A
0.130 MAX.
-A-
Q
0.050 ± 0.010
A
L
0.130 ± 0.010
E
1.100 ± 0.020
PIN 1 I.D.
(Geometry Optional)
-B-
-C(Base Plane)
TOP VIEW
e
0.100
TYP.
0.030 C A B
0.010 C 2
SIDE VIEW
L
K
J
H
G
D1/
1.000
F
E
D
1
A
b
0.018 ± 0.002
2
3
4
5
6
7
8 9 10 11
PIN 1 I.D.
(Geometry Optional)
BOTTOM VIEW A-A
0.003 MIN.
Notes:
1. True position applies to pins at base plane (datum C).
2. True position applies at pin tips.
3. All packages finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
84-Pin Pingrid Array
Packaging-6
1
D
1.100 ± 0.020
A
0.130 MAX.
Q
0.050 ± 0.010
-A-
A
L
0.130 ± 0.010
E
1.100 ± 0.020
-B-
PIN 1 I.D.
(Geometry Optional)
A
-C(Base Plane)
TOP
b
0.010 ± 0.002
∅ 0.030 C A B
∅ 0.010 C 2
e
0.100
TYP.
1
SIDE VIEW
L
K
J
H
G
F
E
D
C
B
A
D1/E1
1.00
1 2 3 4 5 6
PIN 1 I.D.
(Geometry Optional)
7
8
9
10 11
0.003 MIN. TYP.
BOTTOM VIEW A-A
Notes:
1 True position applies to pins at base plane (datum C).
2 True position applies at pin tips.
3. All packages finishes are per MIL-M-38510.
4. Letter designations are for cross-reference to MIL-M-38510.
68-Pin Pingrid Array
Packaging-7
E
0.750 ± 0.015
L
0.490
MIN.
b
0.015 ± 0.002
D
1.800 ± 0.025
e
0.10
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
c
0.008
+ 0.002
- 0.001
A
0.130 MAX.
END VIEW
Notes:
1 All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589 or
equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
36-Lead Flatpack, Dual Cavity (100-MIL Lead Spacing)
Packaging-8
Q
0.080 ± 0.010
(At Ceramic Body)
E
0.700 + 0.015
L
0.330
MIN.
b
0.016 + 0.002
D
1.000 ± 0.025
e
0.050
PIN 1 I.D
(Geometry Optional)
TOP
+ 0.002
c
0.007 - 0.001
A
0.100 MAX.
END
Q
0.070 + 0.010
(At Ceramic Body)
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589
or equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
36-Lead Flatpack, Dual Cavity (50-MIL Lead Spacing)
Packaging-9
E
0.590 ± 0.012
S1
0.005 MIN.
S2
0.005 MAX.
e
0.100
D
1.800 ± 0.025
b
0.018 ± 0.002
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
C
0.010 +- 0.002
0.001
E1
0.600 + 0.010
(At Seating Plane)
A
0.155 MAX.
L/L1
0.150 MIN.
SIDE VIEW
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589
or equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
END VIEW
36-Lead Side-Brazed DIP, Dual Cavity
Packaging-10
E
0.590 ± 0.015
S1
0.005 MIN.
S2
0.005 MAX.
e
0.100
D
1.200 ± 0.025
b
0.018 ± 0.002
PIN 1 I.D.
(Geometry Optional)
TOP VIEW
+ 0.002
C
0.010 - 0.001
E1
0.600 + 0.010
(At Seating Plane)
L/L1
0.150 MIN.
A
0.140 MAX.
SIDE VIEW
Notes:
1. All package finishes are per MIL-M-38510.
2. It is recommended that package ceramic be mounted to
a heat removal rail located on the printed circuit board.
A thermally conductive material such as MERECO XLN-589 or
equivalent should be used.
3. Letter designations are for cross-reference to MIL-M-38510.
END VIEW
24-Lead Side-Brazed DIP, Single Cavity
Packaging-11
ORDERING INFORMATION
UT1553B RTI Remote Terminal Interface:
5962
*
*
*
*
*
*
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Case Outline:
(Z) = 84 pin PGA
Class Designator:
(B) = Jan Class Q
Device Type
01 = 10% to 35% Clock Duty Cycle
Drawing Number: JM38510/555
Total Dose:
(-) = None
Federal Stock Class Designator: No options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
UT1553B RTI Remote Terminal Interface
UT1553B -
*
*
*
*
Lead Finish:
(A) = Solder
(C) = Gold
(X) = Optional
Screening:
(C) = Military Temperature
(P) = Prototype
Package Type:
(G) = 84 pin PGA
Modifier:
RTI = 10% to 35% Clock Duty Cycle
UTMC Core Part Number
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. Mil Temp range flow per UTMC’s manufacturing flows document. Devices are tested at -55°C, room temperature, and 125°C.
4. Prototpe flow per UTMC’s document manufacturing flows and are tested at 25°C only. Lead finish is GOLD only.
5. Prototypes and reduced high-reliability devices are only available with 40% to 60% clock duty cycle.