VISHAY SI2343CDS

SPICE Device Model Si2343CDS
Vishay Siliconix
P-Channel 30 V (D-S) MOSFET
DESCRIPTION
CHARACTERISTICS
The attached SPICE model describes the typical electrical
characteristics of the p-channel vertical DMOS. The
subcircuit model is extracted and optimized over the - 55 °C
to + 125 °C temperature ranges under the pulsed 0 V to 10 V
gate drive. The saturated output impedance is best fit at the
gate bias near the threshold voltage. A novel gate-to-drain
feedback capacitance network is used to model the gate
charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter
values are optimized to provide a best fit to the measured
electrical data and are not intended as an exact physical
interpretation of the device.
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the - 55 °C to + 125 °C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
SUBCIRCUIT MODEL SCHEMATIC
D
CGD
R1
3
M2
Gy
G
RG
+ –
ETCV
Gx
CGS
DBD
M1
S
Note
This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to
the appropriate datasheet of the same number for guaranteed specification limits.
Document Number: 66545
S10-0753-Rev. A, 05-Apr-10
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SPICE Device Model Si2343CDS
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
SIMULATED MEASURED
DATA
DATA
UNIT
Static
Gate-Source Threshold Voltage
Drain-Source On-State Resistancea
VGS(th)
RDS(on)
VDS = VGS, ID = - 250 μA
1.9
-
VGS = - 10 V, ID = - 4.2 A
0.040
0.037
VGS = - 4.5 V, ID = - 3.2 A
0.061
0.062
V

Forward Transconductancea
gfs
VDS = - 15 V, ID = - 4.2 A
9
10
S
Diode Forward Voltage
VSD
IS = - 3.3 A
- 0.85
- 0.80
V
585
590
114
115
87
93
13
13.6
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = - 15 V, VGS = 0 V, f = 1 MHz
VDS = - 15 V, VGS = - 10 V, ID = - 4.2 A
VDS = - 15 V, VGS = - 4.5 V, ID = - 4.2 A
6.4
7
2.3
2.3
3.2
3.2
pF
nC
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
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Document Number: 66545
S10-0753-Rev. A, 05-Apr-10
SPICE Device Model Si2343CDS
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA TJ = 25 °C, unless otherwise noted
25
3.0
TJ = 125 °C
2.4
VGS = 10 V, 7 V, 6 V, 5 V
ID - Drain Current (A)
ID - Drain Current (A)
20
15
VGS = 4 V
10
5
1.8
TJ = 25 °C
1.2
0.6
VGS = 3 V
TJ = - 55 °C
0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0
3.0
1
0.10
1000
0.08
800
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
2
3
4
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
0.06
VGS = 4.5 V
0.04
VGS = 10 V
Ciss
600
400
200
0.02
Coss
Crss
0
0.00
0
5
10
15
20
25
0
ID - Drain Current (A)
5
10
15
20
25
30
VDS - Drain-to-Source Voltage (V)
100
10
8
VDS = 15 V
IS - Source Current (A)
VGS - Gate-to-Source Voltage (V)
ID = 4.2 A
6
VDS = 24 V
4
TJ = 150 °C
10
TJ = 25 °C
1
2
0.1
0
0
3
6
9
Qg - Total Gate Charge (nC)
12
15
0
0.3
0.6
0.9
1.2
1.5
VSD - Source-to-Drain Voltage (V)
Note
Dots and squares represent measured data.
Document Number: 66545
S10-0753-Rev. A, 05-Apr-10
www.vishay.com
3
SPICE Device Model Si2343CDS
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA TJ = 25 °C, unless otherwise noted
1.7
0.10
ID = 4.2 A
ID = 4.2 A
RDS(on) - On-Resistance (Ω)
RDS(on) - On-Resistance
Normalized
1.5
1.3
1.1
VGS = 4.5 V, 2.5 V
0.08
TJ = 125 °C
0.06
0.04
0.9
0.7
- 50
TJ = 25 °C
0.02
- 25
0
25
50
75
100
TJ - Junction Temperature (°C)
125
150
2
4
6
8
10
VGS - Gate-to-Source Voltage (V)
Note
Dots and squares represent measured data.
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Document Number: 66545
S10-0753-Rev. A, 05-Apr-10
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Document Number: 91000
Revision: 18-Jul-08
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