Melexis EVB71120-315-ASK-C 300 to 930mhz receiver evaluation board description Datasheet

EVB71120
300 to 930MHz Receiver
Evaluation Board Description
Features
!
!
!
!
!
!
!
!
!
!
!
!
!
!
Dual RF input for antenna space and frequency diversity, LNA cascading or differential feeding
Fully integrated PLL-based synthesizer
2nd mixer with image rejection
Reception of ASK or FSK modulated signals
Wide operating voltage and temperature ranges
Very low standby current consumption
Low operating current consumption
External IF filters 455kHz or 10.7MHz
Internal FSK demodulator
Average or peak detection data slicer mode
RSSI output with high dynamic range for RF level indication
Output noise cancellation filter
MCU clock output
High over-all frequency accuracy
Ordering Information
Part No. (see paragraph 4)
EVB71120-315-C
EVB71120-433-C
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EVB71120-868-C
EVB71120-915-C
Note 1: Peak detection mode, IF2 selection = 10.7MHz is default population.
Application Examples
! General digital and analog RF receivers
at 300 to 930MHz
! Tire pressure monitoring systems (TPMS)
! Remote keyless entry (RKE)
! Low power telemetry systems
! Alarm and security systems
! Active RFID tags
! Remote controls
! Garage door openers
! Home and building automation
General Description
The MLX71120 is a multi-band, single-channel RF receiver based on a double-conversion super-heterodyne
architecture. It can receive FSK and ASK modulated signals. The IC is designed for general purpose
applications for example in the European bands at 433MHz and 868MHz or for similar applications in North
America or Asia, e.g. at 315MHz or 915MHz. It is also well-suited for narrow-band applications according to
the ARIB STD-T67 standard in the frequency range 426MHz to 470MHz.
The receiver’s extended temperature and supply voltage ranges make the device a perfect fit for automotive
or similar applications where harsh environmental conditions are expected.
39012 71120 01
Rev. 003
Page 1 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
Document Content
1
2
3
Theory of Operation ...................................................................................................3
1.1
General............................................................................................................................. 3
1.2
Technical Data Overview.................................................................................................. 3
1.3
Block Diagram .................................................................................................................. 4
1.4
Operating Modes .............................................................................................................. 5
1.5
Frequency Range ............................................................................................................. 5
1.6
LNA Selection................................................................................................................... 5
1.7
External IF2 Selection ...................................................................................................... 5
1.8
Demodulation Selection.................................................................................................... 5
1.9
Data Slicer ........................................................................................................................ 5
Frequency Planning ...................................................................................................6
2.1
Calculation of Frequency Settings.................................................................................... 7
2.2
Standard Frequency Plans ............................................................................................... 8
2.3
433/868MHz Frequency Diversity .................................................................................... 8
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Dual-Channel Application Circuits for FSK & ASK Reception ...............................9
3.1
3.1.1
3.1.2
3.2
3.2.1
Peak Detector Data Slicer ................................................................................................ 9
Component Arrangement Top Side (Peak Detection Data Slicer, IF2 = 10.7MHz) .................. 10
Component Arrangement Top Side (Peak Detection Data Slicer, IF2 = 455kHz) .................... 11
Averaging Data Slicer Configured for-Bi Phase Codes .................................................. 12
Component Arrangement Top Side (Averaging Data Slicer, IF2 = 10.7MHz) .......................... 13
3.3
Component List for Dual-Channel Application................................................................ 14
3.4
PCB Layouts for Antenna Space Diversity ..................................................................... 15
4
Board Variants..........................................................................................................15
5
Package Description ................................................................................................16
5.1
Soldering Information ..................................................................................................... 16
6
Reliability Information .............................................................................................17
7
ESD Precautions ......................................................................................................17
8
Disclaimer .................................................................................................................18
39012 71120 01
Rev. 003
Page 2 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
1
Theory of Operation
1.1
General
The MLX71120 receiver architecture is based on a double-conversion super-heterodyne approach. The two
LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency
is derived from a crystal (XTAL). As the first intermediate frequency (IF1) is very high, a reasonably high
degree of image rejection is provided even without using an RF front-end filter. At applications asking for
very high image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front
of the LNA. The second mixer MIX2 is an image-reject mixer.
The receiver signal chain is setup by one (or two) low noise amplifier(s) (LNA1, LNA2), two down-conversion
mixers (MIX1, MIX2) and an external IF filter with an on-chip amplifier (IFA). By choosing the required
modulation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or
the RSSI-based ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the
demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by
means of the positive and negative peak detectors (PKDET+/-). A digital post-processing of the sliced data
signal can be performed by a noise filter (NF) building block.
The dual LNA configuration can be used for antenna space diversity or antenna frequency diversity or to
setup an LNA cascade (to further improve the input sensitivity). The two LNAs can also be setup to feed the
RF signal differentially.
A sequencer circuit (SEQ) controls the timing during start-up. This is to reduce start-up time and to minimize
power dissipation.
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A clock output, which is a divide-by-8 version of the crystal oscillator signal, can be used to drive a
microcontroller. The clock output is open drain and gets activated through a load connected to positive
supply.
1.2
Technical Data Overview
! Input frequency ranges: 300 to 470MHz
610 to 930MHz
! Power supply range: 2.1 to 5.5V
! Temperature range: -40 to +125°C
! Shutdown current: 50 nA
! Operating current: 6.5 to 8.1mA
! Selectable IF2 frequency: 10.7MHz or 455kHz
! FSK deviation range: ±10kHz to ±100kHz (WB)
±2kHz to ±10kHz (NB)
! Image rejection:
65dB 1st IF (with external RF front-end filter)
25dB 2nd IF (internal image rejection)
! Maximum data rate: 50kps RZ (bi-phase) code,
100kps NRZ
! Spurious emission: < -54dBm
! Linear RSSI range: > 70dB
! Crystal reference frequency: 16 to 27MHz
! MCU clock frequency: 2.0 to 3.4
! Input Sensitivity: at 4kbps NRZ, BER = 3·10-3
Frequency
FSK
ASK
Note:
315 MHz
433 MHz
868 MHz
915 MHz
wide band 180kHz BW, IF2=10.7MHz
Δf = ±20kHz
-109dBm
-108dBm
-106dBm
-104dBm
narrow band 20kHz BW, IF2=455kHz
Δf = ±5kHz
-114dBm
-112dBm
-111dBm
-109dBm
wide band 180kHz BW, IF2=10.7MHz
-113dBm
-113dBm
-111dBm
-109dBm
- Sensitivities given for RF input 1 (without SAW filter)
- Sensitivity for RF input 2 is about 2 to 3dB worse (because of SAW filter loss)
39012 71120 01
Rev. 003
Page 3 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
24
14
2
LNA1
FSK
MIX1
MIX2
IFA
OA1
FSK
DEMOD
SEQ
VCO
31
TEST
BIAS
30
LF
OA2
DIV 8
CP
25
Fig. 1:
PDN
21
SW2
RO
ENRX
26
PKDET_
PFD
28
15
SLCSEL
RFSEL
N2
counter
CLKO
7
N1
counter
20
PDP
100k
LNA2
VEE
ROI
8
LO2
18
PKDET+
100k
32
LO1
DFO
SW1
100k
LNASEL
LNAI2
100k
NCF
DTAO
29
CINT
22
19
23
SLC
1
100k
16
ASK
VCC
LNAI1
17
DF2
27
DF1
13
RSSI
12
IFSEL
11
VEE
10
MIXO
9
VCC
5
MIXN
4
MODSEL
VEE
6
MIXP
3
LNAO2
Block Diagram
LNAO1
1.3
MLX71120 block diagram
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The MLX71120 receiver IC consists of the following building blocks:
•
•
•
•
•
•
•
•
•
•
•
•
PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2.
The PLL SYNTH consists of a fully integrated voltage-controlled oscillator (VCO), a distributed feedback
divider chain (N1, N2), a phase-frequency detector (PFD) a charge pump (CP), a loop filter (LF) and a
crystal-based reference oscillator (RO).
Two low-noise amplifiers (LNA) for high-sensitivity RF signal reception
First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)
Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF
IF amplifier (IFA) to provide a high voltage gain and an RSSI signal output
FSK demodulator (FSK DEMOD)
Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively
Positive (PKDET+) and negative (PKDET-) peak detectors
Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak
detection mode.
Noise cancellation filter (NF)
Sequencer circuit (SEQ) and biasing (BIAS) circuit
Clock output (DIV8)
39012 71120 01
Rev. 003
Page 4 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
1.4
Operating Modes
ENRX
Description
0
Shutdown mode
1
Receive mode
Note: ENRX is pulled down internally.
1.5
Frequency Range
Two different receive frequency ranges can be selected by the control signal RFSEL.
1.6
RFSEL
Description
0
Input frequency range 300 to 470MHz
1
Input frequency range 610 to 930MHz
LNA Selection
LNASEL
0
Hi-Z
Description
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LNA1 active, LNA2 shutdown
LNA1 and LNA2 active
1
LNA1 shutdown, LNA2 active
Note: Hi-Z state means pin LNASEL is left floating (pin is internally pulled to VCC/2 in this case).
1.7
External IF2 Selection
IFSEL
0
1
1.8
1.9
Description
IF2 = 455 kHz
IF2 = 10.7 MHz
Demodulation Selection
MODSEL
Description
0
ASK demodulation
1
FSK demodulation
Data Slicer
SLCSEL
Description
0
Averaging detection mode
1
Peak detection mode
39012 71120 01
Rev. 003
Page 5 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
2
Frequency Planning
Because of the double conversion architecture that employs two mixers and two IF signals, there are four
different combinations for injecting the LO1 and LO2 signals:
LO1 high side and LO2 high side:
LO1 high side and LO2 low side:
LO1 low side and LO2 high side:
LO1 low side and LO2 low side:
receiving at fRF(high-high)
receiving at fRF(high-low)
receiving at fRF(low-high)
receiving at fRF(low-low)
As a result, four different radio frequencies (RFs) could yield one and the same second IF (IF2). Fig. 2
shows this for the case of receiving at fRF(high-high). In the example of Fig. 2, the image signals at fRF(lowhigh) and fRF(low-low) are suppressed by the bandpass characteristic provided by the RF front-end. The
bandpass shape can be achieved either with a SAW filter (featuring just a couple of MHz bandwidth), or by
the tank circuits at the LNA input and output (this typically yields 30 to 60MHz bandwidth). In any case, the
high value of the first IF (IF1) helps to suppress the image signals at fRF(low-high) and fRF(low-low).
The two remaining signals at IF1 resulting from fRF(high-high) and fRF(high-low) are entering the second
mixer MIX2. This mixer features image rejection with so-called single-sideband (SSB) selection. This means
either the upper or lower sideband of IF1 can be selected. In the example of Fig. 2, LO2 high-side injection
has been chosen to select the IF2 signal resulting from fRF(high-high).
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f LO2
f RF
Fig. 2:
f RF
f LO2
f LO1
f RF
f RF
The four receiving frequencies in a double conversion superhet receiver
It can be seen from the block diagram of Fig. 1 that there is a fixed relationship between the LO signal
frequencies (fLO1 , fLO2) and the reference oscillator frequency fRO.
f LO1 = N 1 ⋅ f LO2
f LO2 = N 2 ⋅ f RO
The IF2 frequency can be selected to 455kHz or 10.7MHz via the logic level at the IFSEL control pin. At the
same time the output impedance of the 2nd mixer at pin MIXO is set according to the IF2 (please refer to pin
description for details). Of course, also the operating frequency of the FSK demodulator (FSK DEMOD) is
set accordingly.
39012 71120 01
Rev. 003
Page 6 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
2.1
Calculation of Frequency Settings
The receiver has two predefined receive frequency plans which can be selected by the RFSEL control pin.
Depending on the logic level of RFSEL pin the sideband selection of the second mixer and the counter
settings for N1 and N2 are changed accordingly. (see in 1.5)
RFSEL
Injection
fRFmin [MHz]
fRFmax [MHz]
N1
N2
0
high-low
300
470
4
6
1
low-high
610
930
2
12
The following table shows the relationships of several internal receiver frequencies for the two input
frequency ranges.
fRF [MHz]
fIF1
fLO1
fLO2
fRO
300 to 470
f RF + N 1f IF2
N1 − 1
N 1 (f RF + f IF2 )
N1 − 1
f RF + f IF2
N1 − 1
f RF + f IF2
N 2 (N 1 − 1)
610 to 930
f RF − N 1f IF2
N1 + 1
N 1 (f RF + f IF2 )
N1 + 1
f RF + f IF2
N1 + 1
f RF + f IF2
N 2 (N 1 + 1)
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Given IF2 is selectable at either 455kHz or 10.7MHz and the corresponding N1, N2 counter settings, above
equations can be transferred into the following table.
IF2=455kHz
fRF [MHz]
fIF1
fLO1
300 to 470
f RF + 1.82MHz
3
4(f RF + 0.455MHz )
3
610 to 930
f RF − 0.91MHz
3
2(f RF + 0.455MHz )
3
fRF [MHz]
fIF1
fLO1
300 to 470
f RF + 42.8MHz
3
4(f RF + 10.7MHz )
3
610 to 930
f RF − 21.4MHz
3
2(f RF + 10.7MHz )
3
IF2=10.7MHz
39012 71120 01
Rev. 003
Page 7 of 18
fLO2
f RF + 0.455MHz
3
fLO2
f RF + 10.7MHz
3
fRO
f RF + 0.455MHz
18
f RF + 0.455MHz
36
fRO
f RF + 10.7MHz
18
f RF + 10.7MHz
36
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
2.2
Standard Frequency Plans
IF2 = 455kHz
fRF [MHz]
fIF1 [MHz]
fLO1 [MHz]
fLO2 [MHz]
fRO [MHz]
315
105.6067
420.6067
105.1517
17.525277
433.92
145.2467
579.1667
144.7917
24.131944
868.3
289.1300
579.1700
289.5850
24.132083
915
304.6967
610.3033
305.1517
25.429305
fRF [MHz]
fIF1 [MHz]
fLO1 [MHz]
fLO2 [MHz]
fRO [MHz]
315
119.2667
434.2667
108.5667
18.094444
433.92
158.0667
592.8267
148.2067
24.701111
868.3
282.3000
586.0000
293.0000
24.416666
915
297.8667
617.1333
308.5667
25.713888
IF2 = 10.7MHz
2.3
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433/868MHz Frequency Diversity
The receiver’s multi-band functionality can be used to operate at two different frequency bands just by
changing the logic level at pin RFSEL and without changing the crystal. This feature is applicable for
common use of the 433 and 868MHz bands. Below table shows the corresponding frequency plans.
IF2 = 455kHz
RFSEL
fRF [MHz]
fIF1 [MHz]
fLO1 [MHz]
fLO2 [MHz]
0
433.9225
145.2483
579.17
144.7925
1
868.3
289.1300
579.17
289.5850
39012 71120 01
Rev. 003
Page 8 of 18
fRO [MHz]
24.132083
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
3
Dual-Channel Application Circuits for FSK & ASK Reception
3.1
Peak Detector Data Slicer
jumpers
LNA1 LNA2
ENRX
1 2 3
DTAO CLKO ROI RSSI
1 2 3
1 2
3 4
5 6
CRO
VCC
XTAL
10.7MHz
RCL
RFSEL
7 8
0 Ω jumper pads
455kHz
C4
C5
ROI 25
TEST 26
IFSEL 27
3 LNAO1
VCC 22
CP1
VEE
IFAP
IFAN
MODSEL
SLCSEL
DF2
DFO 18
10
11
12
13
14
15
16
DF1 17
CF2
CB0
CERFIL
39012 71120 01
Rev. 003
VCC
GND
DFO
5 6 7
CB1
VCC
CF1
SCLSEL
CIF
Fig. 3:
CB2
3 4
9
CP2
1 2
C8
SLC 19
MIXO
LNAI2
VCC
8
CF3
PDP 20
32L QFN 5x5
6 LNAO2
L4
PDN 21
MLX71120
7 VEE
1
3
SAWFIL
4
6
50
CINT 23
5 MIXN
C6
C7
2 VEE
4 MIXP
CB3
L3
CRS
RSSI 24
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L2
VCC
CLKO 28
1 LNAI1
DTAO 29
C3
ENRX 30
L1
RFSEL 31
50
32
CX
ASK
jumpers
FSK
Circuit schematic
Page 9 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
3.1.1
Component Arrangement Top Side (Peak Detection Data Slicer, IF2 = 10.7MHz)
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Fig. 4:
39012 71120 01
Rev. 003
PCB top-side view
Page 10 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
3.1.2
Component Arrangement Top Side (Peak Detection Data Slicer, IF2 = 455kHz)
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Fig. 5:
39012 71120 01
Rev. 003
PCB top-side view
Page 11 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
3.2
Averaging Data Slicer Configured for Bi-Phase Codes
jumpers
LNA1 LNA2
DTAO CLKO ROI RSSI
ENRX
1 2 3
1 2 3
1 2
3 4
5 6
CRO
VCC
XTAL
10.7MHz
RCL
RFSEL
7 8
0 Ω jumper pads
455kHz
C4
C5
ROI 25
TEST 26
IFSEL 27
VCC 22
VEE
IFAP
IFAN
MODSEL
SLCSEL
DF2
DFO 18
10
11
12
13
14
15
16
DF1 17
CF1
SCLSEL
CIF
CF2
CERFIL
39012 71120 01
Rev. 003
CB0
VCC
GND
DFO
5 6 7
CB1
Fig. 6:
VCC
3 4
9
CSL
1 2
C8
CB2
SLC 19
MIXO
8
LNAI2
VCC
L4
PDP 20
32L QFN 5x5
6 LNAO2
CF3
PDN 21
MLX71120
7 VEE
1
3
SAWFIL
4
6
50
CINT 23
5 MIXN
C6
C7
2 VEE
3 LNAO1
4 MIXP
CB3
L3
CRS
RSSI 24
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L2
VCC
CLKO 28
1 LNAI1
DTAO 29
C3
ENRX 30
L1
RFSEL 31
50
32
CX
ASK
jumpers
FSK
Circuit schematic
Page 12 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
3.2.1
Component Arrangement Top Side (Averaging Data Slicer, IF2 = 10.7MHz)
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Fig. 7:
39012 71120 01
Rev. 003
PCB top-side view
Page 13 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
3.3
Component List for Dual-Channel Application
Below table is valid for test circuits shown in Figures 3.1 to 3.2.
Part
Size
Value @
315 MHz
Value @
Value @
433.92 MHz 868.3 MHz
Value @
915 MHz
Tol.
C3
0603
100 pF
100 pF
C4
0603
4.7 pF
3.9 pF
100 pF
100 pF
±5%
LNA input filtering capacitor
2.2 pF
1.5 pF
±5%
C5
0603
100 pF
LNA output tank capacitor
100 pF
100 pF
100 pF
±5%
C6
0603
MIX1 positive input matching capacitor
100 pF
100 pF
100 pF
100 pF
±5%
C7
0603
MIX1 negative input matching capacitor
NIP
NIP
3.9 pF
NIP
±5%
matching capacitor
±5%
matching capacitor
Description
C8
0603
NIP
NIP
1.0 pF
NIP
CB0
0805
33 nF
33 nF
33 nF
33 nF
±10% decoupling capacitor
CB1
0603
330 pF
330 pF
330 pF
330 pF
±10% decoupling capacitor
CB2
0603
330 pF
330 pF
330 pF
330 pF
±10% decoupling capacitor
CB3
0603
330 pF
330 pF
330 pF
330 pF
±10% decoupling capacitor
CF1
0603
680 pF
680 pF
680 pF
680 pF
±10%
data low-pass filter capacitor,
for data rate of 4 kbps NRZ
CF2
0603
330 pF
330 pF
330 pF
330 pF
±10%
data low-pass filter capacitor,
for data rate of 4 kbps NRZ
CF3
0603
±10%
optional capacitor for noise cancellation
filter
CIF
0603
1 nF
1 nF
1 nF
1 nF
±10% IFA feedback capacitor
CP1
0603
33 nF
33 nF
33 nF
33 nF
±10%
positive PKDET capacitor,
for data rate of 4 kbps NRZ
CP2
0603
33 nF
33 nF
33 nF
33 nF
±10%
negative PKDET capacitor,
for data rate of 4 kbps NRZ
CRS
0603
1 nF
1 nF
1 nF
1 nF
±10%
RSSI output low pass capacitor,
for data rate of 4 kbps NRZ
CRO
0603
1 nF
1 nF
1 nF
1 nF
±5%
optional capacitor,
to couple external RO signal
CSL
0603
100 nF
100 nF
100 nF
±10%
data slicer capacitor,
for data rate of 4 kbps NRZ
CX
0603
27 pF
27 pF
27 pF
27 pF
±5%
crystal series capacitor
L1
0603
56 nH
27 nH
0Ω
0Ω
±5%
matching inductor
L2
0603
27 nH
15 nH
3.9 nH
3.9 nH
±5%
LNA output tank inductor
L3
0603
0Ω
68 nH
22 nH
0Ω
±5%
matching inductor
L4
0603
56 nH
82 nH
22 nH
0Ω
±5%
matching inductor
±5%
optional CLK output resistor,
to clock output signal generated
value according to the data rate
connected to ground if noise filter not used
Y
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A
N
I
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P
100 nF
for averaging detection mode only
RCL
0603
3.3 kΩ
3.3 kΩ
3.3 kΩ
3.3 kΩ
SAW
FIL
SMD
3x3
SAFDC315M
SM0T00
(315 MHz)
SAFCC433M
BL0X00
(433.92 MHz)
SAFCC868M
SL0X00
(868.3 MHz)
SAFCC915M
AL0N00
(915 MHz)
CER
FIL
SMD
3.45x3.1
SFECF10M7HA00
B3dB = 180 kHz
SMD
6.5x6.0
CFUKG455KD4A
B6dB = 20 kHz
18.094444
MHz
XTAL
SMD
5x3.2
17.525278
MHz
24.701111
MHz
low-loss SAW filter from Murata
or equivalent part
IF2=10.7MHz ceramic filter
from Murata,
or equivalent part
IF2=455kHz
24.416667
MHz
24.132083
MHz
25.713889
MHz
25.429306
MHz
IF2=10.7MHz fundamental-mode
crystal from Telcona,
IF2=455kHz or equivalent part
±20ppm cal., ±30ppm temp.
Note:
NIP – not in place, may be used optionally
39012 71120 01
Rev. 003
Page 14 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
PCB Layouts for Antenna Space Diversity
FSK
MOD
SEL
ASK
GND
DFO
Board layout data in Gerber format is available, board size is 40mm x 44.5mm.
GND
•
VCC
3.4
Melexis
GND
RSSI
GND
ROI
GND
CLKO
GND
DTAO
VCC
ENRX
LNA2
RFI1
RFI2
GND
LNA
SEL
LNA1
PCB bottom view
PCB top view
4
Y
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Board Variants
Type
EVB71120
Frequency/MHz
Modulation
Board Execution
–315
–FSK
according to section 3.1 / 3.2
–A
antenna version
–433
–ASK
according to section 3.1 / 3.2
–C
connector version
–868
–FM
–915
Note:
39012 71120 01
Rev. 003
available EVB setups
Page 15 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
5
Package Description
The device MLX71120 is RoHS compliant.
D
A3
24
17
25
16
32
9
E
A1
8
b
1
e
A
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exp osed pad
E2
L
D2
The “exposed pad” is not connected to internal ground,
it should not be connected to the PCB.
Fig. 8:
32L QFN 5x5 Quad
all Dimension in mm
min
max
D
E
D2
E2
A
A1
A3
L
e
b
4.75
5.25
4.75
5.25
3.00
3.25
3.00
3.25
0.80
1.00
0
0.05
0.20
0.3
0.5
0.50
0.18
0.30
0.118
0.128
0.118
0.128
0.0315
0.0393
0
0.002
0.0079
0.0118
0.0197
0.0197
0.0071
0.0118
all Dimension in inch
min
max
5.1
0.187
0.207
0.187
0.207
Soldering Information
•
The device MLX71120 is qualified for MSL3 with soldering peak temperature 260 deg C
according to JEDEC J-STD-20
39012 71120 01
Rev. 003
Page 16 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
6
Reliability Information
This Melexis device is classified and qualified regarding soldering technology, solderability and moisture
sensitivity level, as defined in this specification, according to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)
•
•
IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices
(classification reflow profiles according to table 5-2)”
EIA/JEDEC JESD22-A113
“Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles
according to table 2)”
Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
•
•
EN60749-20
“Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat”
EIA/JEDEC JESD22-B106 and EN60749-15
“Resistance to soldering temperature for through-hole mounted devices”
Iron Soldering THD’s (Through Hole Devices)
•
Y
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EN60749-15
“Resistance to soldering temperature for through-hole mounted devices”
Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
•
EIA/JEDEC JESD22-B102 and EN60749-21
“Solderability”
For all soldering technologies deviating from above mentioned standard conditions (regarding peak
temperature, temperature gradient, temperature profile etc) additional classification and qualification tests
have to be agreed upon with Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more
information on qualification of RoHS compliant products (RoHS = European directive on the Restriction Of
the Use of Certain Hazardous Substances) please visit the quality page on our website:
http://www.melexis.com/quality_leadfree.aspx
7
ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
39012 71120 01
Rev. 003
Page 17 of 18
EVB Description
Jan/08
EVB71120
300 to 930MHz Receiver
Evaluation Board Description
8
Disclaimer
1) The information included in this documentation is subject to Melexis intellectual and other property
rights. Reproduction of information is permissible only if the information will not be altered and is
accompanied by all associated conditions, limitations and notices.
2) Any use of the documentation without the prior written consent of Melexis other than the one set forth in
clause 1 is an unfair and deceptive business practice. Melexis is not responsible or liable for such
altered documentation.
3) The information furnished by Melexis in this documentation is provided ’as is’. Except as expressly
warranted in any other applicable license agreement, Melexis disclaims all warranties either express,
implied, statutory or otherwise including but not limited to the merchantability, fitness for a particular
purpose, title and non-infringement with regard to the content of this documentation.
4) Notwithstanding the fact that Melexis endeavors to take care of the concept and content of this
documentation, it may include technical or factual inaccuracies or typographical errors. Melexis
disclaims any responsibility in connection herewith.
5) Melexis reserves the right to change the documentation, the specifications and prices at any time and
without notice. Therefore, prior to designing this product into a system, it is necessary to check with
Melexis for current information.
Y
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6) Melexis shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special
incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the information in this documentation.
7) The product described in this documentation is intended for use in normal commercial applications.
Applications requiring operation beyond ranges specified in this documentation, unusual environmental
requirements, or high reliability applications, such as military, medical life-support or life-sustaining
equipment are specifically not recommended without additional processing by Melexis for each
application.
8) Any supply of products by Melexis will be governed by the Melexis Terms of Sale, published on
www.melexis.com.
© Melexis NV. All rights reserved.
For the latest version of this document, go to our website at:
www.melexis.com
Or for additional information contact Melexis Direct:
Europe, Africa:
Americas:
Asia:
Phone: +32 1367 0495
E-mail: [email protected]
Phone: +1 603 223 2362
E-mail: [email protected]
Phone: +32 1367 0495
E-mail: [email protected]
ISO/TS 16949 and ISO14001 Certified
39012 71120 01
Rev. 003
Page 18 of 18
EVB Description
Jan/08
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