TI1 CDCF2510 3.3-v phase-lock loop clock driver Datasheet

SCAS628D − APRIL 1999 − REVISED DECEMBER 2004
D Use CDCVF2510A as a Replacement for
D
D
D
D
D
D
D
D
D
D
D
D
D
PW PACKAGE
(TOP VIEW)
this Device
Designed to Meet PC133 SDRAM
Registered DIMM Specification Rev. 0.9
Spread Spectrum Clock Compatible
Operating Frequency 25 MHz to 140 MHz
Static Phase Error Distribution at 66 MHz
to 133 MHz is ±125 ps
Jitter (cyc−cyc) at 66 MHz to 133 MHz Is
|70| ps
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to One Bank of
10 Outputs
Output Enable Pin to Enable/Disable All 10
Outputs
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
G
FBOUT
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CLK
AVCC
VCC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
VCC
FBIN
description
The CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDCF2510 operates at a 3.3-V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50%, independent of the duty cycle at CLK. The outputs can be enabled/disabled with the control (G) input.
When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the
outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCF2510 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCF2510 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDCF2510 is characterized for operation from 0°C to 85°C.
For application information see the High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread
Spectrum Clocking (SSC) (literature number SCAA039) application reports.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&
*%$"# $ " #'&$$!"# '& "+& "&# &,!# #"%&"#
#"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*&
"&#"/ !)) '!!&"&#
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCAS628D − APRIL 1999 − REVISED DECEMBER 2004
FUNCTION TABLE
OUTPUTS
INPUTS
G
CLK
1Y
(0:9)
X
L
L
L
L
H
L
H
H
H
H
H
FBOUT
functional block diagram
G
11
3
4
5
8
9
15
16
CLK
24
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÁÁÁÁÁÁ
ÎÎÎÎÎÎÎ
ÁÁÁÁÁÁ
ÎÎÎÎÎÎÎ
17
PLL
FBIN
AVCC
13
20
21
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
1Y9
23
12
AVAILABLE OPTIONS
PACKAGE
2
1Y0
TA
SMALL OUTLINE
(PW)
0°C to 85°C
CDCF2510PWR
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
FBOUT
SCAS628D − APRIL 1999 − REVISED DECEMBER 2004
Terminal Functions
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
CLK
24
I
Clock input. CLK provides the clock signal to be distributed by the CDCF2510 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
FBIN
13
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally
zero phase error between CLK and FBIN.
G
11
I
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same
frequency as CLK.
FBOUT
12
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK.
When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an
integrated 25-Ω series-damping resistor.
1Y (0:9)
3, 4, 5, 8, 9,
15, 16, 17, 20,
21
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via the
G input. These outputs can be disabled to a logic-low state by deasserting the G control input. Each
output has an integrated 25-Ω series-damping resistor.
AVCC
23
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can
be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and
CLK is buffered directly to the device outputs.
AGND
1
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
GND
2, 10, 14, 22
Power
Power supply
6, 7, 18, 19
Ground
Ground
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCAS628D − APRIL 1999 − REVISED DECEMBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, AVCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVCC < VCC +0.7 V
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. AVCC must not exceed VCC.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
recommended operating conditions (see Note 5)
MIN
MAX
Supply voltage, VCC, AVCC
3
3.6
High-level input voltage, VIH
2
Low-level input voltage, VIL
0
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
0
V
V
0.8
Input voltage, VI
UNIT
V
VCC
−12
mA
V
12
mA
85
°C
NOTE 5: Unused inputs must be held high or low to prevent them from floating.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
fclk
Clock frequency
Input clock duty cycle
Stabilization time‡
MIN
MAX
UNIT
25
140
MHz
40%
60%
1
ms
‡ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCAS628D − APRIL 1999 − REVISED DECEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage
II = −18 mA
IOH = −100 µA
VOH
High-level output voltage
IOH = −12 mA
IOH = − 6 mA
VOL
IOH
Low-level output voltage
High-level output current
IOL = 100 µA
IOL = 12 mA
IOL = 6 mA
VCC−0.2
2.1
3V
2.4
VO = 3.135 V
VO = 1.95 V
3.465 V
Input current
VI = VCC or GND
VI = VCC or GND,
Outputs: low or high
V
0.8
V
0.55
−32
−36
−12
34
3.3 V
40
3.465 V
14
3.6 V
±5
µA
3.6 V
10
µA
3.3 V to 3.6 V
500
µA
IO = 0,
One input at VCC − 0.6 V,
Other inputs at VCC or GND
UNIT
−1.2
0.2
3.3 V
3.135 V
MAX
V
3V
3.135 V
II
Change in supply current
3V
VO = 1 V
VO = 1.65 V
VO = 1.65 V
VO = 0.4 V
∆ICC
MIN to MAX
TYP†
3V
Low-level output current
Supply current
MIN
MIN to MAX
IOL
ICC§
VCC, AVCC
3V
Ci
Input capacitance
VI = VCC or GND
3.3 V
Co
Output capacitance
VO = VCC or GND
3.3 V
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ For ICC of AVCC, and ICC vs Frequency (see Figures 8 and 9).
4
pF
6
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 25 pF (see Note 6 and Figures 1 and 2)§
PARAMETER
tsk(o)
FROM
(INPUT)
Phase error time − static (normalized)
(See Figures 3 − 6)
CLKIN↑ = 66 MHz to133 MHz
Output skew time¶
Any Y or FBOUT
TO
(OUTPUT)
FBIN↑
VCC, AVCC = 3.3 V
± 0.3 V
MIN
TYP
−125
Any Y or FBOUT
Phase error time − jitter (see Note 7)
Any Y or FBOUT
Clkin = 66 MHz to 100 MHz
−50
Any Y or FBOUT
UNIT
MAX
125
ps
200
ps
50
ps
|70|
Jitter(cycle-cycle)
(See Figure 7)
Clkin = 100 MHz to 133 MHz
Any Y or FBOUT
Duty cycle
F(clkin > 60 MHz)
Any Y or FBOUT
45%
55%
tr
Rise time (See Notes 8 and 9)
VO = 1.2 V to 1.8 V,
IBIS simulation
Any Y or FBOUT
2.5
1
V/ns
tf
Fall time (See Notes 8 and 9)
VO = 1.2 V to 1.8 V,
IBIS simulation
Any Y or FBOUT
2.5
1
V/ns
|65|
ps
§ These parameters are not production tested.
¶ The tsk(o) specification is only valid for equal loading of all outputs.
NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. Calculated per PC DRAM SPEC (tphase error, static − jitter(cycle-to-cycle)).
8. This is equivalent to 0.8 ns/2.5 ns and 0.8 ns/2.7 ns into standard 500 Ω/ 30 pf load for output swing of 04. V to 2 V.
9. 64 MB DIMM configuration according to PC SDRAM Registered DIMM Design Support Document, Figure 20 and Table 13.
Intel is a trademark of Intel Corporation.
PC SDRAM Register DIMM Design Support Document is published by Intel Corporation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SCAS628D − APRIL 1999 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
3V
Input
50% VCC
0V
tpd
From Output
Under Test
500 W
Output
25 pF
2V
0.4 V
tr
LOAD CIRCUIT FOR OUTPUTS
50% VCC
VOH
2V
0.4 V
VOL
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CLKIN
FBIN
tphase error
FBOUT
Any Y
tsk(o)
Any Y
Any Y
tsk(o)
Figure 2. Phase Error and Skew Calculations
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCAS628D − APRIL 1999 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LOAD CAPACITANCE
200
VCC = 3.3 V
fc = 133 MHz
C(LY) = 25 pF
TA = 25°C
See Notes A and B
10
100
0
0
Phase Error
−10
−100
−20
−200
−30
−300
Phase Error − ps
Phase Adjustment Slope − ps/pF
20
Phase Adjustment Slope
−40
−400
0
5
10
15
20
25
30
35
40
45
50
C(LF) − Load Capacitance − pF
NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω Phase error measured from CLK to Yn
B. C(LF) = Lumped feedback capacitance at FBIN
Figure 3
PHASE ERROR
vs
CLOCK FREQUENCY
PHASE ERROR
vs
SUPPLY VOLTAGE
0
0
VCC = 3.3 V
C(LY) = 25 pF
C(LF) = 12 pF
TA = 25°C
See Note A
−50
−150
−100
−150
Phase Error − ps
Phase Error − ps
−100
−200
−250
−300
−200
−250
−300
−350
−350
−400
−400
−450
−450
−500
fc = 133 MHz
C(LY) = 25 pF
C(LF) = 12 pF
TA = 25°C
See Note A
−50
50
60
70
80
90
100 110
120 130
140
−500
3
3.1
fc − Clock Frequency − MHz
3.2
3.3
3.4
3.5
3.6
VCC − Supply Voltage − V
Figure 5
Figure 4
NOTE A: Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SCAS628D − APRIL 1999 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
JITTER
vs
CLOCK FREQUENCY
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
300
0
VCC = 3.3 V
C(LY) = 25 pF
C(LF) = 12 pF
TA = 25°C
See Note A
−50
−150
250
200
Jitter − ps
Phase Error − ps
−100
VCC = 3.3 V
C(LY) = 25 pF
C(LF) = 12 pF
TA = 25°C
See Notes A and B
−200
−250
150
−300
Peak to Peak
100
−350
−400
50
Cycle to Cycle
−450
−500
50
60
70
80
90
100 110
120 130
0
50
140
60
70
80
Figure 6
NOTES: A.
B.
C.
D.
SUPPLY CURRENT
vs
CLOCK FREQUENCY
300
AVCC = VCC = 3.465 V
Bias = 0/3 V
C(LY) = 25 pF
C(LF) = 0
TA = 25°C
See Notes A and B
250
I CC − Supply Current − mA
AI CC − Analog Supply Current − mA
10
8
6
4
200
AVCC = VCC = 3.465 V
Bias = 0/3 V
C(LY) = 25 pF
C(LF) = 0
TA = 25°C
See Notes A and B
150
100
50
2
0
10
30
50
70
90
110
130
150
0
10
30
fc − Clock Frequency − MHz
50
70
Figure 8
Figure 9
POST OFFICE BOX 655303
90
110
fc − Clock Frequency − MHz
NOTES: A. C(LY) = Lumped capacitive load at Y
B. C(LF) = Lumped feedback capacitance at FBIN
8
120 130 140
Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω
Phase error measured from CLK to FBIN
C(LY) = Lumped capacitive load at Y
C(LF) = Lumped feedback capacitance at FBIN
16
12
100 110
Figure 7
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
14
90
fc − Clock Frequency − MHz
fc − Clock Frequency − MHz
• DALLAS, TEXAS 75265
130
150
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CDCF2510PW
NRND
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
CDCF2510
CDCF2510PWG4
NRND
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
CDCF2510
CDCF2510PWR
NRND
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
CDCF2510
CDCF2510PWRG4
NRND
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
CDCF2510
HPA00016PWR
NRND
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
CDCF2510
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CDCF2510PWR
Package Package Pins
Type Drawing
TSSOP
PW
24
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
6.95
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCF2510PWR
TSSOP
PW
24
2000
333.2
345.9
28.6
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated