March 2004 AS7C1025B ® 5V 128K X 8 CMOS SRAM (Center power and ground) Features • JEDEC-standard packages - 32-pin, 300 mil SOJ - 32-pin, 400 mil SOJ • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA • Industrial and commercial temperatures • Organization: 131,072 x 8 bits • High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time • Low power consumption: ACTIVE - 605mW / max @ 10 ns • Low power consumption: STANDBY - 55 mW / max CMOS • 6 T 0.18 u CMOS technology • Easy memory expansion with CE, OE inputs • Center power and ground • TTL/LVTTL-compatible, three-state I/O Pin arrangement Logic block diagram VCC A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 GND 512 x 256 x 8 Array (1,048,576) I/O7 Sense amp A0 A1 A2 A3 A4 A5 A6 A7 A8 Row decoder Input buffer I/O0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 WE OE CE Control circuit A9 A10 A11 A12 A13 A14 A15 A16 Column decoder 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C1025B 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns Maximum operating current 110 100 90 80 mA Maximum CMOS standby current 10 10 10 10 mA 3/26/04, v. 1.3 Alliance Semiconductor P. 1 of 9 Copyright © Alliance Semiconductor. All rights reserved. AS7C1025B ® Functional description The AS7C1025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 x 8 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for highperformance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1025B is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on VCC relative to GND Vt1 –0.50 +7.0 V Voltage on any pin relative to GND Vt2 –0.50 VCC + 0.5 V Power dissipation PD – 1.0 Storage temperature (plastic) Tstg –65 W +150 o C Ambient temperature with VCC applied Tbias –55 +125 oC DC current into outputs (low) IOUT – 20 mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (ISB, ISB1) L H H High Z Output disable (ICC) L H L DOUT Read (ICC) L L X DIN Write (ICC) Key: X = don’t care, L = low, H = high. 3/26/04, v. 1.3 Alliance Semiconductor P. 2 of 9 AS7C1025B ® Recommended operating conditions Parameter Symbol Min Nominal Max Unit VCC 4.5 5.0 5.5 V VIH 2.2 – VCC + 0.5 V VIL –0.5 – 0.8 Supply voltage Input voltage commercial Ambient operating temperature TA industrial 0 TA – –40 – V 70 o C 85 o C VIL min = -1.0V for pulse width less than 5ns VIH max = VCC+2.0V for pulse width less than 5ns. DC operating characteristics (over the operating range)1 -10 -15 -20 Parameter Symbol Input leakage current | ILI | VCC = Max, VIN = GND to VCC – 1 – 1 – 1 – 1 µA Output leakage current | ILO | VCC = Max, CE = VIH, Vout = GND to VCC – 1 – 1 – 1 – 1 µA – 110 – 100 – 90 – 80 mA – 50 – 45 – 45 – 40 mA – 10 10 mA 0.4 Operating power supply current ICC Standby power supply current1 ISB Test conditions -12 Min Max Min Max Min Max Min Max Unit VCC = Max CE ≤ VIL, f = fMax, IOUT = 0 mA VCC = Max CE ≥ VIH, f = fMax VCC = Max ISB1 Output voltage CE ≥ VCC–0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC –0.2 V, f=0 VOL IOL = 8 mA, VCC = Min – VOH IOH = –4 mA, VCC = Min 2.4 10 10 – 0.4 – 0.4 – 0.4 V 2.4 – 2.4 – 2.4 – V Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE VIN = 0 V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0 V 7 pF 3/26/04, v. 1.3 Alliance Semiconductor P. 3 of 9 AS7C1025B ® Read cycle (over the operating range)3,9 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Notes Read cycle time tRC 10 - 12 – 15 – 20 – ns Address access time tAA - 10 – 12 – 15 – 20 ns 3 Chip enable (CE) access time tACE - 10 – 12 – 15 – 20 ns 3 Output enable (OE) access time tOE - 5 – 6 – 7 – 8 ns Output hold from address change tOH 3 - 3 – 3 – 3 – ns 5 CE low to output in low Z tCLZ 3 - 3 – 3 – 3 – ns 4, 5 CE low to output in high Z tCHZ - 4 – 5 – 6 – 7 ns 4, 5 OE low to output in low Z tOLZ 0 - 0 – 0 – 0 – ns 4, 5 OE high to output in high Z tOHZ - 4 – 5 – 6 – 7 ns 4, 5 Power up time tPU 0 - 0 – 0 – 0 – ns 4, 5 Power down time tPD - 10 – 12 – 15 – 20 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address tAA tOH DOUT Data valid Read waveform 2 (CE and OE controlled)3,6,8,9 tRC1 CE tOE OE DOUT Supply current 3/26/04, v. 1.3 tOHZ tCHZ tOLZ tACE tCLZ tPU Data valid tPD 50% Alliance Semiconductor ICC ISB 50% P. 4 of 9 AS7C1025B ® Write cycle (over the operating range)11 -10 Parameter -12 -15 Min Max Min -20 Symbol Min Max Max Min Max Unit Notes Write cycle time tWC 10 - 12 – 15 – 20 – ns Chip enable (CE) to write end tCW 8 - 9 – 10 – 12 – ns Address setup to write end tAW 8 - 9 – 10 – 10 – ns Address setup time tAS 0 - 0 – 0 – 0 – ns Write pulse width tWP 7 - 8 – 9 – 12 – ns Write recovery time tWR 0 - 0 – 0 – 0 – ns Address hold from end of write tAH 0 - 0 – 0 – 0 – ns Data valid to write end tDW 5 - 6 – 8 – 10 – ns Data hold time tDH 0 - 0 – 0 – 0 – ns 4, 5 Write enable to output in high Z tWZ - 5 – 6 – 7 – 8 ns 4, 5 Output active from write end tOW 1 - 1 – 1 – 2 – ns 4, 5 Write waveform 1 (WE controlled)10,11 tWC tAW tWR tAH Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT 3/26/04, v. 1.3 Alliance Semiconductor P. 5 of 9 AS7C1025B ® Write waveform 2 (CE controlled)10,11 tAW tWC tAH tWR Address tAS tCW CE tWP WE tWZ tDW DIN tDH Data valid DOUT AC test conditions – – – – Output load: see Figure B. Input pulse level: GND to 3.5 V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5 V. +5 V Thevenin equivalent: 480 Ω +3.5 V GND 90% 10% DOUT 255 Ω 90% 2 ns 10% Figure A: Input pulse C13 DOUT 168 Ω +1.728 V GND Figure B: 5 V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. tCLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±500 mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 3/26/04, v. 1.3 Alliance Semiconductor P. 6 of 9 AS7C1025B ® Package dimensions 32-pin SOJ 300 mil/400 mil D e E1 E2 B Pin 1 A A1 c b A2 Seating plane 32-pin SOJ 300 mil 32-pin SOJ 400 mil Symbol Min Max Min Max A 0.128 0.145 0.132 0.146 A1 0.025 - 0.025 - A2 0.095 0.105 0.105 0.115 B 0.026 0.032 0.026 0.032 b 0.016 0.020 0.015 0.020 c 0.007 0.010 0.007 0.013 D 0.820 0.830 0.820 0.830 E 0.255 0.275 0.354 0.378 E1 0.295 0.305 0.395 0.405 E2 0.330 0.340 0.435 0.445 e 0.050 BSC 0.050 BSC E 3/26/04, v. 1.3 Alliance Semiconductor P. 7 of 9 AS7C1025B ® Ordering Codes Package \ Access time Temperature 300-mil SOJ Commercial Industrial 400-mil SOJ Commercial Industrial 10 ns 12 ns 15 ns 20 ns AS7C1025B-10TJC AS7C1025B-12TJC AS7C1025B-15TJC AS7C1025B-20TJC AS7C1025B-10TJI AS7C1025B-12TJI AS7C1025B-15TJI AS7C1025B-20TJI AS7C1025B-10JC AS7C1025B-12JC AS7C1025B-15JC AS7C1025B-20JC AS7C1025B-10JI AS7C1025B-12JI AS7C1025B-15JI AS7C1025B-20JI Note: Add suffix ‘N’ to the above part number for LEAD FREE parts. (Ex AS7C1025B-10TJCN) Part numbering system AS7C SRAM prefix 3/26/04, v. 1.3 1025B –XX Device number Access time X X X Package: TJ = SOJ 300 mil J = SOJ 400 mil Temperature range C = commercial, 0° C to 70° C I = industrial, -40° C to 85° C N = LEAD FREE PART Alliance Semiconductor P. 8 of 9 AS7C1025B ® ® Alliance Semiconductor Corporation Copyright © Alliance Semiconductor 2575, Augustine Drive, All Rights Reserved Santa Clara, CA 95054 Part Number: AS7C1025B Tel: 408 - 855 - 4900 Document Version: v. 1.3 Fax: 408 - 855 - 4999 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.