EMC EM83040BAQ Lcd controller Datasheet

EM83040B
LCD CONTROLLER
i n ar y
m
i
l
e
r
P
GENERAL DESCRIPTION
The EM83040B is a dot matrix LCD driver, which is fabricated by low power CMOS technology. This chip
includes 80-bits shift register, 80 bits data latch and 80 bits level driver. A LCD RAM inside can be mapping
to LCD signal. It converts RAM data to parallel data and output waveform to LCD.
FEATURES
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Supply power: 2.5~5.5V
LCD drive voltage: 3.6 to15V
Internal RAM: 2.5k x 4 bits
RAM can be controlled by eight signals including four bits data bus.
Duty: 1/32, 1/48, 1/64, 1/80
Build in DC/DC converter: double, triple, quad and five times.
Modularized function: connect to another 83040B to extent LCD matrix
One DC converter enabled and other 83040B can share with this.
Internal regulator output for DC/DC converter controlled by control register.
Chip form (EM83040BH), 128 pin package (14mm x 20mm EM83040BAQ), 160 pin package
(EM83040BBQ)
(11) Bias: 1/5 (32 COMMON), 1/7 (48 COMMON), 1/9 (64 and 80 COMMON) fixed by internal circuit.
(12) Internal RC clock about 250 KHz.
APPLICATION
(1)
(2)
(3)
Data Bank
LCD toy
Education computer
* This specification are subject to be changed without notice.
9.14.2001
1
EM83040B
LCD CONTROLLER
inary
m
i
l
e
r
P
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
EM83040BAQ
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
O53
O52
O51
NC
NC
NC
NC
NC
O50
O49
O48
O47
O46
O45
O44
O43
O42
O41
O40
O39
O38
O37
O36
O35
O34
O33
O32
O31
O30
NC
NC
NC
NC
NC
NC
O29
O28
O27
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
O16
O17
O18
O19
O20
O21
O22
O23
O24
O25
O26
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
MAIN
M1
M0
EN
NC
NC
NC
NC
RAMEN
RAMADS
RAMW
RAMR
RAMD3
RAMD2
RMAD1
RAMD0
LOAD
VDD
GND
VOUT
VSS4
VSS3
CB
CA
VSS2+
VSS2V1
V2
VREG
NC
NC
NC
NC
NC
V3
V4
V5
O0
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
O79
O78
O77
O76
O75
O74
O73
O72
O71
O70
O69
O68
O67
O66
O65
O64
O63
O62
O61
O60
O59
O58
O57
O56
O55
O54
EM83040BAQ
* This specification are subject to be changed without notice.
9.14.2001
2
EM83040B
LCD CONTROLLER
i n ar y
m
i
l
e
r
P
EM83040BBQ
VOUT
VSS4
VSS3
EM83040BBQ
+
-
VREG
* This specification are subject to be changed without notice.
9.14.2001
3
EM83040B
LCD CONTROLLER
inary
m
i
l
e
r
P
BLOCK DIAGRAM
VOUT
VSS4
VSS3
CA
CB
VSS2+
VSS2-
REG(5~0)
Regulator
VREG
M1,M0 IR(2~0)
Resistance
ratio
V1
Buffer1
Buffer2
Buffer3
Buffer4
Buffer5
* This specification are subject to be changed without notice.
MUX
:::::
BIAS
9.14.2001
4
EM83040B
LCD CONTROLLER
PIN DESCRIPTIONS
Symbol
I/O
VDD
GND
VOUT
Power
Power
Power
VSS4
Power
VSS3
Power
VSS2+
Power
VSS2VREG
Power
Power
MAIN
I
EN
I
M1
M0
RAMEN
I
I
RAMADS
RAMW
RAMR
RAMD3~RAM
D0
LOAD
CA
CB
V1~V5
O1~O80
i n ar y
m
i
l
e
r
P
I/O
I
I
I
O
Function
System power supply
Ground
Voltage converter input/output pin
Connect this pin to GND through capacitor
EN=1,VOUT=VDD
Step-up capacitor
EN=1, VSS4=VDD
Step-up capacitor
EN=1, VSS3=VDD
Step-up capacitor
EN=1, VSS2=VDD
Step-up capacitor
Output voltage regulator terminal. Provides the voltage between V1 and GND
through a resistive voltage divider.
Master or slave control signal.
MAIN=1, master unit
MAIN=0, slave unit
This pin control whole chip power. This chip will work when this pin is connected
to ground. And whole chip will disable when connect to VDD voltage.
EN=0 and MAIN=1 the chip will generate VSS2+, VSS2VSS3, VSS4, VOUT, LOAD signal and internal RC clock.
EN=1, standby mode
Mode select
Mode select
RAM read and write control signal.
1 => can not read and write. 0=> can read and write.
RAM data select signal
1=> RAM Data, 0=>Address
RAM write signal, low write
RAM read signal, low read
RAM data or address bus
LCD load signal between one COMMON signal to another.
MAIN=1, the master unit will output LOAD signal.
MAIN=0, the slave will accept the signal from master unit.
Coupling capacitor
Coupling capacitor
Reference voltage input, highest V1°K lowest V5
LCD waveform output
* This specification are subject to be changed without notice.
9.14.2001
5
EM83040B
LCD CONTROLLER
inary
m
i
l
e
r
P
FUNCTION DESCRIPTIONS
(1)User can use MAIN pin to chose master unit or slave unit.
MAIN
1
0
Unit
MASTER
SLAVE
Function
Generate these signals:
Load, CA, CB, VSS2+, VSS2-, VSS3, VSS4, VOUT
Internal RC clock
Accept these Master unit signals
Load, VOUT, V1, V2, V3, V4, V5
No internal RC clock
(2)User can use M1,M2 to choose four modes. As followed
MASTER
MAIN
M1
M0
Segment
Mode1
1
0
0
O(16:1)=S(16:1)
Mode2
1
0
1
Mode3
1
1
0
O(32:1)=S(32:1)
Mode4
1
1
1
O(48:1)=S(48:1)
SLAVE
MAIN
M1
M0
Segment
Mode1
0
0
0
O(80:1)=S(80:1)
Mode2
0
0
1
O(80:1)=S(80:1)
Mode3
0
1
0
O(80:1)=S(80:1)
Mode4
0
1
1
O(80:1)=S(80:1)
* S=Segment, C=Common
* (M1, M0) for Master must same as Slave unit
Common
O(80:17)=C(64:1)
O(80:1)=C(80:1)
O(80:33)=C(48:1)
O(80:49)=C(32:1)
Common
BIAS
1/9
1/9
1/7
1/5
BIAS
1/9
1/9
1/7
1/5
(3)RAM control
Write mode
FIG. 3
LCD RAM can be written or read with control signal. The RAMEN pin can select a RAM which can be read or
write. The RAMADS pin can select whether
* This specification are subject to be changed without notice.
9.14.2001
6
EM83040B
LCD CONTROLLER
i n ar y
m
i
l
e
r
P
RAMD(3:0) are data or address of RAM. At the address mode, RAMADS is low and user should sent address
three times, from address (11:8) to address (3:0). Then it will go into data mode when RAMADS is high. In data
mode, user can sent one or more nibble data which address can be increased by internal counter.
Once the RAMEN pin is high, the RAM can not read and write.
(4)Read control
Ten
RAM disable
RAM enable
RAMEN
ADDRESS
RAMADS
A3 A2
RAMD(3:0)
Tdd
DATA
A1
D1
D2
D3
Tdh
RAMW
Tdv
RAMR
A3=address (11:8)
A2=address(7:4)
A1=address(3:0)
FIG. 4
As same as write mode, user has to sent address three times. And read data from RAM one by one which address
can be increased by internal counter. Note!! Be sure to make RAMR low pulse 2uS (Tdv +data) width and 2uS
(Tdd) high width at least.
(5) RAM mapping
RAM address is from 0 to address 2562
User fill “1” to LCD RAM, LCD driver will generate “light” waveform. Otherwise, it will generate a “dark”
waveform. The LCD RAM area is mapped to segment 1 to segment 80 from address 0 to address 19. And user
can refer to fig.5 and Table 1 to get the idea of LCD ram mapping. The other RAM can use as general RAM for
data storage if not mapping to LCD display. And the RAM of address 2560, 2561 and 2562 is control registers.
Table 1: LCD mapping RAM area
Common
Segment
32
48
32
80
48
32
48
80
64
16
64
80
80
0
80
80
Any
Any
Master/slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Any
* This specification are subject to be changed without notice.
Display area
1,2,3
1,2,3,4
1,2,5,6
1,2,3,4,5,6,7
1,5,8
1,2,3,4,5,6,7,8,9
No mapping RAM
1,2,3,4,5,6,7,8,9,10
Area 11 is general RAM
9.14.2001
7
EM83040B
LCD CONTROLLER
inary
m
i
l
e
r
P
Address 2560,2561
2562 Control register
Address 2560,2561,2562
Control register
address2559 ...................
address2547 ......................................................................................................................... address2528
COM80
Area 11
address2047 ...................
:
:
:
:
address1535 ...................
:
address2035 ......................................................................................address2019...............address2016
Area 9
:
:
:
:
:
Area 7
:
Area 6
Area 5
:
address1011 .......................address1003 ............................................................................. address0992
Area 4
Area 3
:
Area 2
COM64
Area 8
address1523 ............................................................address1511........................................address1504
:
address1023 ...................
:
Area 10
LCD RAM
EMPTY AREA
COM48
COM32
Area 1
:
address0063 ...................
address0051 ................... ..................................... .......................... ................................... address0032
COM2
address0031 ...................
address0019 ................... address0011................ address7........... address0003............... address0000
COM1
b3 b2 b1 b0 ...................
s80s79s78s77
b3 b2 b1 b0
s48
s32
s16
s4 s3 s2 s1
Fig.5
As same as write mode , user has to sent address three times. And read data from RAM one by one which
address can be increased by internal counter. NOTE!! Be sure to make RAMR low pulse 2 µS (Tdv+data)
width and 2 µS (Tdd) high width at least.
(5) RAM mapping
RAM address is from 0 to address 2559
User fill “1” to LCD RAM , LCD driver will generate “light” waveform. Otherwise , it will generate a
“dark” waveform. The LCD RAM area is mapped to segment 1 to segment 80 from address 0 to address
19. And user can refer to fig.5 to get the idea of LCD ram mapping. The other RAM can use as general
RAM for data storage. And the RAM of address 2560 is a control register.
* This specification are subject to be changed without notice.
9.14.2001
8
EM83040B
LCD CONTROLLER
i n ar y
m
i
l
e
r
P
(6) LCD waveform
frame
V1
V2
V3
V4
V5
GND
com0
V1
V2
V3
V4
V5
GND
com1
V1
V2
V3
V4
V5
GND
com2
V1
V2
V3
V4
V5
GND
seg
dark
V1
V2
V3
V4
V5
GND
seg
light
Fig.6
* This specification are subject to be changed without notice.
9.14.2001
9
EM83040B
LCD CONTROLLER
inary
m
i
l
e
r
P
(7) Control register
Address
Bit3
Bit2
Bit1
Bit0
2560
IRS
IR2
IR1
IR0
2561
REG3
REG2
REG1
REG0
2562
PS1
PS0
REG5
REG4
X: don’t care
Default status of Address 2560,2561 and 2562, respectively: 0010, 0000, 0000
Address 2562 bit3~2(PS1, PS0) be selected:
Use settings
Only the internal power
supply is used
Only the V regulator
circuit and the V/F circuit
are used
Only the V/F circuit is
used
Only the external power
supply is used
PS1
PS0
Step-up
circuit
V
regulator
circuit
V/F
circuit
External
voltage input
1
1
Ο
O
O
X
1
0
X
O
O
VOUT
0
1
X
X
O
V1
0
0
X
X
X
V1 to V5
Address 2562 bit1~0 and 2561 bit3~0 (Reg5~Reg0) is selected the VEV value
REG5~REG0
000000
000001
↓
011111
100000
↓
111110
111111
VEV
1.2 V
1.212 V
↓
1.572 V
1.584 V
↓
1.944 V
1.956 V
VEV step
0.012V
VOUT
V1
Rb
V EV
VREG
Ra
Fig.7
* This specification are subject to be changed without notice.
9.14.2001
10
EM83040B
LCD CONTROLLER
i n ar y
m
i
l
e
r
P
Address 2560 bit3 (IRS) is internal resistor selected
IRS=0: internal regulator resistor is used.
IRS=1: internal regulator resistor is not used. (External resistor is used)
Address 2560 bit0~2(IR2, IR1, IR0) is selected for the V1 voltage regulator internal resistance ratio
IR2~IR0
Resistor ratio (1+Rb/Ra)
000
3.0
001
3.5
010
4.0
011
4.5
100
5.0
101
5.5
110
6.0
111
6.5
The V1 voltage can be calculated using equation A over the range where VDD < V1 ≤ VOUT
V1=(1+Rb/Ra) • VEV *(94%~97%) (Equation A)
(94%~97%) depend on loading
Example: Default: IRS=0 (internal regulator resistor is used), (IR2, IR1, IR0)=(0, 1, 0), and (REG5~0)=(000000)
V1=(1+Rb/Ra) • VEV*(94%~97%)=4.0 • 1.2*(94%~97%)= 4.51 V~4.65V
When IRS=0 (internal regulator resistor is used), (IR2, IR1, IR0)=(0, 1, 1), and (REG5~0)=(100000)
V1=(1+Rb/Ra) • VEV*(94%~97%)=4.5 • 1.584*(94%~97%)= 6.7~6.91 V
FIG. 8 show the V1 voltage measured by values of the internal resistance ratio resistor (1+Rb/Ra) for V1 voltage
adjustment and electric volume resister (REG5~REG0).
FIG. 8 The output voltage V1 is determined by function of the V1 voltage regulator ratio register (1+Rb/Ra), and
the electric volume resister (REG5~REG0).
(8) The step-up voltage circuit
Case of the double step-up, the triple step-up and Case of the quad step-up VOUT is output voltage pin the bias
voltage V1 is supported from VREG.
(a) Double step-up, (b) Triple step-up, (c) Quad step-up (d) five times step-up C1=0.47 to 1.0£gf, C2=1.0 to
4.7uf
VOUT
VSS4
VOUT
VOUT
VSS4
VSS4
VOUT
C2
VSS4
C2
C2
VSS2-
EM83040B
C2
VSS2-
VSS2+
CB
C2
C2
CA
CA
CA
EM83040B
EM83040B
CB
C2
CA
C2
C2
CB
C2
VSS2+
VREG
C2
VSS2+
C2
VSS2-
C2
VSS2+
C2
VSS2VREG
VREG
VREG
EM83040B
CB
VSS3
VSS3
VSS3
VSS3
C1
V1
V2
V3
V4
V5
(a) VOUT=2*VDD
V1
V2
V3
V4
V5
C1
(b) VOUT=3*VDD
* This specification are subject to be changed without notice.
V1
V2
V3
V4
V5
C1
(c) VOUT=4*VDD
FIG. 9
V1
V2
V3
V4
V5
C1
(d) VOUT=5*VDD
9.14.2001
11
EM83040B
LCD CONTROLLER
inary
m
i
l
e
r
P
(9) Reference circuit examples are as following FIG. 10
(a) Only the internal power supply is used, control register (PS1, PS0, IRS)=(1,1,0)
(b) Only the internal power supply is used, control register (PS1, PS0, IRS)=(1,1,1) When internal regulator
resistor is not used (external resistor is used), V1=VREG*(1+Rb’/Ra’)
(c) Only the V regulator circuit and the V/F circuit are used, control register (PS1, PS0, IRS)=(1,0,0)
(d) Only the V regulator circuit and the V/F circuit are used, control register (PS1, PS0, IRS)=(1,0,1),
When internal regulator resistor is not used (external resistor is used), V1=VREG*(1+Rb’/Ra’)
(e) Only the V/F circuit is used, control register (PS1, PS0)=(0,1)
(f) Only the external power supply is used, control register (PS1, PS0)=(0,0)
VOUT
VDD
MAIN
VOUT
VDD
MAIN
VSS4
VSS3
VSS4
C2
VSS3
C2
VSS3
C2
CB
CB
CB
C2
C2
CA
CA
VSS2+
C2
VSS2VREG
EM83040B
CA
EM83040B
MAIN
VSS4
C2
EXTERNAL
POWER
SUPPLY
VOUT
EM83040B
VDD
VSS2+
C2
VSS2Ra’
VREG
VSS2+
VSS2VREG
Rb’
V1
V2
V3
V4
V5
V1
V2
V3
V4
V5
V1
V2
V3
V4
V5
C1
(a)
(b)
EXTERNAL
POWER
SUPPLY
VOUT
(c)
VOUT
VDD
VOUT
VDD
VSS4
VSS4
VSS3
VSS3
VSS3
CB
CB
CA
CA
CA
CB
VSS2+
VSS2VREG
Ra’
VSS2+
VSS2-
EXTERNAL
POWER
SUPPLY
VREG
EM83040B
VSS4
EM83040B
EM83040B
VDD
C1
C1
VSS2+
VSS2VREG
Rb’
V1
V2
V3
V4
V5
V1
V2
V3
V4
V5
C1
(d)
V1
V2
V3
V4
V5
EXTERNAL
POWER
SUPPLY
C1
(e)
(f)
FIG. 10
* This specification are subject to be changed without notice.
9.14.2001
12
EM83040B
LCD CONTROLLER
i n ar y
m
i
l
e
r
P
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
DC SUPPLY VOLTAGE
INPUT VOLTAGE
OPERATING TEMPERATURE RANGE
STEP-UP VOLTAGE
Value
VDD
Vin
Ta
VOUT
Unit
<3.5
-0.5 TO Vdd ±0.5
-30 TO 80
<18
V
V
°C
V
DC ELECTRICAL CHARACTERISTICS (TA= -30°C ~ 80°C, VDD=3V±5%, VSS=0V)
Parameter
Input voltage
Output Low current
Standby current
Operating voltage
Current of a buffer (V1 toV5)
Voltage variation of regulator
Regulator current
BIAS resister
Sym. Min.
VDD
IOL
ISD
IOP
Typ.
Max.
2.5
5.5
2.5
2.5
5.5
4.0
2.5
-100
3.3
Ibuf
4
Vreg V-0.1
Ireg
R_bias 1800
Unit
Condition
With double step-up
V
1
180
4
220
µA
µA
µA
40
70
µA
6
10
V V+0.1
10
15
2000 2200
µA
V
µA
kΩ
With triple step-up
With quad step-up
With five times step-up
VDD=3V
EN=1
EN=0, MAIN =1(MASTER) , DC
converter enable, Five times step-up
(M1, M0)=(1,1) V1=11V, 250KHz
clock, No load
EN=0 . MAIN =0 (SLAVE) ,DC
converter enable, Five times step-up
(M1, M0)=(1,1) V1=11V, 250KHz
clock, No load
Current of a buffer
AC ELECTRICAL CHARACTERISTICS (TA= -30°C ~ 80°C, VDD=3V VSS=0V)
Parameter
Sym.
RC clock variable
Vrc
Frame period
Load period
Enable time
Write low pulse
Data hold time
Data to data time
Data valid time
Tframe
Tload
Ten
Tw
Tdh
Tdd
Tdv
* This specification are subject to be changed without notice.
Min.
Typ.
-20
1/64
31
30
2
500
2
1500
Max.
Unit
+20
%
S
µS
µS
µS
nS
µS
nS
9.14.2001
13
EM83040B
LCD CONTROLLER
inary
m
i
l
e
r
P
AC TIMING
LCD control timing
EN
Tframe
POSITIVE FRAME
FRAME
NEGATIVE FRAME
LOAD
C0 C1
S0
CM C0
Tload
S1
S2
S3
SN
Fig .11 LCD control timing
Ten
RAM disable
RAM enable
RAMEN
RAMADS
ADDRESS
RAMD(3:0)
A3
DATA
Tdd
A2
A1
D1
D2
D3
Tdh
RAMW
Tw
RAMR
A3=address(11:8)
A2=address(7:4)
A1=address(3:0)
Fig .12 LCD RAM write mode
* This specification are subject to be changed without notice.
9.14.2001
14
EM83040B
LCD CONTROLLER
i n ar y
m
i
l
e
r
P
Ten
RAM disable
RAM enable
RAMEN
RAMADS
ADDRESS
RAMD(3:0)
A3
A2
Tdd
DATA
A1
D1
D2
Tdv
RAMW
D3
Tdh
RAMR
A3=address (11:8) A2=address(7:0) A1=address(3:0)
D1= first nibble D2=second nibble D3=third nibble data
Fig .13 LCD RAM read mode
APPLICATION CIRCUIT
(1) C32 x S48
VDD
VDD
VDD
VDD
GND
MAIN
M1
M0
EN
RAMEN
RAMADS
RAMW
RAMR
RAMD(3:0)
LOAD
VOUT
VSS4
VSS3
CB
CA
VSS2+
VSS2VREG
V1
V2
V3
V4
V5
NC
NC
Fig .14
* This specification are subject to be changed without notice.
9.14.2001
15
EM83040B
LCD CONTROLLER
inary
m
i
l
e
r
P
(2) C32 x S128
C31
:
:
C0
LCD 32*128
S127 ...... S80
VDD
GND
MAIN
M1
M0
EN
RAMEN
RAMADS
RAMW
RAMR
RAMD(3:0)
VDD
VDD
VDD
LOAD
VOUT
VSS4
VSS3
CB
CA
VSS2+
VSS2VREG
V1
V2
V3
V4
V5
S79 ...... S0
LOAD
VOUT
VSS
VDD
VDD
NC
MASTER
VDD
GND
MAIN
M1
M0
EN
RAMEN
RAMADS
RAMW
RAMR
RAMD(3:0)
LOAD
VOUT
VSS4
VSS3
CB
CA
VSS2+
VSS2VREG
V1
V2
V3
V4
V5
LOAD
VOUT
NC
NC
NC
NC
NC
NC
NC
CONNECT
TO
MASTER
CHIP
SLAVE
Fig .15
(3) C48 x S112
LCD 48*112
C47
:
:
C0
S79 ...... S0
S111 ...... S80
VDD
VDD
GND
VDD
GND
MAIN
M1
M0
EN
RAMEN
RAMADS
RAMW
RAMR
RAMD(3:0)
LOAD
VOUT
VSS4
VSS3
CB
CA
VSS2+
VSS2VREG
V1
V2
V3
V4
V5
LOAD
VOUT
VSS
VDD
GND
NC
MASTER
VDD
GND
MAIN
M1
M0
EN
RAMEN
RAMADS
RAMW
RAMR
RAMD(3:0)
LOAD
VOUT
VSS4
VSS3
CB
CA
VSS2+
VSS2VREG
V1
V2
V3
V4
V5
LOAD
VOUT
NC
NC
NC
NC
NC
NC
NC
CONNECT
TO
MASTER
CHIP
SLAVE
Fig .16
* This specification are subject to be changed without notice.
9.14.2001
16
EM83040B
LCD CONTROLLER
i n ar y
m
i
l
e
r
P
(4) C64 x S96
LCD 64*96
C63
:
:
C0
S79 ...... S0
S95 ...... S80
VDD
GND
GND
VDD
GND
MAIN
M1
M0
EN
RAMEN
RAMADS
RAMW
RAMR
RAMD(3:0)
LOAD
VOUT
VSS4
VSS3
CB
CA
VSS2+
VSS2VREG
V1
V2
V3
V4
V5
LOAD
VOUT
VSS
GND
GND
NC
MASTER
VDD
GND
MAIN
M1
M0
EN
RAMEN
RAMADS
RAMW
RAMR
RAMD(3:0)
LOAD
VOUT
VSS4
VSS3
CB
CA
VSS2+
VSS2VREG
V1
V2
V3
V4
V5
LOAD
VOUT
NC
NC
NC
NC
NC
NC
NC
CONNECT
TO
MASTER
CHIP
SLAVE
Fig .17
* This specification are subject to be changed without notice.
9.14.2001
17
EM83040B
LCD CONTROLLER
inary
m
i
l
e
r
P
(5) C80 x S160
LCD 80*160
C79
:
:
C0
S79 ...... S0
VDD
GND
GND
VDD
GND
MAIN
M1
M0
EN
RAMEN
RAMADS
RAMW
RAMR
RAMD(3:0)
LOAD
VOUT
VSS4
VSS3
CB
CA
VSS2+
VSS2VREG
V1
V2
V3
V4
V5
LOAD
VOUT
VSS
GND
VDD
NC
MASTER
LOAD
VOUT
VSS4
VSS3
CB
CA
VSS2+
VSS2VREG
V1
V2
V3
V4
V5
VDD
GND
MAIN
M1
M0
EN
RAMEN
RAMADS
RAMW
RAMR
RAMD(3:0)
LOAD
VOUT
NC
NC
NC
NC
NC
NC
NC
CONNECT
TO
MASTER
CHIP
SLAVE1
S159 ...... S80
VSS
GND
VDD
VDD
GND
MAIN
M1
M0
EN
RAMEN
RAMADS
RAMW
RAMR
RAMD(3:0)
LOAD
VOUT
VSS4
VSS3
CB
CA
VSS2+
VSS2VREG
V1
V2
V3
V4
V5
LOAD
VOUT
NC
NC
NC
NC
NC
NC
NC
CONNECT
TO
MASTER
CHIP
SLAVE2
Fig .18
* This specification are subject to be changed without notice.
9.14.2001
18
EM83040B
LCD CONTROLLER
OP_51_
OP_52_
OP_53_
OP_54_
OP_55_
OP_56_
OP_57_
OP_58_
OP_59_
OP_60_
OP_61_
OP_62_
OP_63_
OP_64_
OP_65_
OP_66_
OP_67_
OP_69_
OP_70_
OP_71_
OP_72_
OP_73_
OP_74_
OP_75_
OP_76_
OP_77_
2
OP_78_
M1
3
OP_79_
M0
4
MAIN
ENB
PAD DIAGRAM
OP_68_
i n ar y
m
i
l
e
r
P
1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
RAMENB
9
94
OP_50_
RAMADS
10
93
OP_49_
RAMW
11
92
OP_48_
RAMR
12
91
OP_47_
RAMD_3_
13
90
OP_46_
RAMD_2_
14
89
OP_45_
RAMD_1_
15
88
OP_44_
RAMD_0_
16
87
OP_43_
LOAD
17
86
OP_42_
VDD
18
85
OP_41_
GND
19
84
OP_40_
VOUT
20
83
OP_39_
VSS4
21
82
OP_38_
VSS3
22
81
OP_37_
CB
23
80
OP_36_
CA
24
79
OP_35_
VSS2A
25
78
OP_34_
VSS2B
26
77
OP_33_
VV1
27
76
OP_32_
V2
28
75
OP_31_
VREG
29
74
OP_30_
V5
OP_0_
OP_1_
OP_2_
OP_3_
OP_4_
OP_5_
OP_6_
OP_7_
OP_8_
OP_9_
OP_10_
OP_11_
OP_12_
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
OP_29_
V4
51
OP_28_
50
OP_27_
49
OP_26_
48
OP_25_
47
OP_24_
46
OP_23_
45
OP_22_
44
OP_21_
43
OP_20_
42
OP_19_
41
OP_18_
40
OP_17_
39
OP_16_
38
OP_15_
37
OP_14_
36
OP_13_
35
V3
(0,0)
Chip Size : 3890 µm x 2500 µm
Pad No.
Sym.
1
MAIN
2
M1
3
M0
4
ENB(EN)
5
6
7
8
9
RAMENB(RAMEN)
10
RAMADS
11
RAMW
12
RAMR
13
RAMD_3_
14
RAMD_2_
15
RAMD_1_
16
RAMD_0_
17
LOAD
18
VDD
20
GND
* This specification are subject to be changed without notice.
X
-1370.0
-1480.0
-1590.0
-1700.0
Y
1120.0
1120.0
1120.0
1120.0
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
1065.0
955.0
845.0
735.0
630.0
525.0
420.0
315.0
210.0
105.0
0.0
9.14.2001
19
EM83040B
LCD CONTROLLER
inary
m
i
l
e
r
P
Pad No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Sym.
VSS4
VSS3
CB
CA
VSS2A(VSS2+)
VSS2B(VSS2-)
VV1(V1)
V2
VREG
X
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
-1820.0
Y
-210.0
-315.0
-420.0
-525.0
-630.0
-735.0
-845.0
-955.0
-1065.0
V3
V4
V5
OP_0_
OP_1_
OP_2_
OP_3_
OP_4_
OP_5_
OP_6_
OP_7_
OP_8_
OP_9_
OP_10_
OP_11_
OP_12_
OP_13_
OP_14_
OP_15_
OP_16_
OP_17_
OP_18_
OP_19_
OP_20_
OP_21_
OP_22_
OP_23_
OP_24_
OP_25_
OP_26_
OP_27_
-1700.0
-1590.0
-1480.0
-1370.0
-1265.0
-1160.0
-1055.0
-950.0
-845.0
-740.0
-635.0
-530.0
-425.0
-320.0
-215.0
-110.0
-5.0
100.0
205.0
310.0
415.0
520.0
625.0
730.0
835.0
940.0
1045.0
1150.0
1255.0
1365.0
1475.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
-1120.0
* This specification are subject to be changed without notice.
9.14.2001
20
EM83040B
LCD CONTROLLER
i n ar y
m
i
l
e
r
P
Pad No.
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
Sym.
OP_28_
OP_29_
X
1585.0
1695.0
Y
-1120.0
-1120.0
OP_30_
OP_31_
OP_32_
OP_33_
OP_34_
OP_35_
OP_36_
OP_37_
OP_38_
OP_39_
OP_40_
OP_41_
OP_42_
OP_43_
OP_44_
OP_45_
OP_46_
OP_47_
OP_48_
OP_49_
OP_50_
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1820.0
1660.0
-1065.0
-955.0
-845.0
-735.0
-630.0
-525.0
-420.0
-315.0
-210.0
-105.0
0.0
105.0
210.0
315.0
420.0
525.0
630.0
740.0
850.0
960.0
1115.0
OP_51_
OP_52_
OP_53_
OP_54_
OP_55_
OP_56_
OP_57_
OP_58_
OP_59_
OP_60_
1695.0
1585.0
1475.0
1365.0
1255.0
1150.0
1045.0
940.0
835.0
730.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
* This specification are subject to be changed without notice.
9.14.2001
21
EM83040B
LCD CONTROLLER
inary
m
i
l
e
r
P
Pad No.
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Sym.
OP_61_
OP_62_
OP_63_
OP_64_
OP_65_
OP_66_
OP_67_
OP_68_
OP_69_
OP_70_
OP_71_
OP_72_
OP_73_
OP_74_
OP_75_
OP_76_
OP_77_
OP_78_
OP_79_
X
625.0
520.0
415.0
310.0
205.0
100.0
-5.0
-110.0
-215.0
-320.0
-425.0
-530.0
-635.0
-740.0
-845.0
-950.0
-1055.0
-1160.0
-1265.0
Y
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
1120.0
* The substrate must be fixed at GND level or floating, cannot fixed to VDD level.
* This specification are subject to be changed without notice.
9.14.2001
22