AD ADM483EARZ-REEL 15,-15 kv esd protected, slew rate Datasheet

±15 kV ESD Protected, Slew Rate
Limited, 5 V, RS-485 Transceiver
ADM483E
±15 kV ESD protection
250 kbps data rate
Reduced slew rate for low EM interference
Single 5 V ± 10% supply
−7 V to +12 V bus common-mode range
Up to 32 nodes on the bus
Receiver open-circuit, fail-safe design
Short-circuit protection
36 μA supply current
0.1 μA shutdown current
FUNCTIONAL BLOCK DIAGRAM
ADM483E
RO
R
B
RE
DE
DI
A
D
06012-001
FEATURES
Figure 1.
APPLICATIONS
Low power RS-485 systems
Electrically harsh environments
EMI sensitive applications
DTE-DCE interface
Packet switching
Local area networks
GENERAL DESCRIPTION
The ADM483E is a 5 V, low power data transceiver with ±15 kV
ESD protection suitable for half-duplex communication on
multipoint bus transmission lines. The ADM483E is designed
for balanced data transmission and complies with TIA/EIA
Standards RS-485 and RS-422, which allow up to 32 transceivers
on a bus.
The ADM483E has a low current shutdown mode in which it
consumes only 0.1 μA.
Drivers are short-circuit current-limited and are protected
against excessive power dissipation by thermal shutdown
circuitry that places their outputs into a high impedance state.
The receiver input has a fail-safe feature that guarantees a logic
high output if the input is open circuit.
The ADM483E is fully specified over the industrial temperature
ranges and is available in 8-lead SOIC_N packages.
Because only one driver is enabled at any time, the output of a
disabled or power-down driver is three-stated to avoid
overloading the bus.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1997–2007 Analog Devices, Inc. All rights reserved.
ADM483E
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits and Switching Characteristics...................................9
Applications....................................................................................... 1
General Information ...................................................................... 11
Functional Block Diagram .............................................................. 1
ESD Transient Protection Scheme ........................................... 11
General Description ......................................................................... 1
ESD Testing ................................................................................. 12
Revision History ............................................................................... 2
Applications Information .............................................................. 13
Specifications..................................................................................... 3
Differential Data Transmission ................................................ 13
Timing Specifications .................................................................. 4
Cable and Data Rate................................................................... 13
Absolute Maximum Ratings............................................................ 5
Outline Dimensions ....................................................................... 14
ESD Caution.................................................................................. 5
Ordering Guide .......................................................................... 14
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
12/07—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Features ......................................................................... 1
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Table 5............................................................................ 6
Changes to Typical Performance Characteristics Section........... 7
Changes to Test Circuits and Switching Characteristics Section...9
Changes to General Information Section.................................... 11
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
1/97—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADM483E
SPECIFICATIONS
VCC = 5 V ± 10%. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
DRIVER
Differential Output Voltage, VOD
Min
Typ
2.0
1.5
1.5
Δ|VOD| for Complementary Output States
Common-Mode Output Voltage, VOC
Δ|VOC| for Complementary Output States
Output Short-Circuit Current (VOUT = High)
Output Short-Circuit Current (VOUT = Low)
CMOS Input Logic Threshold Low, VINL
CMOS Input Logic Threshold High, VINH
Logic Input Current (DE, DI)
RECEIVER
Differential Input Threshold Voltage, VTH
Input Voltage Hysteresis, ΔVTH
Input Resistance
Input Current (A, B)
2.0
1.4
1.4
Max
Unit
Test Conditions/Comments
5.0
5.0
5.0
5.0
0.2
3
0.2
250
250
0.8
V
V
V
V
V
V
V
mA
mA
V
V
μA
VCC = 5.25 V; R = ∞, see Figure 15
R = 50 Ω (RS-422), see Figure 15
R = 27 Ω (RS-485), see Figure 15
VIN = –7 V to +12 V
R = 27 Ω or 50 Ω, see Figure 15
R = 27 Ω or 50 Ω, see Figure 15
R = 27 Ω or 50 Ω
–7 V ≤ VO ≤ +12 V
–7 V ≤ VO ≤ +12 V
−7 V ≤ VCM ≤ +12 V
VCM = 0 V
−7 V ≤ VCM ≤ +12 V
VIN = 12 V
VIN = –7 V
85
±2.0
V
mV
kΩ
mA
mA
μA
V
V
mA
μA
120
360
10
μA
μA
μA
IOUT = 4.0 mA
IOUT = −4.0 mA
VOUT = GND or VCC
0.4 V ≤ VOUT ≤ 2.4 V
Outputs unloaded, receivers enabled
DE = 0 V (disabled), RE = 0 V
DE = 5 V (enabled), RE = 0 V
DE = 0 V, RE = VCC
kV
HBM air discharge; Pin A, Pin B
±1.0
−0.2
+0.2
70
12
1
−0.8
Logic Enable Input Current (RE)
CMOS Output Voltage Low, VOL
CMOS Output Voltage High, VOH
Short-Circuit Output Current
Three-State Output Leakage Current
POWER SUPPLY CURRENT
ICC
Supply Current in Shutdown
ESD IMMUNITY
ESD Protection
±1
0.4
4.0
7
36
270
0.1
±15
Rev. A | Page 3 of 16
ADM483E
TIMING SPECIFICATIONS
VCC = 5 V ± 10%. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
DRIVER
Propagation Delay Input to Output (tPLH, tPHL)
Min
Max
Unit
Test Conditions/Comments
2000
ns
800
ns
250
2000
ns
250
300
2000
3000
ns
ns
RL Diff = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and
Figure 17
RL Diff = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and
Figure 17
RL Diff = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and
Figure 17
RL = 500 Ω, CL = 100 pF, see Figure 18 and Figure 19
RL = 500 Ω, CL = 15 pF, see Figure 18 and Figure 19
2000
50
50
ns
ns
ns
ns
RL = 1 kΩ, CL = 15 pF, see Figure 22
RL = 1 kΩ, CL = 15 pF, see Figure 22
3000
5000
5000
ns
ns
ns
RL = 500 Ω, CL = 100 pF, see Figure 18 and Figure 19
RL = 1 kΩ, CL = 15 pF, see Figure 22
250
100
Driver Output to Output (tSKEW)
Driver Rise/Fall Time (tR, tF)
Driver Enable to Output Valid
Driver Disable Timing
RECEIVER
Propagation Delay Input to Output (tPLH, tPHL)
Skew (|tPLH – tPHL|)
Receiver Enable (tEN1)
Receiver Disable (tEN2)
SHUTDOWN
Time to Shutdown
Driver Enable from Shutdown
Receiver Enable from Shutdown
Typ
250
200
10
10
50
200
Rev. A | Page 4 of 16
CL = 15 pF, see Figure 20
ADM483E
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VCC to GND
Digital I/O Voltage (DE, RE)
Driver Input Voltage (DI)
Receiver Output Voltage (RO)
Driver Output/Receiver Input Voltage
(Pin A, Pin B)
ESD Rating: Air (Human Body Model)
(Pin A, Pin B)
Power Dissipation 8-Lead SOIC_N
θJA, Thermal Impedance
Operating Temperature Range
Industrial (A Version)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.5 V to +6 V
−0.5 V to (VCC + 0.5 V)
−0.5 V to (VCC + 0.5 V)
−0.5 V to (VCC + 0.5 V)
−9 V to +14 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
±15 kV
470 mW
110°C/W
−40°C to +85°C
−65°C to +150°C
300°C
215°C
220°C
Rev. A | Page 5 of 16
ADM483E
RO 1
RE 2
ADM483E
DE 3
TOP VIEW
DI 4 (Not to Scale)
8
VCC
7
B
6
A
5
GND
06012-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
Mnemonic
RO
RE
3
DE
4
DI
5
6
7
8
GND
A
B
VCC
Description
Receiver Output. When enabled, if A > B by 200 mV, then RO = high. If A < B by 200 mV, then RO = low.
Receiver Output Enable. A low level enables the receiver output, RO. A high level places the receiver output in a high
impedance state.
Driver Output Enable. A high level enables the driver differential outputs, A and B. A low level places the driver
differential outputs in a high impedance state.
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high. A logic high on DI forces
A high and B low.
Ground Connection, 0 V.
Noninverting Receiver Input A/Driver Output A.
Inverting Receiver Input B/Driver Output B.
Power Supply, 5 V ± 10%.
Table 5. Selection Table
Part No.
ADM483E
Duplex
Half
Data Rate (kbps)
250
Low Power Shutdown
Yes
Tx/Rx Enable
Yes
Rev. A | Page 6 of 16
ICC (μA)
36
No. of Tx/Rx on Bus
32
ESD kV
±15
ADM483E
TYPICAL PERFORMANCE CHARACTERISTICS
50
0.9
45
0.8
OUTPUT LOW VOLTAGE (V)
35
30
25
20
15
10
0.6
0.5
0.4
0.3
0.2
0.1
5
0
0.5
1.0
1.5
2.0
2.5
OUTPUT LOW VOLTAGE (V)
0
–40
06012-003
0
0.7
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 3. Output Current vs. Receiver Output Low Voltage
06012-006
OUTPUT CURRENT (mA)
40
Figure 6. Receiver Output Low Voltage vs. Temperature
45
–30
40
–25
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
35
–20
–15
–10
30
25
20
15
10
–5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT HIGH VOLTAGE (V)
0
06012-004
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Figure 7. Driver Output Current vs. Differential Output Voltage
2.3
DIFFERENTIAL OUTPUT VOLTAGE (V)
4.5
4.4
4.3
4.2
4.1
4.0
–20
0
20
40
60
80
TEMPERATURE (°C)
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
–40
06012-005
OUTPUT HIGH VOLTAGE (V)
0.5
DIFFERENTIAL OUTPUT VOLTAGE (V)
Figure 4. Output Current vs. Receiver Output High Voltage
3.9
–40
0
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 5. Receiver Output High Voltage vs. Temperature
Figure 8. Driver Differential Output Voltage vs. Temperature
Rev. A | Page 7 of 16
06012-008
0
1.5
06012-007
5
ADM483E
10
140
9
120
SHUTDOWN CURRENT (µA)
80
60
40
7
6
5
4
3
2
20
1
0
2
4
6
8
10
12
OUTPUT LOW VOLTAGE (V)
0
–60
06012-009
0
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 9. Output Current vs. Driver Output Low Voltage
Figure 12. Shutdown Current vs. Temperature
–140
OUTPUT CURRENT (mA)
–120
–100
–80
A
B
2
–60
–40
RO
–20
–4
–2
0
2
4
6
OUTPUT HIGH VOLTAGE (V)
CH1 5.00V CH2 500mV
CH3 500mV
Figure 10. Output Current vs. Driver Output High Voltage
M200ns
T
57.60%
A CH1
2.80V
06012-013
–6
06012-010
1
0
–8
Figure 13. ADM483E Receiver tPHL
600
400
B
300
A
2
200
DE = VCC AND RE = x
DE = 0 AND RE = 0
DE = 0 AND RE = VCC
RO
1
0
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
CH1 5.00V CH2 500mV
CH3 500mV
Figure 11. ADM483E Supply Current vs. Temperature
M200ns
T
60.80%
A CH1
Figure 14. ADM483E Receiver tPLH
Driven by External RS-485 Device
Rev. A | Page 8 of 16
2.80V
06012-014
100
06012-011
SUPPLY CURRENT (µA)
500
06012-012
OUTPUT CURRENT (mA)
8
100
ADM483E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
Y
VCC
RL = 500Ω
S1
RL
0V OR 5V
D
OUT
CL
VOD
VOC
GENERATOR
06012-015
RL
Z
50Ω
Figure 15. Driver DC Test Load
5V
DE
5V
VCC/2
0V
tDZL,
tDZL(SHDN)
CL
2.3V
OUT
RL
0.5V
VOL
B
Figure 19. Driver Enable and Disable Times (tDZL, tDLZ, tDZL(SHDN))
06012-016
CL
VID
ATE
5V
DI
tDPLH
tDPHL
1/2 VO
Figure 20. Receiver Propagation Delay Test Circuit
B
A
+1V
A
VO
B
tRPLH
1/2VO
VDIFF = V (A) – V (B)
90%
RO
90%
10%
tDR
1.5V
VOL
10%
tDF
tSKEW = tDPLH – tDPHL
Figure 17. Driver Propagation Delays
S1
0 OR 5V
GENERATOR
D
OUT
CL
RL = 500Ω
50Ω
5V
DE
1.5V
0V
tDZH,
tDZH(SHDN)
0.5V
VOH
2.3V
tDHZ
0V
06012-018
OUT
–1V
tRPHL
VOH
06012-017
+VO
VDIFF
0V
–VO
R
A
1.5V
0V
RECEIVER
OUTPUT
B
Figure 16. Driver Timing Test Circuit
Figure 18. Driver Enable and Disable Times (tDHZ, tDZH, tDZH(SHDN))
Rev. A | Page 9 of 16
THE RISE TIME AND FALL TIME OF INPUT A AND INPUT B < 4ns
Figure 21. Receiver Propagation Delays
06012-021
VOD
06012-020
DI
tDLZ
VCC
A
06012-019
DE
ADM483E
S1
S3
–1.5V
0V OR 5V
GENERATOR
VCC
1kΩ
VID
CL
15pF
S2
50Ω
S1 CLOSED
S2 OPEN
S3 = –1.5V
S1 OPEN
S2 CLOSED
S3 = +1.5V
+5V
+5V
RE
RE
0V
tRZH, tRZH(SHDN)
tRZL, tRZL(SHDN)
+1.5V
RO
0V
VOL
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = +1.5V
+5V
RE
+5V
RE
+1.5V
0V
RO
+1.5V
tRLZ
tRHZ
+0.5V
0V
VCC
VOH
+1.5V
RO
+1.5V
0V
VCC
VOH
RO
0V
+0.5V
Figure 22. Receiver Enable and Disable Times
Rev. A | Page 10 of 16
VOL
06012-022
+1.5V
ADM483E
GENERAL INFORMATION
+5V
+5V
The ADM483E is a robust RS-485 transceiver that operates
from a single 5 V supply.
0.1µF
It is ideally suited for operation in electrically harsh environments or where cables may be plugged and unplugged. It is also
immune to high RF field strengths without special shielding
precautions. The ADM483E is intended for balanced data
transmission and complies with both EIA Standards RS-485 and
RS-422. It contains a differential line driver and a differential
line receiver; it is suitable for half-duplex data transmission
because the driver and receiver share the same differential pins.
RE
The receiver has a fail-safe feature that results in a logic high
output state if the inputs are unconnected (floating).
A high level of robustness is achieved using internal protection
circuitry, eliminating the need for external protection components
such as transorbs or surge suppressors.
VCC
VCC
B
ADM483E
B
A
A
ADM483E
RS-485/RS-422 LINK
DI
RO
GND
GND
RE
06012-023
DE
DE
DI
RO
The input impedance on the ADM483E is 12 kΩ, allowing up to
32 transceivers on the differential bus.
The ADM483E operates from a single 5 V ± 10% power supply.
Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit.
This feature forces the driver output into a high impedance state
if, during fault conditions, a significant temperature increase is
detected in the internal driver circuitry.
0.1µF
Figure 23. Typical Half-Duplex Link Application
Table 6 and Table 7 show the truth tables for transmitting and
receiving.
Table 6. Transmitting Truth Table
RE
Inputs
DE
DI
B
X1
X1
0
1
1
1
0
0
1
0
X1
X1
0
1
High-Z
High-Z
1
Outputs
A
X = don’t care.
Low electromagnetic emissions are achieved using slew limited
drivers, minimizing interference both conducted and radiated.
Table 7. Receiving Truth Table
The ADM483E can transmit at data rates up to 250 kbps.
RE
A typical application for the ADM483E is illustrated in Figure 23.
This figure shows a half-duplex link where data may be
transferred at rates up to 250 kbps. A terminating resistor is
shown at both ends of the link. This termination is not critical
because the slew rate is controlled by the ADM483E and
reflections are minimized.
0
0
0
1
The communications network can be extended to include
multipoint connections as shown in Figure 26. Up to 32
transceivers can be connected to the bus.
ESD TRANSIENT PROTECTION SCHEME
1
1
0
High-Z
High-Z
Inputs
DE
0
0
0
0
Outputs
A−B
RO
≥ +0.2 V
≤ −0.2 V
Inputs O/C
X1
1
0
1
High-Z
X = don’t care.
The ADM483E uses protective clamping structures on its inputs
and outputs that clamp the voltage to a safe level and dissipate
the energy present in ESD (electrostatic discharge).
The protection structure achieves ESD protection up to ±15 kV
according to the Human Body Model.
Rev. A | Page 11 of 16
ADM483E
Although very little energy is contained within an ESD pulse,
the extremely fast rise time, coupled with high voltages, can
cause failures in unprotected semiconductors. Catastrophic
destruction may occur immediately as a result of arcing or
heating. Even if catastrophic failure does not occur immediately,
the device may suffer from parametric degradation, which can
result in degraded performance. The cumulative effects of
continuous exposure may eventually lead to complete failure.
HIGH
VOLTAGE
GENERATOR
It is possible that the ESD discharge could induce latch-up in
the device under test. Therefore, it is important that ESD testing
on the I/O pins be carried out while device power is applied.
This type of testing is more representative of a real-world I/O
discharge where the equipment is operating normally when the
discharge occurs.
100%
90%
36.8%
10%
TIME (t)
tRL
R2
Figure 25. Human Body Model ESD Current Waveform
DEVICE
UNDER TEST
ESD TEST METHOD
R2
C1
HUMAN BODY MODEL
1.5kΩ
100pF
Table 8. ADM483E ESD Test Results
ESD Test Method
Human Body Model: Air
Human Body Model: Contact
06012-024
C1
tDL
Figure 24. ESD Generator
I/O lines are particularly vulnerable to ESD damage. Simply
touching or plugging in an I/O cable can result in a static
discharge that may damage or completely destroy the interface
product connected to the I/O port.
Rev. A | Page 12 of 16
I/O Pins
±15 kV
±8 kV
06012-025
Two coupling methods are used for ESD testing: contact
discharge and air-gap discharge. Contact discharge calls for a
direct connection to the unit being tested. Air-gap discharge
uses a higher test voltage but does not make direct contact with
the unit under test. With air-gap discharge, the discharge gun is
moved toward the unit under test, developing an arc across the
air gap. This method is influenced by humidity, temperature,
barometric pressure, distance, and rate of closure of the discharge
gun. The contact discharge method, though less realistic, is
more repeatable and is gaining acceptance and preference over
the air-gap method.
It is, therefore, extremely important to have high levels of ESD
protection on the I/O lines.
IPEAK
ESD TESTING
ADM483E
APPLICATIONS INFORMATION
DIFFERENTIAL DATA TRANSMISSION
CABLE AND DATA RATE
Differential data transmission is used to reliably transmit data at
high rates over long distances and through noisy environments.
Differential transmission nullifies the effects of ground shifts
and noise signals that appear as common-mode voltages on the
line. There are two main standards approved by the Electronics
Industries Association (EIA) that specify the electrical characteristics of transceivers used in differential data transmission.
The transmission line of choice for RS-485 communications is a
twisted pair. Twisted pair cable tends to cancel common-mode
noise and also cancels the magnetic fields generated by the
current flowing through each wire, thereby reducing the
effective inductance of the pair.
To accommodate true multipoint communications, the RS-485
standard was defined. This standard meets or exceeds all the
requirements of RS-422 and also allows for up to 32 drivers and
32 receivers to be connected to a single bus. An extended
common-mode range of −7 V to +12 V is defined. The most
significant difference between RS-422 and RS-485 is the fact
that the drivers can be disabled, thereby allowing more than one
(32, in fact) to be connected to a single line. Only one driver
should be enabled at a time, but the RS-485 standard contains
additional specifications to guarantee device safety in the event
of line contention.
RT
RT
D
Rev. A | Page 13 of 16
D
R
R
D
R
D
R
Figure 26. Typical RS-485 Network
06012-026
The RS-422 standard specifies data rates up to 10 MBaud and
line lengths up to 4000 feet. A single driver can drive a transmission
line with up to 10 receivers.
A typical application showing a multipoint transmission
network is shown in Figure 26. An RS-485 transmission line can
have as many as 32 transceivers on the bus. Only one driver can
transmit at a particular time, but multiple receivers can be
enabled simultaneously.
ADM483E
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
4.00 (0.1574)
3.80 (0.1497)
Figure 27. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
ADM483EAR
ADM483EAR-REEL
ADM483EARZ1
ADM483EARZ-REEL1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
1
Z = RoHS Compliant Part.
Rev. A | Page 14 of 16
Package Option
R-8
R-8
R-8
R-8
Ordering Quantity
2500
2500
ADM483E
NOTES
Rev. A | Page 15 of 16
ADM483E
NOTES
©1997–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06012-0-12/07(A)
Rev. A | Page 16 of 16