Cypress CY29352AXIT 2.5v or 3.3v, 200 mhz, 11 output zero delay buffer Datasheet

CY29352
2.5V or 3.3V, 200 MHz,
11 Output Zero Delay Buffer
Features
Description
■
Output frequency range: 16.67 MHz to 200 MHz
■
Input frequency range: 16.67 MHz to 200 MHz
The CY29352 is a low voltage high performance 200 MHz PLL
based zero delay buffer designed for high speed clock distribution applications.
■
2.5V or 3.3V operation
■
Split 2.5V and 3.3V outputs
■
±2% maximum output duty cycle variation
■
11 clock outputs: drive up to 22 clock lines
■
LVCMOS reference clock input
■
125 ps maximum output-output skew
■
PLL bypass mode
■
Spread Aware™
■
Output enable and disable
■
Pin compatible with MPC9352 and MPC952
■
Industrial temperature range: –40°C to +85°C
■
32-pin 1.4 mm TQFP package
The CY29352 features an LVCMOS reference clock input and
provides 11 outputs partitioned in three banks of five, four, and
two outputs. Bank A divides the VCO output by four and six
while bank B divides by four and two, and bank C divides by
two and four per SEL(A:C) settings, see Table 3 on page 3.
These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1,
2:3, 1:2, and 1:3. Each LVCMOS compatible output drives 50Ω
series or parallel terminated transmission lines. For series
terminated transmission lines, each output drives one or two
traces, giving the device an effective fanout of 1:22.
The PLL is stable if the VCO is configured to run between 200
MHz to 500 MHz. This allows a wide range of output
frequencies from 16.67 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO runs at multiples of the
input reference clock set by the feedback divider, see Table 2
on page 3. When PLL_EN# is HIGH, PLL is bypassed and the
reference clock directly feeds the output dividers. This mode
is fully static and the minimum input clock frequency specification does not apply.
Block Diagram
PLL_EN#
REFCLK
Phase
Detector
VCO
200-500MHz
÷2
÷4 /
÷6
FB_IN
QA0
QA1
QA2
QA3
QA4
LPF
VCO_SEL
SELA
÷4 /
÷2
QB0
QB1
SELB
QB2
QB3
÷2 /
÷4
QC0
QC1
SELC
MR/OE#
Cypress Semiconductor Corporation
Document Number: 38-07476 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 14, 2008
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CY29352
Pinouts
32
31
30
29
28
27
26
25
VDDQC
QC1
QC0
VSS
VSS
QB3
QB2
VDDQB
Figure 1. Pin Diagram - 32-pin 1.4 mm TQFP package
1
2
3
4
5
6
7
8
CY29352
24
23
22
21
20
19
18
17
VSS
QB1
QB0
VDDQB
VDDQA
QA4
QA3
VSS
PLL_EN#
AVDD
VDD
QA0
VSS
QA1
QA2
VDDQA
9
10
11
12
13
14
15
16
VCO_SEL
SELC
SELB
SELA
MR/OE#
REFCLK
AVSS
FB_IN
Table 1. Pin Definition - 32-pin 1.4 mm TQFP package
Pin
6
IO[1]
Name
REFCLK
I, PD
Type
LVCMOS
Description
Reference clock input
12, 14, 15, 18, 19 QA(0:4)
O
LVCMOS
Clock output bank A
22, 23, 26, 27
QB(0:3)
O
LVCMOS
Clock output bank B
30, 31
QC(0,1)
O
LVCMOS
Clock output bank C
8
FB_IN
I, PD
LVCMOS
Feedback clock input. Connect to an output for normal operation.
This input must be at the same voltage rail as input reference clock,
see Table 2 on page 3.
1
VCO_SEL
I, PD
LVCMOS
VCO divider select input, see Table 3 on page 3.
5
MR/OE#
I, PD
LVCMOS
Master reset or output enable and disable input, see Table 3 on page
3.
9
PLL_EN#
I, PD
LVCMOS
PLL enable and disable input, see Table 3 on page 3.
2, 3, 4
SEL(A:C)
I, PD
LVCMOS
Frequency select input, bank (A:C), see Table 3 on page 3.
16, 20
VDDQA
Supply
VDD
2.5V or 3.3V power supply for bank A output clocks [2,3]
21, 25
VDDQB
Supply
VDD
2.5V or 3.3V power supply for bank B output clocks [2,3]
32
VDDQC
Supply
VDD
2.5V or 3.3V power supply for bank C output clocks [2,3]
10
AVDD
Supply
VDD
2.5V or 3.3V power supply for PLL [2,3]
11
VDD
Supply
VDD
2.5V or 3.3V power supply for core and inputs [2,3]
7
AVSS
Supply
Ground
Analog ground
Supply
Ground
Common ground
13, 17, 24, 28, 29 VSS
Notes
1. PD = Internal pull down.
2. A 0.1-μF bypass capacitor must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, the
high frequency filtering characteristics are cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
Document Number: 38-07476 Rev. *B
Page 2 of 9
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CY29352
Table 2. Frequency Table
VCO_SEL
Feedback Output
Divider
Input Frequency Range
(AVDD = 3.3V)
0
÷2
Input clock * 2
100 MHz to 200 MHz
100 MHz to 200 MHz
0
÷4
Input clock * 4
50 MHz to 125 MHz
50 MHz to 100 MHz
0
÷6
Input clock * 6
33.33 MHz to 83.33 MHz
33.33 MHz to 66.67 MHz
1
÷2
Input clock * 4
50 MHz to 125 MHz
50 MHz to 100 MHz
1
÷4
Input clock * 8
25 MHz to 62.5 MHz
25 MHz to 50 MHz
1
÷6
Input clock * 12
16.67 MHz to 41.67 MHz
16.67 MHz to 33.33 MHz
VCO
Input Frequency Range
(AVDD = 2.5V)
Table 3. Function Table
Control
Default
0
1
VCO ÷ 2
VCO_SEL
0
VCO
PLL_EN#
0
PLL enabled, the VCO output connects Bypass mode, PLL disabled, the input clock
to the output dividers
connects to the output dividers
MR/OE#
0
Outputs enabled
SELA
0
QA = VCO ÷ 4
QA = VCO ÷ 6
SELB
0
QB = VCO ÷ 4
QB = VCO ÷ 2
SELC
0
QC = VCO ÷ 2
QC = VCO ÷ 4
Outputs disabled (three-state), VCO runs at its
minimum frequency
Absolute Maximum Conditions
Parameter
Description
Min
Max
Unit
–0.3
5.5
V
Functional
2.375
3.465
V
DC input voltage
Relative to VSS
–0.3
VDD + 0.3
V
VOUT
DC output voltage
Relative to VSS
–0.3
VDD + 0.3
V
VTT
Output termination voltage
VDD ÷ 2
V
LU
Latch up immunity
Functional
RPS
Power supply ripple
Ripple frequency < 100 kHz
TS
Temperature, storage
Non functional
–65
+150
°C
TA
Temperature, operating ambient
Functional
–40
+85
°C
TJ
Temperature, junction
Functional
155
°C
ØJC
Dissipation, junction to case
Functional
42
°C/W
ØJA
Dissipation, junction to ambient
Functional
105
°C/W
ESDH
ESD protection (human body model)
FIT
Failure in time
VDD
DC supply voltage
VDD
DC operating voltage
VIN
Document Number: 38-07476 Rev. *B
Condition
200
mA
150
2000
Manufacturing test
mVp-p
Volts
10
ppm
Page 3 of 9
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CY29352
DC Parameters (VDD= 2.5V ± 5%, TA = –40°C to +85°C)
Parameter
Description
VIL
Input voltage, low
VIH
Input voltage, high
Condition
Min
Typ
LVCMOS
LVCMOS
[4]
1.7
Max
Unit
0.7
V
VDD + 0.3
V
VOL
Output voltage, low
IOL = 15 mA
VOH
Output voltage, high[4]
IOH = –15 mA
IIL
Input current, low
VIL = VSS
–10
μA
VIL = VDD
100
μA
[5]
0.6
1.8
V
V
IIH
Input current, high
IDDA
PLL supply current
AVDD only
5
10
mA
IDDQ
Quiescent supply current
All VDD pins except AVDD
3
5
mA
IDD
Dynamic supply current
CIN
Input pin capacitance
ZOUT
Output impedance
170
mA
4
pF
17–20
Ω
DC Parameters (VDD= 3.3V ± 5%, TA = –40°C to +85°C)
Parameter
Description
Condition
Max
Unit
0.8
V
VDD + 0.3
V
IOL = 24 mA
0.55
V
IOL = 12 mA
0.30
VIL
Input voltage, low
LVCMOS
VIH
Input voltage, high
LVCMOS
VOL
Output voltage,
low[4]
VOH
Output voltage, high[4]
IOH = –24 mA
IIL
Input current, low
VIL = VSS
high[5]
2.4
V
–10
μA
μA
mA
0.8
V
VDD + 0.3
V
IOL = 24 mA
0.55
V
IOL = 12 mA
0.30
PLL supply current
AVDD only
VIL
Input voltage, low
LVCMOS
VIH
Input voltage, high
LVCMOS
Output voltage,
2.0
10
Input current,
IDDA
VOL
Typ
100
IIH
low[4]
Min
VIL = VDD
VOH
Output voltage, high[4]
IOH = –24 mA
IIL
Input current, low
VIL = VSS
5
2.0
2.4
V
–10
μA
IIH
Input current,
100
μA
IDDA
PLL supply current
AVDD only
5
10
mA
IDDQ
Quiescent supply current
All VDD pins except AVDD
3
5
mA
IDD
Dynamic supply current
CIN
Input pin capacitance
ZOUT
Output impedance
high[5]
VIL = VDD
240
mA
4
pF
14–17
Ω
Notes
4. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated transmission
lines.
5. Inputs have pull down resistors that affect the input current.
Document Number: 38-07476 Rev. *B
Page 4 of 9
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CY29352
AC Parameters (VDD= 2.5V ± 5%, TA = –40°C to +85°C)
Parameter[6]
Description
fVCO
VCO frequency
fin
Input frequency
Condition
Min
Typ
Max
Unit
200
400
MHz
÷2 feedback
100
200
MHz
÷4 feedback
50
100
÷6 feedback
33.33
66.67
÷8 feedback
25
50
÷12 feedback
16.67
33.33
0
200
25
75
Bypass mode (PLL_EN# = 1)
frefDC
Input duty cycle
tr , tf
TCLK input rise and fall time
0.7V to 1.7V
1.0
ns
fMAX
Maximum output frequency
÷2 output
100
200
MHz
÷4 output
50
100
÷6 output
33.33
66.67
DC
Output duty cycle
÷8 output
25
50
÷12 output
16.67
33.33
fMAX < 100 MHz
47
53
fMAX > 100 MHz
44
56
tr , tf
Output rise and fall times
0.6V to 1.8V
t(φ)
Propagation delay (static phase
offset)
TCLK to FB_IN, same VDD,
does not include jitter
tsk(O)
Output to output skew
tsk(B)
Bank to bank skew
tPLZ, HZ
Output enable time
BW
PLL closed loop bandwidth
(–3 dB)
tJIT(CC)
tJIT(PER)
tJIT(φ)
tLOCK
Cycle to cycle jitter
Period jitter
IO phase jitter
Maximum PLL lock time
Document Number: 38-07476 Rev. *B
%
0.1
1.0
ns
-100
100
ps
Skew within bank
125
ps
Banks at same voltage, same
frequency
175
ps
Banks at same voltage,
different frequency
225
Output disable time
tPZL, ZH
%
8
10
÷2 feedback
2
÷4 feedback
1–1.5
÷6 feedback
0.6
÷8 feedback
0.75
÷12 feedback
0.5
100
Multiple frequencies
300
Same frequency
100
Multiple frequencies
150
150
VCO > 300 MHz
100
ns
MHz
Same frequency
VCO < 300 MHz
ns
ps
ps
ps
1
ms
Page 5 of 9
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CY29352
AC Parameters (VDD = 3.3V ± 5%, TA = –40°C to +85°C)
Parameter[6]
Description
fVCO
VCO frequency
fin
Input frequency
Condition
÷2 feedback
Min
Typ
Max
Unit
200
500
MHz
100
200
MHz
÷4 feedback
50
125
÷6 feedback
33.33
83.33
÷8 feedback
25
62.5
÷12 feedback
16.67
41.67
0
200
25
75
%
1.0
ns
200
MHz
Bypass mode (PLL_EN# = 1)
frefDC
Input duty cycle
tr , tf
TCLK input rise and fall time
0.8V to 2.0V
fMAX
Maximum output frequency
÷2 output
100
÷4 output
50
125
÷6 output
33.33
83.33
÷8 output
25
62.5
÷12 output
16.67
41.67
48
52
%
–100
200
ps
DC
Output duty cycle
fMAX < 100 MHz
t(φ)
Propagation delay (static phase
offset)
TCLK to FB_IN, same VDD,
does not include jitter
tsk(O)
Output to output skew
Skew within each Bank
125
ps
tsk(B)
Bank to bank skew
Banks at same voltage, same
frequency
175
ps
Banks at same voltage,
different frequency
235
Banks at different voltage
425
tPLZ, HZ
Output disable time
8
ns
tPZL, ZH
Output enable time
10
ns
BW
PLL closed loop bandwidth
(–3 dB)
tJIT(CC)
tJIT(PER)
tJIT(φ)
tLOCK
Cycle to cycle jitter
Period jitter
IO phase jitter
Maximum PLL lock time
÷2 feedback
2
÷4 feedback
1–1.5
÷6 feedback
0.6
÷8 feedback
0.75
÷12 feedback
0.5
MHz
Same frequency
100
Multiple frequencies
275
Same frequency
100
Multiple frequencies
150
VCO < 300 MHz
150
VCO > 300 MHz
100
ps
ps
ps
1
ms
Note
6. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at the same supply voltage unless otherwise stated. Parameters are guaranteed
by characterization and are not 100% tested.
Document Number: 38-07476 Rev. *B
Page 6 of 9
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CY29352
Figure 2. AC Test Reference for VDD = 3.3V / 2.5V
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
R T = 50 ohm
R T = 50 ohm
VTT
VTT
Figure 3. Propagation Delay t(φ), Static Phase Offset
VDD
LVCMOS_CLK
V DD /2
GND
V DD
FB_IN
V DD /2
t(φ)
GND
Figure 4. Output Duty Cycle (DC)
V DD
V DD/2
tP
GND
T0
DC = tP / T0 x 100%
Figure 5. Output to Output Skew, tsk(O)
VDD
VDD/2
GND
VDD
VDD/2
tSK(O)
Document Number: 38-07476 Rev. *B
GND
Page 7 of 9
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CY29352
Ordering Information
Part Number
Package Type
Product Flow
Pb-Free
CY29352 AXI
32-pin TQFP
Industrial, –40°C to +85°C
CY29352 AXIT
32-pin TQFP—tape and reel
Industrial, –40°C to 85°C
Package Drawing and Dimension
Figure 6. 32 Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm
51-85088-*B
Document Number: 38-07476 Rev. *B
Page 8 of 9
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CY29352
Document History Page
Document Title:CY29352 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer
Document Number: 38-07476
REV.
ECN No. Issue Date
**
124654
03/21/03
*A
739798
See ECN
*B
1923227
See ECN
Orig. of
Change
Description of Change
RGL
New Data Sheet
RGL
Removed the leaded parts and replaced by lead-free parts
PYG/KVM/ Corrected package thickness from 1.0 mm to 1.4 mm in Features section on
AESA
page 1 and in Figure 5.
© Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07476 Rev. *B
Revised January 14, 2008
Page 9 of 9
Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
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