Am29PDS322D Data Sheet The following document contains information on Spansion memory products. Although the document is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 23569 Revision A Amendment 5 Issue Date December 4, 2006 THIS PAGE LEFT INTENTIONALLY BLANK. DATA SHEET Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only (1.8 V to 2.2 V) Simultaneous Read/Write Page-Mode Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank. — Zero latency between read and write operations ■ Page Mode Operation — 4 word page allows fast asynchronous reads ■ Dual Bank architecture — One 4 Mbit bank and one 28 Mbit bank ■ SecSi (Secured Silicon) Sector: Extra 64 KByte sector — Factory locked and identifiable: 16 byte Electronic Serial Number available for factory secure, random ID; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. ■ Package options — 48-ball FBGA ■ Top or bottom boot block ■ Manufactured on 0.23 µm process technology ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS ■ High performance — Access time as fast 40 ns (100 ns random access time) at 1.8 V to 2.2 V VCC — Random access time of 100 ns at 1.8 V to 2.2 V VCC will be required as customers migrate downward in voltage ■ Ultra low power consumption (typical values) — 2.5 mA active read current at 1 MHz for initial page read — 24 mA active read current at 10 MHz for initial page read — 0.5 mA active read current at 10 MHz for intra-page read — 1 mA active read current at 20 MHz for intra-page read — 200 nA in standby or automatic sleep mode ■ Minimum 1 million write cycles guaranteed per sector ■ 20 year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES ■ Data Management Software (DMS) — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations ■ Erase Suspend/Erase Resume — Suspends erase operations to allow programming in same bank ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to the read mode ■ WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing — ACC voltage is 8.5 V to 12.5 V ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 23569 Rev: A Amendment/5 Issue Date: December 4, 2006 D A T A S H E E T GENERAL DESCRIPTION The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash memory organized as 2,097,152 words of 16 bits each. This device is offered in a 48-ball FBGA package. The device is designed to be programmed in system with standard system 1.8 V V CC supply. This device can also be reprogrammed in standard EPROM programmers. The Am29PDS322D offers fast page access time of 40 ns with random access time of 100 ns (at 1.8 V to 2.2 V VCC), allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The page size is 4 words. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table: Bank 1 Sectors Quantity Size 8 4 Kwords 7 32 Kwords Bank 2 Sectors Quantity Size 56 32 Kwords 4 Mbits total 28 Mbits total Am29PDS322D Features The SecSi (Secured Silicon) Sector is an extra 64 KByte sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any 2 other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This i s a n a d va n t a g e c o m p a r e d t o s y s t e m s w h e r e user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Special Handling Instructions for FBGA Package .................... 5 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8 Table 1. Am29PDS322D Device Bus Operations .............................8 Requirements for Reading Array Data ..................................... 8 Read Mode ............................................................................... 8 Sector Erase Command Sequence ........................................ 24 Erase Suspend/Erase Resume Commands ........................... 24 Figure 6. Erase Operation.............................................................. 25 Am29PDS322D Command Definitions . . . . . . . . 26 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 27 DQ7: Data# Polling ................................................................. 27 Figure 7. Data# Polling Algorithm .................................................. 27 RY/BY#: Ready/Busy#............................................................ 28 DQ6: Toggle Bit I .................................................................... 28 Figure 8. Toggle Bit Algorithm........................................................ 28 Writing Commands/Command Sequences .............................. 9 DQ2: Toggle Bit II ................................................................... 29 Reading Toggle Bits DQ6/DQ2 ............................................... 29 DQ5: Exceeded Timing Limits ................................................ 29 DQ3: Sector Erase Timer ....................................................... 29 Accelerated Program Operation ........................................................9 Autoselect Functions .........................................................................9 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 31 Random Read (Non-Page Mode Read) ............................................8 Page Mode Read ...................................................................... 9 Table 2. Page Word Mode ................................................................9 Simultaneous Read/Write Operations with Zero Latency ......... 9 Standby Mode .......................................................................... 9 Automatic Sleep Mode ........................................................... 10 RESET#: Hardware Reset Pin ............................................... 10 Output Disable Mode .............................................................. 10 Table 3. Am29PDS322DT Top Boot Sector Addresses ..................11 Table 4. Am29PDS322DT Top Boot SecSi Sector Address ...........12 Table 5. Am29PDS322DB Bottom Boot Sector Addresses ............12 Table 6. Am29PDS322DB Bottom Boot SecSi Sector Address . . .14 Table 11. Write Operation Status ................................................... 30 Figure 9. Maximum Negative Overshoot Waveform ...................... 31 Figure 10. Maximum Positive Overshoot Waveform...................... 31 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) .............................................................................. 33 Figure 12. Typical ICC1 vs. Frequency ............................................ 33 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Autoselect Mode..................................................................... 15 Figure 13. Test Setup.................................................................... 34 Table 12. Test Specifications ......................................................... 34 Table 7. Autoselect Codes (High Voltage Method) ........................15 Key to Switching Waveforms. . . . . . . . . . . . . . . . 34 Sector/Sector Block Protection and Unprotection .................. 16 Figure 14. Input Waveforms and Measurement Levels ................. 34 Table 8. Top Boot Sector/Sector Block Addresses for Protection/Unprotection ...................................................................16 Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection ...................................................................16 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 Write Protect (WP#) ................................................................ 17 Temporary Sector/Sector Block Unprotect ............................. 17 Figure 1. Temporary Sector Unprotect Operation........................... 17 Figure 2. Temporary Sector Group Unprotect Operation................ 18 Figure 3. In-System Sector Group Protect/Unprotect Algorithms ... 19 SecSi (Secured Silicon) Sector Flash Memory Region .......... 20 Factory Locked: SecSi Sector Programmed and Protected at the Factory ..................................................................................20 Hardware Data Protection ...................................................... 20 Figure 15. Conventional Read Operation Timings ......................... 35 Figure 16. Page Mode Read Timings ............................................ 36 Hardware Reset (RESET#) .................................................... 37 Figure 17. Reset Timings ............................................................... 37 Erase and Program Operations .............................................. 38 Figure 18. Program Operation Timings.......................................... Figure 19. Accelerated Program Timing Diagram.......................... Figure 20. Chip/Sector Erase Operation Timings .......................... Figure 21. Back-to-back Read/Write Cycle Timings ...................... Figure 22. Data# Polling Timings (During Embedded Algorithms). Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... Figure 24. DQ2 vs. DQ6................................................................. 39 39 40 41 41 42 42 Low VCC Write Inhibit .......................................................................20 Write Pulse “Glitch” Protection ........................................................21 Logical Inhibit ..................................................................................21 Power-Up Write Inhibit ....................................................................21 Temporary Sector Unprotect .................................................. 43 Command Definitions . . . . . . . . . . . . . . . . . . . . . 21 Reading Array Data ................................................................ 21 Reset Command ..................................................................... 21 Autoselect Command Sequence ............................................ 21 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 22 Word Program Command Sequence ..................................... 22 Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings.......................................................................... 46 Unlock Bypass Command Sequence ..............................................22 Chip Erase Command Sequence ........................................... 22 Figure 4. Unlock Bypass Algorithm................................................. 23 Figure 5. Program Operation .......................................................... 23 December 4, 2006 23569A5 Figure 25. Temporary Sector Group Unprotect Timing Diagram ... 43 Figure 26. Sector Group Protect and Unprotect Timing Diagram .. 44 Alternate CE# Controlled Erase and Program Operations ..... 45 Erase And Programming Performance. . . . . . . . 47 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 47 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 48 FBD048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 12 mm package ................................................................ 48 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49 Am29PDS322D 3 D A T A S H E E T PRODUCT SELECTOR GUIDE Part Number Speed Options Am29PDS322D Standard Voltage Range: VCC = 1.8–2.2 V 10 12 Max Random Address Access Time (ns) 100 120 Max Page Address Access Time (ns) 40 45 CE# Access Time (ns) 100 120 OE# Access Time (ns) 35 40 Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM A0–A20 RY/BY# X-Decoder A0–A20 CE# WP#/ACC STATE CONTROL & COMMAND REGISTER Status DQ0–DQ15 Mux Control DQ0–DQ15 Lower Bank Address Lower Bank Latches and Control Logic A0–A20 Y-Decoder A0–A20 X-Decoder DQ0–DQ15 RESET# WE# Upper Bank DQ0–DQ15 Upper Bank Address A0–A20 Y-Decoder Mux Latches and Control Logic OE# VCC VSS Mux 4 Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T CONNECTION DIAGRAMS 48-Ball FBGA Top View, Balls Facing Down A6 B6 C6 D6 E6 F6 G6 H6 A13 A12 A14 A15 A16 NC DQ15 VSS A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A4 B4 C4 D4 E4 F4 G4 H4 WE# RESET# NC A19 DQ5 DQ12 VCC DQ4 A3 B3 C3 D3 E3 F3 G3 H3 A18 A20 DQ2 DQ10 DQ11 DQ3 RY/BY# WP#/ACC A2 B2 C2 D2 E2 F2 G2 H2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A1 B1 C1 D1 E1 F1 G1 H1 A3 A4 A2 A1 A0 CE# OE# VSS Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. December 4, 2006 23569A5 Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am29PDS322D 5 D A T A PIN DESCRIPTION A0–A20 = 21 Addresses inputs S H E E T LOGIC SYMBOL 21 DQ0–DQ15 = 16 Data inputs/outputs A0–A20 CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP#/ACC = Hardware Write Protect/ Acceleration Input WP#/ACC RESET# = Hardware Reset Pin input RESET# RY/BY# = Ready/Busy output VCC = 1.8 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VSS = Device Ground NC = Pin Not Connected Internally CE# 16 DQ0–DQ15 OE# WE# 6 Am29PDS322D RY/BY# 23569A5 December 4, 2006 D A T A S H E E T ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29PDS322D B 10 WM I N OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40°C to +85°C) PACKAGE TYPE WM = 48-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 12 mm package (FBD048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS Boot Sector Page Mode Flash Memory 1.8 Volt-only Read, Program, and Erase Valid Combinations Valid Combinations for FBGA Package Order Number Package Marking Am29PDS322DT10, Am29PDS322DB10 WMI P322DT10U, P322DB10U I Am29PDS322DT12, Am29PDS322DB12 WMI P322DT12U, P322DB12U I December 4, 2006 23569A5 Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29PDS322D 7 D A T A S H E E T DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am29PDS322D Device Bus Operations CE# OE# WE# RESET# WP#/ACC Addresses (Note 1) DQ0–DQ15 Read L L H H L/H AIN DOUT Write L H L H (Note 2) AIN DIN VCC ± 0.3 V X X VCC ± 0.3 V H X High-Z Output Disable L H H H L/H X High-Z Reset X X X L L/H X High-Z Sector Protect (Note 1) L H L VID L/H SA, A6 = L, A1 = H, A0 = L DIN Sector Unprotect (Note 1) L H L VID (Note 2) SA, A6 = H, A1 = H, A0 = L DIN Temporary Sector Unprotect X X X VID (Note 2) AIN DIN Operation Standby Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 9.0–11.0 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 2. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 15 for the 8 timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Read Mode Random Read (Non-Page Mode Read) The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the power control and should be used for device selection. OE# is the output control and should be used to gate data to the output pins if the device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE ) is the delay from the stable addresses and stable CE# to valid data at the output pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable for at least tACC–tOE time). Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T Page Mode Read Accelerated Program Operation The device is capable of fast Page mode read and is compatible with the Page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The Page size of the device is 4 words. The appropriate Page is selected by the higher address bits A20–A2 and the LSB bits A1–A0 determine the specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. The random or initial page access is equal to tACC or tCE and subsequent Page read accesses (as long as the locations specified by the microprocessor falls within that Page) are equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output pins if the device is selected. Fast Page mode accesses are obtained by keeping A2–A20 constant and changing A0 to A1 to select the specific word within that page. See Figure 16 for timing specifications. The following table determines the specific word within the selected page: Table 2. A1 A0 Word 0 0 0 Word 1 0 1 Word 2 1 0 Word 3 1 1 Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address space that each sector occupies. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. December 4, 2006 23569A5 Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency Page Word Mode Word If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC pin returns the device to normal operation. This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. Am29PDS322D 9 D A T A If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Automatic sleep mode current is drawn when CE# = VSS ± 0.3 V and all inputs are held at VCC ± 0.3 V. If CE# and RESET# voltages are not held within these tolerances, the automatic sleep mode current will be greater. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- 10 S H E E T chine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS ± 0.3 V, the device draws CMOS standby current (ICC3). If RESET# is held at VIL but not within VSS ± 0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 17 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T Table 3. Am29PDS322DT Top Boot Sector Addresses Bank 2 Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 December 4, 2006 23569A5 Sector Address A20–A12 000000xxx 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Am29PDS322D (x16) Address Range 000000h–07FFFh 008000h–0FFFFh 010000h–17FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 11 D A T A Table 3. Bank 1 Bank 2 Bank Sector SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 S H E E T Am29PDS322DT Top Boot Sector Addresses (Continued) Sector Address A20–A12 101100xxx 101101xxx 101110xxx 101111xxx 110000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 Table 4. Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Am29PDS322DT Top Boot SecSi Sector Address Sector Address A20–A12 111111xxx Table 5. Bank 1 Bank 12 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 (x16) Address Range 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1F8FFFh 1F9000h–1F9FFFh 1FA000h–1FAFFFh 1FB000h–1FBFFFh 1FC000h–1FCFFFh 1FD000h–1FDFFFh 1FE000h–1FEFFFh 1FF000h–1FFFFFh Sector Size 32 (x16) Address Range 1F8000h–1FFFFh Am29PDS322DB Bottom Boot Sector Addresses Sector Address A20–A12 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx Sector Size (Kwords) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 Am29PDS322D (x16) Address Range 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 23569A5 December 4, 2006 D A T A Table 5. Bank 2 Bank Sector SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 December 4, 2006 23569A5 S H E E T Am29PDS322DB Bottom Boot Sector Addresses (Continued) Sector Address A20–A12 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 111000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx Sector Size (Kwords) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Am29PDS322D (x16) Address Range 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 090000h–097FFFh 098000h–09FFFFh 0A0000h–0A7FFFh 0A8000h–0AFFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 13 D A T A Table 5. Bank 2 Bank Sector SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 S H E E T Am29PDS322DB Bottom Boot Sector Addresses (Continued) Sector Address A20–A12 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111xxx Table 6. Sector Size (Kwords) 32 32 32 32 32 32 32 32 (x16) Address Range 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh Am29PDS322DB Bottom Boot SecSi Sector Address Sector Address A20–A12 000000xxx Sector Size 32 (x16) Address Range 00000h-07FFFh . 14 Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T Autoselect Mode Table 7. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 3 through 6). Table 7 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0. The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 10. This method does not require V ID. Refer to the Autoselect Command Sequence section for more information. When using programming equipment, the autoselect mode requires VID (8.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 7. Autoselect Codes (High Voltage Method) Description CE# OE# WE# A20 to A12 A11 to A10 A9 A8 to A7 A6 A5 to A4 A3 A2 A1 A0 DQ15 to DQ0 Manufacturer ID: AMD L L H X X VID X L X X X L L 0001h Device ID Word 1 L L H X X VID X L X L L L H 227Eh Device ID Word 2 L L H X X VID X L X H H H L 2206h Device ID Word 3: Top or Bottom Boot L L H X X VID X L X H H H H 2201h (Top Boot), 2200h (Bottom Boot) Sector Protection Verification L L H SA X VID X L X X X H L XX01h (protected), XX00h (unprotected) SecSi Indicator Bit (DQ7), WP# protects highest address sector L L H X X VID X L X X X H H 80h (factory locked), 00h (not factory locked) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. December 4, 2006 23569A5 Am29PDS322D 15 D A T A Sector/Sector Block Protection and Unprotection Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 8 and 9). Table 8. Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SA0 SA1–SA3 SA4–SA7 SA8–SA11 SA12–SA15 SA16–SA19 SA20–SA23 A20–A12 000000XXX 00001XXXX 0001XXXXX 0010XXXXX 0011XXXXX 0100XXXXX 0101XXXXX Sectors A20–A12 Sector/Sector Block Size SA70 111111XXX 64 (1x64) Kbytes SGA1 SA69–SA67 11110XXXX 192 (3x64) Kbytes SGA2 SA66–SA63 1110XXXXX 256 (4x64) Kbytes SGA3 SA62–SA59 1101XXXXX 256 (4x64) Kbytes SGA4 SA58–SA55 1100XXXXX 256 (4x64) Kbytes SGA5 SA54–SA51 1011XXXXX 256 (4x64) Kbytes SGA6 SA50–SA47 1010XXXXX 256 (4x64) Kbytes SGA7 SA46–SA43 1001XXXXX 256 (4x64) Kbytes SGA8 SA42–SA39 1000XXXXX 256 (4x64) Kbytes 64 (1x64) Kbytes SGA9 SA38–SA35 0111XXXXX 256 (4x64) Kbytes 192 (3x64) Kbytes SGA10 SA34–SA31 0110XXXXX 256 (4x64) Kbytes 256 (4x64) Kbytes SGA11 SA30–SA27 0101XXXXX 256 (4x64) Kbytes 256 (4x64) Kbytes SGA12 SA26–SA23 0100XXXXX 256 (4x64) Kbytes 256 (4x64) Kbytes SGA13 SA22–SA19 0011XXXXX 256 (4x64) Kbytes 256 (4x64) Kbytes SGA14 SA18–SA15 0010XXXXX 256 (4x64) Kbytes 256 (4x64) Kbytes SGA15 SA14–SA11 0001XXXXX 256 (4x64) Kbytes SA10–SA8 000011XXX 192 (3x64) Kbytes Sector/ Sector Block Size SGA7 SA24–SA27 0110XXXXX 256 (4x64) Kbytes SGA16 SGA8 SA28–SA31 0111XXXXX 256 (4x64) Kbytes SGA17 SA7 000000111 8 Kbytes 256 (4x64) Kbytes SGA18 SA6 000000110 8 Kbytes 256 (4x64) Kbytes SGA19 SA5 000000101 8 Kbytes 256 (4x64) Kbytes SGA20 SA4 000000100 8 Kbytes 256 (4x64) Kbytes SGA21 SA3 000000011 8 Kbytes 256 (4x64) Kbytes SGA22 SA2 000000010 8 Kbytes 256 (4x64) Kbytes SGA23 SA1 000000001 8 Kbytes SGA24 SA0 000000000 8 Kbytes SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SA32–SA35 SA36–SA39 SA40–SA43 SA44–SA47 SA48–SA51 SA52–SA55 1000XXXXX 1001XXXXX 1010XXXXX 1011XXXXX 1100XXXXX 1101XXXXX SGA15 SA56–SA59 1110XXXXX 256 (4x64) Kbytes SGA16 SA60–SA62 111100XXX 192 (3x64) Kbytes SGA17 SA63 111111000 8 Kbytes SGA18 SA64 111111001 8 Kbytes SGA19 SA65 111111010 8 Kbytes SGA20 SA66 111111011 8 Kbytes SGA21 SA67 111111100 8 Kbytes SGA22 SA68 111111101 8 Kbytes SGA23 SA69 111111110 8 Kbytes SGA24 SA70 111111111 8 Kbytes 16 Sector Group SGA0 Top Boot Sector/Sector Block Addresses for Protection/Unprotection Sectors S H E E T The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection and unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 3 shows the algorithms and Figure 26 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Am29PDS322D 23569A5 December 4, 2006 D A T A The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier AMD flash devices. Contact an AMD representative for further details. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details. S H E E T block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Tables 8 and 9). This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID (9.0 V – 11.0 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 25 shows the timing diagrams, for this feature. Write Protect (WP#) The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP#/ACC pin. START RESET# = VID (Note 1) If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two “outermost” 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the two outermost 8 Kbyte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Temporary Sector/Sector Block Unprotect (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector December 4, 2006 23569A5 Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Am29PDS322D Temporary Sector Unprotect Operation 17 D A T A S H E E T START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Group Unprotect Completed (Note 2) Notes: 1. All protected sector groups unprotected (If WP# = VIL, the first or last sector will remain protected). 2. All previously protected sector groups are protected once again. Figure 2. Temporary Sector Group Unprotect Operation 18 Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = VID Wait 1 μs Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = VID Wait 1 μs No First Write Cycle = 60h? First Write Cycle = 60h? Yes Yes Set up sector address No All sectors protected? Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Wait 150 µs Increment PLSCNT Temporary Sector Unprotect Mode Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Reset PLSCNT = 1 Read from sector address with A6 = 0, A1 = 1, A0 = 0 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Increment PLSCNT No No PLSCNT = 25? Yes Yes No Yes Device failed Protect another sector? PLSCNT = 1000? No Yes Remove VID from RESET# Device failed Write reset command Sector Protect Algorithm Read from sector address with A6 = 1, A1 = 1, A0 = 0 Data = 01h? Sector Protect complete Set up next sector address No Data = 00h? Yes Last sector verified? No Yes Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 3. December 4, 2006 23569A5 In-System Sector Group Protect/Unprotect Algorithms Am29PDS322D 19 D A T A SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 KBytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factor y locke d or custom er lockable. The factory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize that sector in any manner they choose. The customer-lockable version also has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors instead of the SecSi sector Factory Locked: SecSi Sector Programmed and Protected at the Factory In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with one of the following: ■ A random, secure ESN only ■ Customer code through the ExpressFlash service ■ Both a random, secure ESN and customer code through the ExpressFlash service. In devices that have an ESN, a Bottom Boot device will have the 16-byte ESN in the lowest addressable memory area at addresses 000000h–000007h. In the Top Boot device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at addresses 1F8000h–1F8007h. 20 S H E E T Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the random ESN. The devices are then shipped from AMD’s factory with the permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected at the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array by 64 Kbytes. The SecSi Sector can be read, programmed, and erased as often as required. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 3, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sector/Sector Block Protection and Unprotection” section. Once the SecSi Sector is locked and verified, the system must wr ite the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 10 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent Am29PDS322D 23569A5 December 4, 2006 D A T A writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. S H E E T Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 10 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 15 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. December 4, 2006 23569A5 The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 10 shows the address and data requirements. This method is an alternative to that shown in Table 7, which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, Am29PDS322D 21 D A T A and the system may read any number of autoselect codes without reinitiating the command sequence. Table 10 shows the address and data requirements for the command sequence. To determine sector protection information, the system must write to the appropriate sector group address (SGA). Tables 3 and 5 show the address range associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 16-byte random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. Table 10 shows the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Note that a hardware reset (RESET#=V IL ) will reset the device to reading array data. Word Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 10 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed 22 S H E E T from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 10 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to reading array data. See Figure 4 for the unlock bypass algorithm. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams. Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T Start START 555h/AAh Set Unlock Bypass Mode 2AAh/55h Write Program Command Sequence Data Poll from System 555h/20h Embedded Program algorithm in progress XXXh/A0h Verify Data? Program Address/Program Data No Yes Data# Polling Device Increment Address Verify Byte? No Yes Increment Address No In Unlock Bypass Program Last Address? Yes Programming Completed Last Address ? Yes Note: See Table 10 for program command sequence. Figure 5. Programming Completed (BA) XXXh/90h XXXh/F0h Figure 4. No Unlock Bypass Algorithm December 4, 2006 23569A5 Reset Unlock Bypass Mode Program Operation cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 10 shows the address and data requirements for the chip erase command sequence. Am29PDS322D 23 D A T A When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 20 section for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 10 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. 24 S H E E T When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing sector. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing sector. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 20 section for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Note that unlock bypass programming is not allowed when the device is erase-suspended. Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to de te r m ine if a sector is ac tively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. START In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. Write Erase Command Sequence (Notes 1, 2) To resume the sector erase operation, the system must write the Erase Resume command. The address of the erase-suspended sector is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Data Poll to Erasing Bank from System No Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed Notes: 1. See Table 10 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 6. December 4, 2006 23569A5 Am29PDS322D Erase Operation 25 D A T A Table 10. Read (Note 6) Autoselect (Note 8) Reset (Note 7) Am29PDS322D Command Definitions Bus Cycles (Notes 2–5) Cycles Command Sequence (Note 1) S H E E T Addr Data 1 RA RD First Second Third Fourth Fifth Addr Data Addr Data Addr Data 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001 Device ID (Note 9) 6 555 AA 2AA 55 555 90 X01 227E SecSi Sector Factory Protect (Note 10) 4 555 AA 2AA 55 555 90 X03 80/00 Sector Group Protect Verify (Note 11) 4 555 AA 2AA 55 555 90 (SGA) X02 XX00/ XX01 Sixth Addr Data Addr Data X0E 2206 X0F 2201/ 2200 Enter SecSi Sector Region 3 555 AA 2AA 55 555 88 Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 555 AA 2AA 55 555 20 XXX A0 PA PD Unlock Bypass Reset (Note 13) 3 2 2 XXX 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Erase Suspend (Note 14) 1 BA B0 Erase Resume (Note 15) 1 BA 30 Unlock Bypass Program (Note 12) Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. Notes: 1. See Table 1 for description of bus operations. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SGA = Address of the sector group to be verified (in autoselect mode) or erased. Address bits A20–A12 uniquely select any sector. 9. The device ID must be read across the fourth, fifth and sixth cycles. The sixth cycle specifies 2201h for top boot or 2200h for bottom boot. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth and fifth cycle of the autoselect command sequence, all bus cycles are write cycles. 10. The data is 80h for factory locked and 00h for not factory locked. 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. 11. The data is 00h for an unprotected sector group and 01h for a protected sector group. 5. Unless otherwise noted, address bits A20–A12 are don’t cares in unlock sequence. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 6. No unlock or command cycles required when device is in read mode. 13. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information). 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t care. See the Autoselect Command Sequence section for more information. 26 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 11 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. invalid. Valid data on DQ0–DQ7 will appear on successive read cycles. Table 11 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data# Polling algorithm. Figure 22 in the AC Characteristics section shows the Data# Polling timing diagram. START DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read mode. Read DQ7–DQ0 Addr = VA DQ7 = Data? No No During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may be still DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 7. December 4, 2006 23569A5 Yes Am29PDS322D Data# Polling Algorithm 27 D A T A RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. S H E E T Table 11 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm. Figure 23 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 24 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or the device is in the erase-suspend-read mode. START Read DQ7–DQ0 Table 11 shows the outputs for RY/BY#. Read DQ7–DQ0 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. Toggle Bit = Toggle? Yes No If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program command sequence is written, then returns to reading array data. Read DQ7–DQ0 Twice Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. 28 DQ5 = 1? Yes After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). No Am29PDS322D Figure 8. Toggle Bit Algorithm 23569A5 December 4, 2006 D A T A DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. S H E E T the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 8). DQ5: Exceeded Timing Limits DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 11 to compare outputs for DQ2 and DQ6. DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 23 shows the toggle bit timing diagram. Figure 24 shows the differences between DQ2 and DQ6 in graphical form. Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previously in the erase-suspend-program mode). Reading Toggle Bits DQ6/DQ2 Refer to Figure 8 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor December 4, 2006 23569A5 The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 11 shows the status of DQ3 relative to the other status bits. Am29PDS322D 29 D A T A Table 11. Standard Mode Erase Suspend Mode Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program S H E E T Write Operation Status DQ7 (Note 2) DQ7# 0 DQ6 Toggle Toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle RY/BY# 0 0 1 No toggle 0 N/A Toggle 1 Data Data Data Data Data 1 DQ7# Toggle 0 N/A N/A 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 30 Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –65°C to +125°C Voltage with Respect to Ground 20 ns 20 ns +0.8 V –0.5 V –2.0 V VCC (Note 1) . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V 20 ns A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . . –0.5 V to +11 V WP#/ACC . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V Figure 9. Maximum Negative Overshoot Waveform Output Short Circuit Current (Note 3) . . . . . . 100 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. Dur ing voltage transitions, input or I/O pins may overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 9. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10. 2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot V SS to –2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +12.6 V which may overshoot to +12.0 V for periods up to 20 ns. 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 20 ns 20 ns Figure 10. Maximum Positive Overshoot Waveform Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C VCC Supply Voltages VCC for standard voltage range . . . . . . . 1.8 V to 2.2 V Operating ranges define those limits between which the functionality of the device is guaranteed. December 4, 2006 23569A5 Am29PDS322D 31 D A T A S H E E T DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ILIT A9 Input Load Current VCC = VCC max; A9, OE#, RESET# = 11 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ICC1 VCC Active Inter-Page Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, ICC2 VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH ICC3 VCC Standby Current (Note 2) ICC4 Typ Max Unit ±1.0 µA 35 µA ±1.0 µA 1 MHz 2.5 3 10 MHz 24 28 15 30 mA CE#, RESET# = VCC ± 0.3 V 0.2 5 µA VCC Reset Current (Note 2) WP#/ACC = VCC ± 0.3 V, RESET# = VSS ± 0.3 V 0.1 5 µA ICC5 VCC Automatic Sleep Mode Current (Notes 2, 4) CE# = VSS ± 0.3 V; RESET# = VCC ± 0.3 V, VIN = VCC ± 0.3 V or VSS ± 0.3 V 0.2 5 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2, 5) CE# = VIL, OE# = VIH 30 55 mA ICC7 VCC Active Read-While-Erase Current (Notes 1, 2, 5) CE# = VIL, OE# = VIH 30 55 mA ICC8 VCC Active Program-While-Erase-Suspended Current (Note 2) CE# = VIL, OE# = VIH 17 35 mA ICC9 VCC Active Intra-Page Read Current CE# = VIL, OE# = VIH 10 MHz 0.5 1 20 MHz 1 2 IACC WP#/ACC Accelerated Program Current VCC = VCCMax, WP#/ACC = VACCMax 12 20 mA VIL Input Low Voltage –0.5 VCC x 0.2 V VIH Input High Voltage 0.8 x VCC VCC + 0.3 V 8.5 12.5 V 9 11 V 0.1 V VACC Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration VCC = 1.8–2.2 V VID Voltage for Autoselect and Temporary VCC = 1.8–2.2 V Sector Unprotect VOL Output Low Voltage IOL = 100 µA, VCC = VCC min VOH Output High Voltage IOH = –100 µA VLKO Low VCC Lock-Out Voltage VCC – 0.1 1.2 mA mA V 1.5 V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. 3. 4. 5. 32 Maximum ICC specifications are tested with VCC = VCCmax. ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for 150 ns. Embedded algorithm (program or erase) is in progress (at 8 MHz). Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T DC CHARACTERISTICS Zero-Power Flash 25 Supply Current in mA 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 Time in ns Note: Addresses are switching at 1 MHz Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 18 2.0 V 15 Supply Current in mA 12 9 6 3 0 1 2 3 4 5 6 7 8 Frequency in MHz Note: T = 25 °C Figure 12. December 4, 2006 23569A5 Typical ICC1 vs. Frequency Am29PDS322D 33 D A T A S H E E T TEST CONDITIONS Table 12. Device Under Test Test Specifications Test Condition 10 12 Unit Output Load Capacitance, CL (including jig capacitance) 30 100 pF Input Rise and Fall Times CL 5 ns 0.0–2.0 V V Input timing measurement reference levels 1.0 V Output timing measurement reference levels 1.0 V Input Pulse Levels Note: Diodes are IN3064 or equivalent Figure 13. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) KS000010-PAL VCC Input 0.5 VCC Measurement Level 1.0 V Output 0.0 V Figure 14. 34 Input Waveforms and Measurement Levels Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T AC CHARACTERISTICS Read-Only Operations Parameter Speed Option JEDEC Std Description Test Setup tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tPRC Page Read Cycle tPACC Page Address to Output Delay 10 12 Unit Min 100 120 ns Max 100 120 ns Min 40 50 ns CE#, OE# = VIL Max 40 50 ns OE# = VIL Max 100 120 ns 35 50 ns CE#, OE# = VIL tELQV tCE Chip Enable to Output Delay tGLQV tOE Output Enable to Output Delay Max tEHQZ tDF Chip Enable to Output High Z (Notes 1, 3) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 0 ns Read Min 0 ns tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling Min 10 ns Notes: 1. Not 100% tested. 2. See Figure 13 and Table 12 for test specifications. 3. Measurements performed by placing a 50Ω termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF. tRC Addresses Stable Addresses tACC CE# tRH tRH tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V Figure 15. December 4, 2006 23569A5 Conventional Read Operation Timings Am29PDS322D 35 D A T A S H E E T AC CHARACTERISTICS Same page Addresses A20 to A2 A1 to A0 Ab Ac tRC tACC tPRC tPRC tOE tOEH WE# Output High-Z Figure 16. 36 Ad tCE CE# OE# Aa tDF tPACC tPACC tPACC tOH tOH tOH Da Db Dc tOH Dd Page Mode Read Timings Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description All Speed Options Unit tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 μs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 200 ns tRPD RESET# Low to Standby Mode Min 20 μs tRB RY/BY# Recovery Time Min 0 ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 17. December 4, 2006 23569A5 Reset Timings Am29PDS322D 37 D A T A S H E E T AC CHARACTERISTICS Erase and Program Operations Parameter Speed Option JEDEC Std Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tAH Address Hold Time Min 60 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 60 ns tWHDX tDH Data Hold Time Min 0 ns tCEPH Chip Enable High during toggle bit polling Min 20 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 60 ns tWHDL tWPH Write Pulse Width High Min 60 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWLAX 10 12 Unit 100 120 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 11 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 5 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns Program/Erase Valid to RY/BY# Delay Max 90 ns tBUSY Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 38 Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH PD A0h Data Status tBUSY DOUT tRB RY/BY# VCC tVCS Note: PA = program address, PD = program data, DOUT is the true data at the program address. Figure 18. Program Operation Timings VHH ACC VIL or VIH VIL or VIH tVHH Figure 19. December 4, 2006 23569A5 tVHH Accelerated Program Timing Diagram Am29PDS322D 39 D A T A S H E E T AC CHARACTERISTICS Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”). Figure 20. 40 Chip/Sector Erase Operation Timings Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T AC CHARACTERISTICS Addresses tWC tWC tRC Valid PA Valid RA tWC Valid PA Valid PA tAH tCPH tACC tCE CE# tCP tOE OE# tOEH tGHWL tWP WE# tDF tWPH tDS tOH tDH Valid Out Valid In Data Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle Figure 21. CE# Controlled Write Cycles Back-to-back Read/Write Cycle Timings tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ0–DQ6 Status Data Status Data True Valid Data High Z True Valid Data tBUSY RY/BY# Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 22. Data# Polling Timings (During Embedded Algorithms) December 4, 2006 23569A5 Am29PDS322D 41 D A T A S H E E T AC CHARACTERISTICS tAHT tAS Addresses tAHT tASO CE# tCEPH tOEH WE# tOEPH OE# tDH DQ6/DQ2 tOE Valid Status Valid Status Valid Status (first read) (second read) (stops toggling) Valid Data Valid Data RY/BY# Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle Figure 23. Enter Embedded Erasing WE# Erase Suspend Erase Toggle Bit Timings (During Embedded Algorithms) Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 24. DQ2 vs. DQ6 42 Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description All Speed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 500 ns tRSP RESET# Setup Time for Temporary Sector/Sector Block Unprotect Min 4 µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector/Sector Block Unprotect Min 4 µs Note: Not 100% tested. VID RESET# VID VSS, VIL, or VIH VSS, VIL, or VIH tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRRB tRSP RY/BY# Figure 25. December 4, 2006 23569A5 Temporary Sector Group Unprotect Timing Diagram Am29PDS322D 43 D A T A S H E E T AC CHARACTERISTICS VID VIH RESET# SA, A6, A1, A0 Valid* Valid* Sector/Sector Block Protect or Unprotect Data 60h 60h Valid* Verify 40h Status Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 ms 1 µs CE# WE# OE# * For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 26. 44 Sector Group Protect and Unprotect Timing Diagram Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter Speed Option JEDEC Std Description 10 12 Unit tAVAV tWC Write Cycle Time (Note 1) Min 100 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 60 ns tDVEH tDS Data Setup Time Min 60 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 60 ns tEHEL tCPH CE# Pulse Width High Min 60 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 16 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 5 5 1 µs sec Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. December 4, 2006 23569A5 Am29PDS322D 45 D A T A S H E E T AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tWHWH1 or 2 tCP CE# tWS tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 27. 46 Alternate CE# Controlled Write (Erase/Program) Operation Timings Am29PDS322D 23569A5 December 4, 2006 D A T A S H E E T ERASE AND PROGRAMMING PERFORMANCE Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 1 10 sec Chip Erase Time 93 Excludes 00h programming prior to erasure (Note 4) Word Program Time 16 Accelerated Word Program Time 5 Chip Program Time (Note 3) 20 sec 360 µs Excludes system level overhead (Note 5) µs 100 sec Notes: 1. Typical program and erase times assume the following conditions: 25°C, 2.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V –100 mA +100 mA VCC Current Note: Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time. DATA RETENTION Parameter Description Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time December 4, 2006 23569A5 Am29PDS322D 47 D A T A S H E E T PHYSICAL DIMENSIONS FBD048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 12 mm package Dwg rev AF; 1/2000 xFBD 048 6.00 mm x 12.00 mm PACKAGE 1.20 0.20 0.94 0.84 12.00 BSC 6.00 BSC 5.60 BSC 4.00 BSC 8 6 0.25 48 0.30 0.35 0.80 BSC 0.40 BSC * For reference only. BSC is an ANSI standard for Basic Space Centering. 48 Am29PDS322D 23569A5 December 4, 2006 D A T A REVISION SUMMARY Revision A (December 4, 2000) S H E E T Erase Suspend/Erase Resume Commands Revision A+1 (February 16, 2001) Noted in the third paragraph that unlock bypass programming is not allowed when the device is erase suspended. Ordering Information Revision A+4 (August 7, 2002) Added “U” designator to package marking. Deleted burn-in option. Distinctive Characteristics Revision A+2 (August 31, 2001) Removed “Supports Common Flash Memory Interface (CFI)) Autoselect Command Sequence Table 10. Am29PDS322D Command Definitions Modified section to point to appropriate tables for autoselect functions. Changed the Command Cycle Device ID cycle from 6 to 4. Revision A+3 (February 18, 2002) Revision A5 (December 4, 2006) Global Global Removed “Advance Information” designation from data sheet. Removed Advance Information designation from document (inadvertently restored in Revision A+4). Initial release. AC Characteristics Erase and Program Operations table: Changed tBUSY to a maximum specification. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2000–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. December 4, 2006 23569A5 Am29PDS322D 49