AD AD7819 2.7 v to 5.5 v, 200 ksps 8-bit sampling adc Datasheet

a
FEATURES
8-Bit ADC with 4.5 s Conversion Time
On-Chip Track and Hold
Operating Supply Range: 2.7 V to 5.5 V
Specifications at 2.7 V – 3.6 V and 5 V 10%
8-Bit Parallel Interface
8-Bit Read
Power Performance
Normal Operation
10.5 mW, VDD = 3 V
Automatic Power-Down
57.75 W @ 1 kSPS, VDD = 3 V
Analog Input Range: 0 V to V REF
Reference Input Range: 1.2 V to VDD
GENERAL DESCRIPTION
The AD7819 is a high speed, microprocessor-compatible, 8-bit
analog-to-digital converter with a maximum throughput of
200 kSPS. The converter operates off a single 2.7 V to 5.5 V
supply and contains a 4.5 µs successive approximation A/D
converter, track/hold circuitry, on-chip clock oscillator and 8-bit
wide parallel interface. The parallel interface is designed to
allow easy interfacing to microprocessors and DSPs. Using only
address decoding logic the AD7819 is easily mapped into the
microprocessor address space.
When used in its power-down mode, the AD7819 automatically
powers down at the end of a conversion and powers up at the
start of a new conversion. This feature significantly reduces the
power consumption of the part at lower throughput rates. The
AD7819 can also operate in a high speed mode where the part is
not powered down between conversions. In this mode of operation the part is capable of providing 200 kSPS throughput.
The part is available in a small, 16-lead 0.3" wide, plastic dualin-line package (DIP); in a 16-lead, 0.15" wide, narrow body
small outline IC (SOIC) and in a 16-lead, narrow body, thin
shrink small outline package (TSSOP).
2.7 V to 5.5 V, 200 kSPS
8-Bit Sampling ADC
AD7819
FUNCTIONAL BLOCK DIAGRAM
VDD
AGND
VREF
AD7819
CHARGE
REDISTRIBUTION
DAC
DB7
THREESTATE
DRIVERS
DB0
CLOCK
OSC
VIN
T/H
COMP
CONTROL
LOGIC
BUSY CS
RD CONVST
PRODUCT HIGHLIGHTS
1. Low Power, Single Supply Operation
The AD7819 operates from a single 2.7 V to 5.5 V supply
and typically consumes only 10.5 mW of power. The power
dissipation can be significantly reduced at lower throughput rates by using the automatic power-down mode.
2. Automatic Power-Down
The automatic power-down mode, whereby the AD7819
goes into power-down mode at the end of a conversion and
powers up before the next conversion, means the AD7819
is ideal for battery powered applications; e.g., 57.75 µW
@ 1 kSPS. (See Power vs. Throughput Rate section.)
3. Parallel Interface
An easy to use 8-bit wide parallel interface allows interfacing
to most popular microprocessors and DSPs with minimal
external circuitry.
4. Dynamic Specifications for DSP Users
In addition to the traditional ADC specifications, the AD7819
is specified for ac parameters, including signal-to-noise ratio
and distortion.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
(GND = 0 V, VREF = VDD = 3 V 10% to 5 V 10%. All specifications –40C
AD7819–SPECIFICATIONS1 to +125C unless otherwise noted.)
Parameter
Y Version
Unit
48
–70
–70
dB min
dB typ
dB typ
–77
–77
dB typ
dB typ
8
Bits
8
± 0.5
± 0.5
±1
± 0.5
± 0.5
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
0
VREF
±1
15
V min
V max
µA max
pF mx
Input Leakage Current
Input Capacitance
1.2
VDD
±1
20
V min
V max
µA max
pF max
LOGIC INPUTS2
VINH, Input High Voltage
VINL, Input Low Voltage
Input Current, IIN
Input Capacitance, CIN
2.0
0.4
±1
8
V min
V max
µA max
pF max
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
High Impedance Leakage Current
High Impedance Capacitance
2.4
0.4
±1
15
V min
V max
µA max
pF max
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time1
4.5
100
µs max
ns max
2.7–5.5
Volts
3.5
1
mA max
µA max
17.5
5
mW max
µW max
57.75
577.5
2.89
µW max
µW max
mW max
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio1
Total Harmonic Distortion (THD)1
Peak Harmonic or Spurious Noise1
Intermodulation Distortion2
2nd Order Terms
3rd Order Terms
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Relative Accuracy1
Differential Nonlinearity (DNL)1
Total Unadjusted Error1
Gain Error1
Offset Error1
ANALOG INPUT
Input Voltage Range
Input Leakage Current2
Input Capacitance2
REFERENCE INPUTS2
VREF Input Voltage Range
POWER SUPPLY
VDD
IDD
Normal Operation
Power-Down
Power Dissipation
Normal Operation
Power-Down
Auto Power-Down (Mode 2)
1 kSPS Throughput
10 kSPS Throughput
50 kSPS Throughput
Test Conditions/Comments
fIN = 30 kHz, fSAMPLE = 136 kHz
fa = 29.1 kHz; fb = 29.8 kHz
(0.8 V max, VDD = 5 V)
Typically 10 nA, VIN = 0 V to VDD
ISOURCE = 200 µA
ISINK = 200 µA
See DC Acquisition Section
For Specified Performance
Digital Inputs = 0 V or VDD
VDD = 5 V
VDD = 5 V
VDD = 3 V
NOTES
1
See Terminology section.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
–2–
REV. B
AD7819
TIMING CHARACTERISTICS1, 2 (–40C to +125C, unless otherwise noted)
Parameter
VDD = 3 V 10%
VDD = 5 V 10%
Unit
Conditions/Comments
tPOWER-UP
1.5
4.5
30
30
0
0
10
10
100
1.5
4.5
30
30
0
0
10
10
100
µs (max)
µs (max)
ns (min)
ns (max)
ns (min)
ns (min)
ns (max)
ns (max)
ns (min)
Power-Up Time of AD7819 after Rising Edge of CONVST.
Conversion Time.
CONVST Pulsewidth.
CONVST Falling Edge to BUSY Rising Edge Delay.
CS to RD Setup Time.
CS Hold Time after RD High.
Data Access Time after RD Low.
Bus Relinquish Time after RD High.
Data Bus Relinquish to Falling Edge of CONVST Delay.
t1
t2
t3
t4
t5
t 63
t73, 4
t 83
NOTES
1
Sample tested to ensure compliance.
2
See Figures 12, 13 and 14.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ± 10% and
0.4 V or 2 V for V DD = 3 V ± 10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the Timing Characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to DGND
(CONVST, RD, CS) . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Digital Output Voltage to DGND
(BUSY, DB0–DB7) . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Analog Input . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
200A
TO
OUTPUT
PIN
IOL
1.6V
CL
50pF
200A
IOH
Figure 1. Load Circuit for Digital Output Timing
Specifications
ORDERING GUIDE
Model
Linearity
Error
Package
(LSB)
Description
AD7819YN ± 1 LSB
AD7819YR
± 1 LSB
AD7819YRU ± 1 LSB
Package
Option
Plastic DIP
N-16
Small Outline IC
R-16A
Thin Shrink Small Outline RU-16
(TSSOP)
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7819 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–3–
WARNING!
ESD SENSITIVE DEVICE
AD7819
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Description
1
2
3
4
VREF
VIN
GND
CONVST
5
6
CS
RD
7
8–15
16
BUSY
DB0–DB7
VDD
Reference Input, 1.2 V to VDD.
Analog Input, 0 V to VREF.
Analog and Digital Ground.
Convert Start. A low-to-high transition on this pin initiates a 1.5 µs pulse on an internally generated
CONVST signal. A high-to-low transition on this line initiates the conversion process if the internal
CONVST signal is low. Depending on the signal on this pin at the end of a conversion, the AD7819
automatically powers down.
Chip Select. This is a logic input. CS is used in conjunction with RD to enable outputs.
Read Pin. This is a logic input. When CS is low and RD goes low, the DB7–DB0 leave their high
impedance state and data is driven onto the data bus.
ADC Busy Signal. This is a logic output. This signal goes logic high during the conversion process.
Data Bit 0 to 7. These outputs are three-state TTL-compatible.
Positive power supply voltage, 2.7 V to 5.5 V.
PIN CONFIGURATION
DIP/SOIC
VREF 1
16 VDD
VIN 2
15 DB7
GND 3
CONVST 4
14 DB6
AD7819
13 DB5
TOP VIEW
12 DB4
(Not to Scale)
11 DB3
RD 6
CS 5
BUSY 7
10 DB2
DB0 8
9 DB1
–4–
REV. B
AD7819
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7819 it is defined as:
2
2
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Thus for an 8-bit converter, this is 50 dB.
THD (dB) = 20 log
The AD7819 is tested using the CCIF standard, where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of
the fundamental expressed in dBs.
2
2
2
V2 + V 3 + V 4 + V 5 + V6
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (0000 . . . 000)
to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the difference in Offset Error between any two channels.
Peak Harmonic or Spurious Noise
Gain Error
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
This is the deviation of the last code transition (1111 . . . 110)
to (1111 . . . 111) from the ideal, i.e., VREF – 1 LSB, after the
offset error has been adjusted out.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
REV. B
Gain Error Match
This is the difference in Gain Error between any two channels.
Track/Hold Acquisition Time
Track/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
± 1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected VIN input of the AD7819. It means that the user
must wait for the duration of the track/hold acquisition time
after the end of conversion or after a step input change to VIN
before starting another conversion, to ensure that the part
operates to specification.
–5–
AD7819
SUPPLY
2.7V TO 5.5V
CIRCUIT DESCRIPTION
Converter Operation
The AD7819 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to VDD. Figures 2 and 3 below show simplified schematics of the ADC.
Figure 2 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A, the comparator is held in a
balanced condition and the sampling capacitor acquires the signal on VIN+.
A
VIN
B
AGND
ACQUISITION
PHASE
SW2
CLOCK
OSC
AGND
Figure 5 shows an equivalent circuit of the analog input structure of the AD7819. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
20 mA is the maximum current these diodes can conduct without causing irreversible damage to the part. The capacitor C2
is typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is a lumped component made up of
the on resistance of a multiplexer and a switch. This resistor is
typically about 125 Ω. The capacitor C1 is the ADC sampling
capacitor and has a capacitance of 3.5 pF.
VDD
D1
R1
125
C1
3.5pF
VDD/3
VIN
C2
4pF
D2
CONVERT PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED
CONTROL
LOGIC
SW2
CONVERSION
PHASE
CS
Analog Input
SAMPLING
CAPACITOR
B
C/P
RD
Figure 4. Typical Connection Diagram
CHARGE
RESTRIBUTION
DAC
SW1
BUSY
CONVST
When the ADC starts a conversion, see Figure 3, SW2 will open
and SW1 will move to Position B causing the comparator to
become unbalanced. The Control Logic and the Charge Redistribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebalanced the conversion is complete. The Control Logic generates
the ADC output code. Figure 7 shows the ADC transfer function.
VIN
VIN
GND
Figure 2. ADC Track Phase
A
AD7819
0V TO VREF
INPUT
COMPARATOR
VDD/3
PARALLEL
INTERFACE
VREF
DB0-DB7
CONTROL
LOGIC
SW1
0.1F
VDD
CHARGE
RESTRIBUTION
DAC
SAMPLING
CAPACITOR
10F
Figure 5. Equivalent Analog Input Circuit
COMPARATOR
VDD/3
DC Acquisition Time
CLOCK
OSC
The ADC starts a new acquisition phase at the end of a conversion and ends on the falling edge of the CONVST signal. At the
end of a conversion there is a settling time associated with the
sampling circuit. This settling time lasts approximately 100 ns.
The analog signal on VIN is also being acquired during this
settling time. The minimum acquisition time needed is approximately 100 ns. Figure 6 shows the equivalent charging circuit
for the sampling capacitor when the ADC is in its acquisition
phase. R2 represents the source impedance of a buffer amplifier
or resistive network, R1 is an internal multiplexer resistance and
C1 is the sampling capacitor.
Figure 3. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 4 shows a typical connection diagram for the AD7819. The
parallel interface is implemented using an 8-bit data bus, the
falling edge of CONVST brings the BUSY signal high and at
the end of conversion, the falling edge of BUSY is used to
initiate an ISR on a microprocessor. (See Parallel Interface
section for more details.) VREF is connected to a well decoupled
VDD pin to provide an analog input range of 0 V to VDD. When
VDD is first connected the AD7819 powers up in a low current
mode, i.e., power-down. A rising edge on the CONVST input
will cause the part to power up. (See Power-Up Times section.)
If power consumption is of concern, the automatic power-down
at the end of a conversion should be used to improve power
performance. See Power vs. Throughput Rate section of the
data sheet.
R2
VIN
R1
125
C1
3.5pF
Figure 6. Equivalent Sampling Circuit
–6–
REV. B
AD7819
During the acquisition phase the sampling capacitor must be
charged to within a 1/2 LSB of its final value. The time it takes
to charge the sampling capacitor (TCHARGE) is given by the following formula:
When operating in Mode 2, the ADC is powered down at the
end of each conversion and powered up again before the next
conversion is initiated. (See Figure 8.)
MODE 1
TCHARGE = 6.2 × (R2 + 125 Ω) × 3.5 pF
VDD
For small values of source impedance, the settling time associated with the sampling circuit (100 ns) is, in effect, the acquisition
time of the ADC. For example, with a source impedance (R2)
of 10 Ω, the charge time for the sampling capacitor is approximately 3 ns. The charge time becomes significant for source
impedances of 2 kΩ and greater.
EXT CONVST
t POWER-UP
1.5s
INT CONVST
AC Acquisition Time
MODE 2
In ac applications it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of the
ADC. Large values of source impedance will cause the THD to
degrade at high throughput rates.
VDD
EXT CONVST
t POWER-UP
t POWER-UP
1.5s
1.5s
INT CONVST
ADC TRANSFER FUNCTION
The output coding of the AD7819 is straight binary. The designed
code transitions occur at successive integer LSB values (i.e.,
1 LSB, 2 LSBs, etc.). The LSB size is = VREF/256. The ideal
transfer characteristic for the AD7819 is shown in Figure 7 below.
Figure 8. Power-Up Times
POWER VS. THROUGHPUT RATE
ADC CODE
By operating the AD7819 in Mode 2, the average power consumption of the AD7819 decreases at lower throughput rates.
111...111
111...110
•
•
•
111...000
•
•
011...111
•
•
•
000...010
000...001
000...000
1LSB = VREF/256
0V 1LSB
ANALOG INPUT
+VREF –1LSB
Figure 9 shows how the Automatic Power-Down is implemented
using the external CONVST signal to achieve the optimum
power performance for the AD7819. The AD7819 is operated
in Mode 2 and the duration of the external CONVST pulse is
set to be equal to or less than the power-up time of the device.
As the throughput rate is reduced, the device remains in its powerdown state longer and the average power consumption over time
drops accordingly.
Figure 7. Transfer Characteristic
EXT CONVST
t POWER-UP
1.5s t CONVERT
POWER-UP TIMES
The AD7819 has a 1.5 µs power-up time. When VDD is first connected, the AD7819 is in a low current mode of operation. In
order to carry out a conversion the AD7819 must first be powered up. The ADC is powered up by a rising edge on an internally
generated CONVST signal, which occurs as a result of a rising
edge on the external CONVST pin. The rising edge of the external
CONVST signal initiates a 1.5 µs pulse on the internal CONVST
signal. This pulse is present to ensure the part has enough time
to power-up before a conversion is initiated, as a conversion is
initiated on the falling edge of gated CONVST. See Timing and
Control section. Care must be taken to ensure that the CONVST
pin of the AD7819 is logic low when VDD is first applied.
REV. B
4.5s
POWER-DOWN
INT CONVST
tCYCLE
100s @ 10kSPS
Figure 9. Automatic Power-Down
If, for example, the AD7819 is operated in a continuous sampling mode with a throughput rate of 10 kSPS, the power
consumption is calculated as follows. The power dissipation
during normal operation is 10.5 mW, VDD = 3 V. If the powerup time is 1.5 µs and the conversion time is 4.5 µs, the AD7819
can be said to dissipate 10.5 mW for 6 µs (worst case) during
each conversion cycle. If the throughput rate is 10 kSPS, the
cycle time is then 100 µs and the average power dissipated during each cycle is (6/100) × (10.5 mW) = 630 µW.
–7–
AD7819
external CONVST and this internal CONVST are input to an
OR gate. The resultant signal has the duration of the longer of
the two input signals. Once a conversion has been initiated, the
BUSY signal goes high to indicate a conversion is in progress. At
the end of conversion the sampling circuit returns to its tracking mode. The end of conversion is indicated by the BUSY
signal going low. This signal may be used to initiate an ISR on a
microprocessor. At this point the conversion result is latched
into the output register where it may be read. The AD7819 has
an 8-bit wide parallel interface. The state of the external CONVST
signal at the end of conversion also establishes the mode of
operation of the AD7819.
Typical Performance Characteristics
POWER – mW
10
1
0.1
Mode 1 Operation (High Speed Sampling)
If the external CONVST is logic high when BUSY goes low, the
part is said to be in Mode 1 operation. While operating in Mode
1 the AD7819 will not power down between conversions. The
AD7819 should be operated in Mode 1 for high speed sampling applications, i.e., throughputs greater than 100 kSPS.
Figure 13 shows the timing for Mode 1 operation. From this
diagram one can see that a minimum delay of the sum of the
conversion time and read time must be left between two successive falling edges of the external CONVST. This is to ensure that
a conversion is not initiated during a read.
0.01
0
5
10
15
20
25
30
35
THROUGHPUT – kSPS
40
45
50
Figure 10. Power vs. Throughput
0
AD7819
2048 POINT FFT
SAMPLING 136.054kHz
FIN = 29.961kHz
–10
–20
Mode 2 Operation (Automatic Power-Down)
–30
At slower throughput rates the AD7819 may be powered down
between conversion to give a superior power performance.
This is Mode 2 Operation and it is achieved by bringing the
CONVST signal logic low before the falling edge of BUSY. Figure 14 shows the timing for Mode 2 Operation. The falling edge
of the external CONVST signal may occur before or after the
falling edge of the internal CONVST signal, but it is the later
occurring falling edge of both that controls when the first conversion will take place. If the falling edge of the external CONVST
occurs after that of the internal CONVST, it means that the
moment of the first conversion is controlled exactly, regardless
of any jitter associated with the internal CONVST signal. The
parallel interface is still fully operational while the AD7819 is
powered down. The AD7819 is powered up again on the rising
edge of the CONVST signal. The gated CONVST pulse will
now remain high long enough for the AD7819 to fully power
up, which takes about 1.5 µs. This is ensured by the internal
CONVST signal, which will remain high for 1.5 µs.
dBs
–40
–50
–60
–70
–80
–90
–100
0
7
13
20
27
33
40
47
FREQUENCY – kHz
53
60
66
Figure 11. SNR
TIMING AND CONTROL
The AD7819 has only one input for timing and control, i.e.,
the CONVST (convert start signal). The rising edge of this
CONVST signal initiates a 1.5 µs pulse on an internally generated CONVST signal. This pulse is present to ensure the part
has enough time to power up before a conversion is initiated. If
the external CONVST signal is low, the falling edge of the internal CONVST signal will cause the sampling circuit to go into
hold mode and initiate a conversion. If, however, the external
CONVST signal is high when the internal CONVST goes low,
it is upon the falling edge of the external CONVST signal that
the sampling circuitry will go into hold mode and initiate a
conversion. The use of the internally generated 1.5 µs pulse as
previously described can be likened to the configuration shown
in Figure 12. The application of a CONVST signal at the
CONVST pin triggers the generation of a 1.5 µs pulse. Both the
CONVST
(PIN 4)
EXT
GATED
INT
1.5s
Figure 12.
–8–
REV. B
AD7819
t1
t2
EXT CONVST
t3
tPOWER-UP
INT CONVST
BUSY
CS/RD
DB7–DB0
8 MSBs
Figure 13. Mode 1 Operation
EXT CONVST
tPOWER-UP
t1
INT CONVST
t3
BUSY
CS/RD
DB7–DB0
8 MSBs
Figure 14. Mode 2 Operation
PARALLEL INTERFACE
BUSY goes logic high. Care must be taken to ensure that a read
operation does not occur while BUSY is high. Data read from
the AD7819 while BUSY is high will be invalid. For optimum
performance the read operation should end at least 100 ns (t8)
prior to the falling edge of the next CONVST.
The parallel interface of the AD7819 is eight bits wide. The output data buffers are activated when both CS and RD are logic
low. At this point the contents of the data register are placed on
the 8-bit data bus. Figure 15 shows the timing diagram for the parallel port. The Parallel Interface of the AD7819 is reset when
CONVST
t3
t2
t8
BUSY
t1
CS
t4
t5
RD
t7
t6
DB7–DB0
8 MSBs
Figure 15. Parallel Port Timing
REV. B
–9–
AD7819
MICROPROCESSOR INTERFACING
The parallel port on the AD7819 allows the device to be interfaced to a range of many different microcontrollers. This section
explains how to interface the AD7819 with some of the more
common microcontroller parallel interface protocols.
PSP0–PSP7
PIC16C6x/7x*
AD7819 to 8051
Figure 16 shows a parallel interface between the AD7819 and
the 8051 microcontroller. The BUSY signal on the AD7819 provides an interrupt request to the 8051 when a conversion begins.
Port 0 of the 8051 may serve as an input or output port, or as in
this case when used together, may be used as a bidirectional
low-order address and data bus. The address latch enable output of the 8051 is used to latch the low byte of the address
during accesses to the device, while the high-order address byte
is supplied from Port 2. Port 2 latches remain stable when the
AD7819 is addressed, as they do not have to be turned around
(set to 1) for data input as is the case for Port 0.
DB0–DB7
AD7819*
CS
CS
RD
RD
INT
BUSY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. Interfacing to the PIC16C6x/7x
AD7819 to ADSP-21xx
Figure 18 shows a parallel interface between the AD7819 and
the ADSP-21xx series of DSPs. As before, the BUSY signal on
the AD7819 provides an interrupt request to the DSP when a
conversion begins.
DB0–DB7
8051*
AD0–AD7
LATCH
ALE
AD7819*
DECODER
D0–D7
DB0–DB7
A13–A0
CS
AD7819*
ADSP-21xx*
A8–A15
RD
RD
INT
BUSY
DMS
RD
*ADDITIONAL PINS OMITTED FOR CLARITY
IRQ
Figure 16. Interfacing to the 8051
AD7819 to PIC16C6x/7x
EN
ADDRESS
DECODE
LOGIC
CS
RD
BUSY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17 shows a parallel interface between the AD7819 and the
PIC16C64/65/74. The BUSY signal on the AD7819 provides
an interrupt request to the microcontroller when a conversion
begins. Of the PIC16C6x/7x range of microcontrollers, only
the PIC16C64/65/74 can provide the option of a parallel slave
port. Port D of the microcontroller will operate as an 8-bit
wide parallel slave port when control bit PSPMODE in the
TRISE register is set. Setting PSPMODE enables the port pin
RE0 to be the RD output and RE2 to be the CS output. For
this functionality, the corresponding data direction bits of the
TRISE register must be configured as outputs (reset to 0). See
user PIC16/17 Microcontroller User Manual.
–10–
Figure 18. Interfacing to the ADSP-21xx
REV. B
AD7819
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.840 (21.33)
0.745 (18.93)
16
9
1
8
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.100
(2.54)
BSC
0.130
(3.30)
MIN
0.070 (1.77) SEATING
0.045 (1.15) PLANE
C01318–0–10/00 (rev. B)
16-Lead Plastic DIP
(N-16)
0.015 (0.381)
0.008 (0.204)
16-Lead Small Outline Package
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
16
9
0.1574 (4.00)
0.1497 (3.80) 1
8
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
0.0500
SEATING
(1.27)
PLANE
BSC
0.2550 (6.20)
0.2284 (5.80)
0.0196 (0.50)
x 45°
0.0099 (0.25)
8°
0.0099 (0.25) 0° 0.0500 (1.27)
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
16-Lead Thin Shrink Small Outline Package
(RU-16)
0.201 (5.10)
0.193 (4.90)
8
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0256
SEATING
(0.65)
PLANE
BSC
REV. B
0.0118 (0.30)
0.0075 (0.19)
0.0433
(1.10)
MAX
8°
0.0079 (0.20) 0°
0.0035 (0.090)
–11–
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
1
0.246 (6.25)
9
0.256 (6.50)
0.169 (4.30)
0.177 (4.50)
16