E-CMOS EC25C32NM1GR 32kbits spi serial eeprom Datasheet

32Kbits SPI Serial EEPROM
EC25C32
General Description
The EC25C32 is an industrial standard electrically
In order to refrain the state machine from entering into a
erasable programmable read only
memory
Wrong state during power-up sequence or a power
standard Serial
toggle off-on condition, a power on reset circuit is
Peripheral Interface (SPI) for communications.
implemented. During power-up, the device does not
The EC25C32 contains a memory array of 32K
respond to any instructions until the supply voltage
bits (4,096x 8), which is organized in 32 bytes per
(VCC)has reached an acceptable stable level above the
page.
reset threshold voltage. Once VCC passes the power on
This EEPROM operates in a wide voltage range
reset threshold, the device is reset and enters into
from 1.7V to 5.5V,which fits most application.
Standby mode. This should also avoid any inadvertent
The device
provides low-power operations and
Write operations during power-up stage. During power-
low standby current. The product is offered in
down process, the device will enter into standby mode,
Lead-free, RoHS, halogen free or Green package.
once VCC drops below the power on reset threshold
The available package types are 8-pin SOP,
voltage. In addition, the device will be in standby mode
TSSOP and UDFN.
after receiving the Stop command, provided that no
The functionalities of the EC25C32 are optimized
internal write operation is in progress. Nevertheless,
for
it is illegal to send a command unless the VCC is within its
(EEPROM) Product that utilizes
most
applications,
such
as
consumer
electronics,wireless,telecommunication, industrial,
operating level.
medical ,instrumentation, commercial and others,
where low-power and
low-voltage are vital. This
product has a compatible SPI
interface: Chip-
Select ( CS ), Serial Data In (SI), Serial Data Out
(SO) and Serial Clock (SCK)
for
communication. Furthermore,
a Hold feature
via HOLD pin
allows the device
high-speed
entering into
a suspended state whenever necessary and
resuming the communication without re-initializing
the serial sequence. A
Status Register
facilitates a flexible write protection mechanism
and device Status monitoring.
E-CMOS Corp. (www.ecmos.com.tw)
Page 1 of 16
5F09N-Rev.F001
32Kbits SPI Serial EEPROM
EC25C32
Features
Serial Peripheral Interface (SPI) Compatible
 Block Write Protection
—Supports Mode 0 (0,0) and Mode 3 (1,1)
— Protect 1/4, 1/2, or Entire Array
Wide-voltage Operation
 Self timed write cycle: 5 ms (max.)
—VCC = 1.7V to 5.5V
 Additional Write lockable Page (Identification
Low power CMOS
page)
 High-reliability
—Standby current: ≤1 μA (1.7V)
— Endurance: 1 million cycles
—Operating current: ≤1 mA (1.7V)
Operating frequency: 20 MHz (5.5V)
— Data retention: 100 years
Memory organization: 32Kb (4,096 x 8)
 Industrial temperature grade
Byte and Page write (up to 32 bytes)
 Packages (8-pin): SOP, TSSOP and DFN
—Partial page write allowed
 Lead-free, RoHS, Halogen free, Green
Ordering Information & Marking Information
EC25C XXN
XX X X
R：Tape & Reel
Device Function
32＝32Kbit
(4,096×8)
Package type
Part Number
SOP-8
EC25C32NM1GR
TSSOP-8
EC25C32NE1GR
DFN-8
EC25C32NF2GR
E-CMOS Corp. (www.ecmos.com.tw)
G：Green
M1：SOP-8
E1：TSSOP-8
F2：DFN-8
Marking
25C32
LLLLL
YYWWT
25C32
LLLLL
YYWWT
5C32
LLLT
Marking Information
25C32：Part No
LLLLL：the last five numbers of wafer lot number
YYWW：Date Code.
T ：Internal tracking Code
5C32：Part No
LLL：the last three numbers of wafer lot number
T：Internal tracking Code
Page 2 of 16
5F09N-Rev.F001
32Kbits SPI Serial EEPROM
EC25C32
Functional Block Diagram
Serial Interface Description
Master：The device that provides a clock signal.
Slave：EC25C32.
Transmitter/Receiver：The EC25C32 has both data input (SI) and data output (SO).
MSB：MSB (Most Significant Bit) is the first bit being transmitted or received.
Op-Code：Operational instruction code typically sent to the EC25C32 is the first byte of information
transmitted after
is Low. If the Op-Code is a valid instruction as listed in Table 3, then it will be
decoded appropriately. It is prohibited to send an invalid Op-Code.
E-CMOS Corp. (www.ecmos.com.tw)
Page 3 of 16
5F09N-Rev.F001
EC25C32
32Kbits SPI Serial EEPROM
Pin Configuration
(SOP-8/TSSOP-8)
(DFN-8)
Pin Definition
Pin No.
Pin Name
I/O
1
CS
SO
I
Chip Select
O
Serial Data Output
WP
GND
I
Write Protect Input
4
-
Ground
5
SI
I
Serial Data Input
6
SCK
I
Serial Clock
7
HOLD
VCC
I
Hold function
-
Supply Voltage
2
3
8
Definition
Pin Descriptions
Chip Select (
)
The CS pin is used to enable or disable the device. Upon power-up, CS must follow the supply voltage. When
the device is ready for instruction input, this signal requires a High-to-Low transition. Once CS is stable at Low,
the device is enabled. Then the master and slave can communicate among each other through SCK, SI, and
SO pins. Upon completion of transmission, CS must be driven to High in order to stop the operation or start
the internal write operation. And the device will enter into standby mode, unless an internal write operation is in
progress. During this mode, SO becomes high impedance.
Serial Clock (SCK)
Under the SPI modes (0,0) and (1,1),this clock signal provides synchronization between the master and
EC25C32.Typically,Op-Codes,addresses and data are latched from SI at the rising edge of SCK, while data
from SO are clocked out at the falling edge of SCK.
Serial Data Input (SI)
Data Input pin.
Serial Data Output(SO)
Data output pin.
Write Protect (
)
This active Low input signal is utilized to initiate Hardware Write Protection mode. This mode prevents the
Block Protection bits and the WPEN bit in the Status Register from being modified. To activate the Hardware
Write Protection, WP must be Low simultaneously when WPEN is set to 1.
Hold (
)
This feature is used to suspend the device in the middle of a serial sequence and temporarily ignore further
communication on the bus (SI,SO,SCK).The HOLD signal transitions must occur only when SCK is Low and be
held stable during SCK transitions. Connecting HOLD to High disables this feature. Figure.8 shows Hold timing.
E-CMOS Corp. (www.ecmos.com.tw)
Page 4 of 16
5F09N-Rev.F001
EC25C32
32Kbits SPI Serial EEPROM
Device Operation
Status Register
The Status Register accessible by the user consists of 8-bits data for write protection control and write status.
It Hardware Write Protection is enabled or WEN is set to 0. If neither is true, it can be modified by a valid
instruction.
Table 1: Status Register
Bit
Symbol
Name
Description
When RDY = 0, device is ready for an instruction.
0
RDY
Ready
When RDY = 1, device is busy.
As busy, device only accepts Read Status Register command.
This represents the write protection status of the device.
When WEN = 0, Status Register and entire array cannot be modified, regardless
1
WEN
Write Enable
the setting of WPEN,WP pin or block protection.
Write Enable command (WREN) can be used to set WEN to 1.
Upon power-up stage, WEN is reset to 0.
2
BP0
Block Protect Bit
3
BP1
Block Protect Bit
4
X
Don’t Care
Values can be either 0 or 1, but are not retained. Mostly always 0, except during
5
X
Don’t Care
write operation.
6
X
Don’t Care
Despite of the status on WPEN, WP or WEN, BP0 and BP1 configure any
combinations of the four blocks being protected (Table2).
They are non-volatile memory and programmed to 0 by factory.
This bit can be utilized to enable Hardware Write Protection, together with
WP pin. If enabled, Status Register becomes read-only. However, the memory
7
WPEN
Write Protect Enable
array is not protected by this mode. Hardware Write Protection requires the
setting of WP = 0 and WPEN = 1. Otherwise, it is disabled.
WPEN cannot be altered from 1 to 0 if WP is already set to Low. (Table 4 for
write protection)
Note: During internal write cycles, bits 0 to 7 are temporarily 1's.
Table 2: Block Protection by BP0 and BP1
Level
Status Register Bits
Array Addresses Protected
BP1
BP0
0
0
0
None
1 (1/4)
0
1
0C00h-0FFFh
2 (1/2)
1
0
0800h-0FFFh
3 (All)
1
1
0000h-0FFFh
E-CMOS Corp. (www.ecmos.com.tw)
Page 5 of 16
5F09N-Rev.F001
EC25C32
32Kbits SPI Serial EEPROM
Op-Code Instructions
The operations of the EC25C32 are controlled by a set of instruction Op-Codes (Table3) that are clocked-in
serially via SI pin. To initiate an instruction, the chip select(CS) must be Low. Subsequently, each Low-to-High
transition of the clock (SCK) will latch a stable level from SI. After the 8-bit Op-Code, it may continue to latch-in
an address and/or data output, data are latched out at the falling edge of SCK. All communications start with
MSB first. Upon the transmission of the last bit but prior to any following Low-to-High transition on SCK, CS
must be brought to High in order to end the transaction and start the operation. The device will enter into
Standby Mode after the operation is completed. data from SI accordingly, or to output data from SO. During
data output, data are latched out at the falling edge of SCK. All communications start with MSB first. Upon
the transmission of the last bit but prior to any following Low-to-High transition on SCK, CS must be brought
to High in order to end the transaction and start the operation. The device will enter into Standby Mode after the
operation is completed.
Table3: Instruction Op-Codes[1,2,3]
Name
Op-Code
WREN
0000 X110
WRDI
Operation
Address
Data (SI)
Data (SO)
Set Write Enable Latch
-
-
-
0000 X100
Reset Write Enable Latch
-
-
-
RDSR
0000 X101
Read Status Register
-
-
D7-D0 -
WRSR
0000 X001
Write Status Register
-
D7-D0
-
READ
0000 X011
Read Data from Array
A15-A0
-
D7-D0, ...
WRITE
0000 X010
Write Data to Array
A15-A0
D7-D0, ...
-
Notes:
[1] X = Don’t care bit. However, it is recommended to be “0”.
[2]Some address bits may be don’t care (Table 5).
[3] It is strongly recommended that an appropriate format of Op-Code must be entered. Otherwise, it maycause
unexpected phenomenon to be occurred. Nevertheless, it is illegal to input invalid any Op-Code.
Write Enable
When VCC is initially applied ,the device powers up with both status register and entire array in a writedisabled state. Upon completion of Write Disable(WRDI),Write Status Register(WRSR) or Write Data to Array
(WRITE), the device resets the WEN bit in the Status Register to 0. Prior to any data modification, a Write
Enable (WREN) instruction is necessary to set WEN to 1 (Figure.2).
Write Disable
The device can be completely protected from modification by resetting WEN to 0 through the Write Disable
(WRDI) instruction (Figure.3).
Read Status Register
The Read Status(RDSR) instruction reviews the status of Write Protect Enable, Block Protection setting
(Table 2), Write Enable state and RDY status. RDSR is the only instruction accepted when a write
cycle is under way. It is recommended that the status of Write Enable and RDY be checked, especially prior
to an attempted modification of data. These 8 bits information can be repeatedly output on SO after the initial
Op-Code (Figure.4)
.
E-CMOS Corp. (www.ecmos.com.tw)
Page 6 of 16
5F09N-Rev.F001
EC25C32
32Kbits SPI Serial EEPROM
Write Status Register
The Write Status Register(WRSR) instruction allows the user to choose a Block Protection setting and set or
reset the WPENbit. The values of the other data bits incorporated into WRSR can be 0 or 1 and are not stored
in the Status Register. WRSR will be ignored unless both following conditions are true: a) WEN=1, due to a
prior WREN instruction; and b) Hardware Write Protection is not enabled(Table 4). Except for RDY status, the
values in the Status Register remain unchanged until the moment when the write cycle is completed and the
register is updated. Note that WPEN can be changed from 1 to 0 only if WP is already set High. Once
completed, WEN is reset for complete chip write protection (Fig.5).
Read Data
This instruction includes an Op-Code and 16-bit address, then results the selected data to be shifted out from
SO. Following the first data byte, additional sequential data can be output. If the data byte of the last
address is initially output, then address will rollover to the first address in the array, and the output could loop
indefinitely. At any time, a rising CS signal ceases the operation (Figure.6).
Write Data
The WRITE instruction contains an Op-Code, a 16-bit address and the first data byte. Additional data bytes
may be supplied sequentially after the first byte. Each WRITE instruction can affect up to 32 bytes of data in a
page. Each page has a starting address XXXXXXXX XXX00000 and an ending address XXXXXXXX XXX11111.
After the last byte of data in a page is input, the address rolls over to the beginning of the same page. If more
than 32 bytes of data is input during a single instruction, then only the last 32 bytes will be retained, but the
initial data will be overwritten. The contents of the array defined by Block Protection cannot be modified as long
as that block configuration is selected. The contents of the array outside the Block Protection can only be
modified if Write Enable (WEN) is set to 1. Therefore, it may be necessary that a WREN instruction is initiated
prior to WRITE. Once Write operation is completed, WEN is reset for complete chip write protection (Figure.7)
Besides, Hardware Write Protection has no affect on the memory array.
Table 4: Write Protection
WPEN
WP
0
X
0
Hardware Write
Status Register
WEN
Inside Block
Outside Block
Not Enabled
0
Read-only
Read-only
Read-only
X
Not Enabled
1
Read-only
Unprotected
Unprotected
1
0
Enabled
0
Read-only
Read-only
Read-only
1
0
Enabled
1
Read-only
Unprotected
Read-only
X
1
Not Enabled
0
Read-only
Read-only
Read-only
X
1
Not Enabled
1
Read-only
Unprotected
Unprotected
Protection
(WPEN, BP1, BP0)
Note: X = Don't care bit.
Table 5: Address Key
Name
EC25C32
AN
A11-A0
Don't Care Bits
A15~ A12
E-CMOS Corp. (www.ecmos.com.tw)
Page 7 of 16
5F09N-Rev.F001
32Kbits SPI Serial EEPROM
EC25C32
Diagrams
Figure 1. Synchronous Data Timing
Figure 2. WREN Timing
Figure 3. WRDI Timing
E-CMOS Corp. (www.ecmos.com.tw)
Page 8 of 16
5F09N-Rev.F001
32Kbits SPI Serial EEPROM
EC25C32
Figure 4. RDSR Timing
Figure 5. WRSR Timing
Figure 6. READ Timing
E-CMOS Corp. (www.ecmos.com.tw)
Page 9 of 16
5F09N-Rev.F001
32Kbits SPI Serial EEPROM
EC25C32
Figure 7. WRITE Timing
Figure 8. HOLD Timing
E-CMOS Corp. (www.ecmos.com.tw)
Page 10 of 16
5F09N-Rev.F001
EC25C32
32Kbits SPI Serial EEPROM
Electrical Characteristics
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
VS
Supply Voltage
-0.5 to + 6.5
VP
Voltage on Any Pin
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
–0.5 to VCC + 0.5
Output Current
IOUT
V
V
5
mA
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other condition outside those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Operating Range
Range
Industrial
Ambient Temperature (TA)
–40°C to +85°C
VCC
1.7V to 5.5V
Capacitance
Symbol
CIN
CI/O
Parameter
[1,2]
Input Capacitance
Input / Output
Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VI/O = 0V
8
pF
Note: (1) Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
(2) Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V.
E-CMOS Corp. (www.ecmos.com.tw)
Page 11 of 16
5F09N-Rev.F001
EC25C32
32Kbits SPI Serial EEPROM
DC Electrical Characteristic
Industrial: TA = –40°C to +85°C, VCC = 1.7V ~ 5.5V
Symbol
Parameter
VCC
Test Conditions
Min.
Max.
Unit
1.7
5.5
V
VCC
Supply Voltage
VIH
Input High Voltage
0.7* VCC
VCC+1
V
VIL
Input Low Voltage
-0.3
0.3* VCC
V
ILI
Input Leakage Current
VIN = 0V To VCC
-2
2
μA
ILO
Output Leakage Current
VOUT = 0V To VCC, CS = VCC
-2
2
μA
VOH
Output High Voltage
VOL
Output Low Voltage
1.7
IOH = -0.1mA
0.8*VCC
—
V
2.5
IOH = -0.4mA
0.8*VCC
—
V
5
IOH = -2 mA
0.8*VCC
—
V
1.7
IOL = 0.15 mA
—
0.2
V
2.5
IOL = 1.5 mA
—
0.4
V
IOL = 2 mA
—
0.4
V
1.7
Write at 5 MHz, SO=Open
—
1
mA
2.5
Write at 10 MHz, SO=Open
—
2
mA
5
Write at 20 MHz, SO=Open
—
3
mA
1.7
VIN= VCC or GND, CS = VCC
—
1
μA
2.5
VIN= VCC or GND, CS = VCC
—
2
μA
5
VIN= VCC or GND, CS = VCC
—
3
μA
5
Write Operating Current
I
ISB
Standby Current
E-CMOS Corp. (www.ecmos.com.tw)
Page 12 of 16
5F09N-Rev.F001
32Kbits SPI Serial EEPROM
EC25C32
AC Electrical Characteristic
1.7VVCC<2.5V
2.5VVCC<4.5V
4.5VVCC5.5V
Min.
Max.
Min.
Max.
Min.
Max.
SCK Clock Frequency
0
5
0
10
0
20
MHz
TRI
Input Rise Time
—
1
—
1
—
1
μs
TFI
Input Fall Time
—
1
—
1
—
1
μs
TWH
SCK High Time
80
—
40
—
20
—
ns
TWL
SCK Low Time
80
—
40
—
20
—
ns
TCS
CS High Time
100
—
50
—
25
—
ns
TCSS
CS Setup Time
100
—
50
—
25
—
ns
TCSH
CS Hold Time
100
—
50
—
25
—
ns
TSU
Data In Setup Time
20
—
10
—
5
—
ns
TH
Data In Hold Time
20
—
10
—
5
—
ns
THD
HOLD Setup Time
20
—
10
—
5
—
ns
TCD
HOLD Hold Time
20
—
10
—
5
—
ns
Output Valid
0
80
0
40
0
20
ns
THO
Output Hold Time
0
—
0
—
0
—
ns
TLZ
HOLDto Output Low Z
0
80
0
40
0
25
ns
THZ
HOLDto Output High Z
—
80
—
40
—
40
ns
TDIS
Output Disable Time
—
80
—
40
—
40
ns
TWC
Write Cycle Time
—
5
—
5
—
5
ms
Symbol
FSCK
TV
[2]
Parameter[1]
Unit
Industrial: TA = –40°C to +85°C, Supply voltage = 1.7V to 5.5V
Notes:
[1] The parameters are characterized but not 100% tested.
[2] CL = 30pF (typical)
E-CMOS Corp. (www.ecmos.com.tw)
Page 13 of 16
5F09N-Rev.F001
32Kbits SPI Serial EEPROM
EC25C32
Package Information
SOP -8
SYMBOLS
A
A1
b
D
E
E1
e
L
L1
ZD
Θ
DIMENSIONS IN MILLIMETERS
MIN
NOM
MAX
1.35
-1.75
0.10
-0.25
0.33
-0.51
4.80
-5.00
5.80
-6.20
3.80
-4.00
1.27 BSC.
0.38
-1.27
0.25 BSC.
0.545 REF.
0
-8°
DIMENSIONS IN INCHES
MIN
NOM
0.053
-0.004
-0.013
-0.189
-0.228
-0.150
-0.050 BSC.
0.015
0.010 BSC.
0.021 REF.
0
--
MAX
0.069
0.010
0.020
0.197
0.244
0.157
0.050
8°
Note:
1. Controlling Dimension：MM
2. Dimension D and E1 do not include
Mold protrusion
3. Dimension b does not include dambar protrusion/intrusion.
4. Refer to Jedec standard MS-012
5. Drawing is not to scale
E-CMOS Corp. (www.ecmos.com.tw)
Page 14 of 16
5F09N-Rev.F001
32Kbits SPI Serial EEPROM
EC25C32
TSSOP -8
SYMBOLS DIMENSIONS IN MILLIMETERS
MIN
NOM
MAX
A
--1.20
A1
0.05
-0.15
A2
0.80
1.00
1.05
b
0.19
-0.30
c
0.09
-0.20
D
2.90
3.00
3.10
E
4.30
4.40
4.50
E1
6.4 BSC
e
0.65 BSC
L
0.45
0.60
0.75
Θ
0
-8°
DIMENSIONS IN INCHES
MIN
NOM
MAX
--0.047
0.002
-0.006
0.031
0.039
0.041
0.007
-0.012
0.004
-0.008
0.114
0.118
0.122
0.169
0.173
0.177
0.252 BSC
0.026 BSC
0.018
0.024
0.030
0
-8°
Note:
1. Controlling Dimension：MM
2. Dimension D and E do not include Mold protrusion
3. Dimension b does not include dambar protrusion/intrusion.
4. Refer to Jedec standard MO-153 AA
5. Drawing is not to scale
6. Package may have exposed tie bar
E-CMOS Corp. (www.ecmos.com.tw)
Page 15 of 16
5F09N-Rev.F001
32Kbits SPI Serial EEPROM
EC25C32
DFN-8
SYMBOLS
A
A1
b
A2
D
D2
E
E2
e
K
L
DIMENSIONS IN MILLIMETERS
MIN
NOM
MAX
0.50
0.55
0.60
0.00
-0.05
0.18
0.25
0.30
0.152 REF
2.00 BSC
1.25
1.40
1.50
3.00 BSC
1.15
1.30
1.40
0.50 BSC.
0.40
--0.20
0.30
0.40
DIMENSIONS IN INCHES
MIN
NOM
MAX
0.020
0.022
0.024
0.000
-0.002
0.007
0.010
0.012
0.006 REF
0.079 BSC
0.049
0.055
0.059
0.118 BSC
0.045
0.051
0.055
0.020 BSC.
0.016
--0.008
0.012
0.016
Note:
1. Controlling Dimension：MM
2. Drawing is not to scale
E-CMOS Corp. (www.ecmos.com.tw)
Page 16 of 16
5F09N-Rev.F001