DSC2044 Low-Jitter Configurable Dual HCSL Oscillator General Description Features The DSC2044 series of high performance dual output oscillators utilize a proven silicon MEMS technology to provide excellent jitter and stability while incorporating additional device functionality. The two outputs are controlled by separate supply voltages to allow for high output isolation. The frequencies of the outputs can be identical or independently derived from a common PLL frequency source. The DSC2044 has provision for up to eight user-defined preprogrammed, pin-selectable output frequency combinations. Low RMS Phase Jitter: <1 ps (typ) DSC2044 is packaged in a 14-pin 3.2x2.5 mm QFN package and available in temperature grades from Ext. Commercial to Industrial. Wide Freq. Range: o HCSL Output: 2.3 – 460 MHz High Stability: ±10, ±25, ±50 ppm Wide Temperature Range o Industrial: -40° to 85° C o Ext. commercial: -20° to 70° C High Supply Noise Rejection: -50 dBc Two Independent HCSL Outputs Pin-Selectable Configurations o 3-bit Output Frequency Combinations Short Lead Times: 2 Weeks Miniature Footprint of 3.2x2.5mm Excellent Shock & Vibration Immunity o Qualified to MIL-STD-883 High Reliability o 20x better MTF than quartz oscillators Block Diagram Supply Range of 2.25 to 3.6 V Lead Free & RoHS Compliant Applications Storage Area Networks o SATA, SAS, Fibre Channel Passive Optical Networks o EPON, 10G-EPON, GPON, 10G-PON Ethernet o 1G, 10GBASE-T/KR/LR/SR, and FCoE HD/SD/SDI Video & Surveillance PCI Express _____________________________________________________________________________________________________________________________ _________________ DSC2044 Page 1 MK-Q-B-P-D-12042614-2 DSC2044 Low-Jitter Configurable Dual HCSL Oscillator Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name Enable NC NC GND FS0 FS1 FS2 Output1+ Output1Output 2Output 2+ VDD2 VDD NC Pin Type I NA NA Power I I I O O O O Power Power NA Description Enables outputs when high and disables when low Leave unconnected or grounded Leave unconnected or grounded Ground Least significant bit for frequency selection Middle bit for frequency selection Most significant bit for frequency selection Positive HCSL Output 1 Negative HCSL Output 1 Negative HCSL Output 2 Positive HCSL Output 2 Power Supply for HCSL Output 2 Power Supply Leave unconnected or grounded Operational Description The DSC2044 is a dual output HCSL oscillator consisting of a MEMS resonator and a support PLL IC. The two outputs are generated through independent 8-bit programmable dividers from the output of the internal PLL. Two constraints are imposed on the output frequencies: 1) f2=M x f1/N, where M and N are even integers between 4 and 254, 2) 1.2GHz < N x f2 < 1.7GHz. The actual frequencies output by the DSC2044 are controlled by an internal pre-programmed memory (OTP). This memory stores all coefficients required by the PLL for up to eight different frequency combinations. Three control pins (FS0 – FS2) select the output frequency combination. Discera supports customer defined versions of the DSC2044. Standard frequency options are described in in the following sections. When Enable (pin 1) is floated or connected to VDD, the DSC2044 is in operational mode. Driving Enable to ground will tri-state both output drivers (hi-impedance mode). _____________________________________________________________________________________________________________________________ _________________ DSC2044 Page 2 MK-Q-B-P-D-12042614-2 DSC2044 Low-Jitter Configurable Dual HCSL Oscillator Output Clock Frequencies Table 1 lists the standard frequency configurations and the associated ordering information to be used in conjunction with the ordering code. Customer defined combinations are available. Table 1. Pre-programmed pin-selectable output frequency combinations Ordering Info H0001 H0002 H0003 H0004 HXXXX Freq (MHz) Freq Select Bits [FS2, FS1, FS0] – Default is [111] fOUT1 000 106.25 001 100 010 125 011 100 100 156.25 101 156.25 110 125 111 156.25 fOUT2 25 100 50 50 25 125 25 156.25 fOUT1 100 156.25 100 125 125 50 200 200 fOUT2 100 156.25 50 125 50 50 50 10 fOUT1 125 100 125 0* 0* 0* 0* 156.25 fOUT2 156.25 100 125 0* 0* 0* 0* 156.25 fOUT1 75 100 125 150 75 100 75 125 fOUT2 75 100 125 150 125 150 100 150 fOUT1 fOUT2 Contact factory for additional configurations. Frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and the device will output the associated frequency highlighted in Bold 0* – denotes invalid selection, output frequency is not specified. _____________________________________________________________________________________________________________________________ _________________ DSC2044 Page 3 MK-Q-B-P-D-12042614-2 DSC2044 Low-Jitter Configurable Dual HCSL Oscillator Absolute Maximum Ratings Item Min Max Unit Supply Voltage -0.3 +4.0 V Input Voltage Junction Temp Storage Temp Soldering Temp ESD HBM MM CDM -0.3 -55 - VDD+0.3 +150 +150 +260 V °C °C °C V Ordering Code Condition Temp Range E: -20 to 70 I: -40 to 85 DSC2044 F I 2 40sec max. Package F: 3.2x2.5mm 4000 400 1500 - xxxxx Stability 1: ±50ppm 2: ±25ppm 5: ±10ppm Packing T: Tape & Reel : Tube T Freq (MHz) See Freq. table Note: 1000+ years of data retention on internal memory Specifications (Unless specified otherwise: T=25° C) Parameter Supply Voltage 1 Supply Current Condition VDD Min. Typ. 2.25 Max. Unit 3.6 V 23 mA IDD EN pin low – outputs are disabled 21 Supply Current2 IDD EN pin high – outputs are enabled RL=50 Ω, FO1=FO2=156.25 MHz 60 Frequency Stability Δf Includes frequency variations due to initial tolerance, temp. and power supply voltage ±10 ±25 ±50 ppm Aging Startup Time3 Input Logic Levels Input logic high Input logic low Δf tSU 1 year @25°C T=25°C ±5 5 ppm ms VIH VIL 0.25xVDD V Output Disable Time4 tDA 5 ns Output Enable Time tEN 20 ns 2 Pull-Up Resistor 0.75xVDD - Pull-up exists on all digital IO mA 40 kΩ HCSL Outputs Output Logic Levels Output logic high Output logic low VOH VOL Pk to Pk Output Swing tR tF Frequency 5 Period Jitter Integrated Phase Noise Notes: 1. 2. 3. 4. 5. 0.725 - Single-Ended Output Transition time4 Rise Time Fall Time Output Duty Cycle RL=50Ω 0.1 750 V mV 20% to 80% RL=50Ω, CL= 2pF 200 400 ps f0 Single Frequency 2.3 460 MHz SYM Differential 48 52 % JPER FO1=FO2=156.25 MHz 2.8 JPH 200kHz to 20MHz @156.25MHz 100kHz to 20MHz @156.25MHz 12kHz to 20MHz @156.25MHz 0.25 0.37 1.7 psRMS 2 psRMS Pin 4 VDD should be filtered with 0.01uf capacitor. Output is enabled if Enable pad is floated or not connected. tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled. Output Waveform and Test Circuit figures below define the parameters. Period Jitter includes crosstalk from adjacent output. _____________________________________________________________________________________________________________________________ _________________ DSC2044 Page 4 MK-Q-B-P-D-12042614-2 DSC2044 Low-Jitter Configurable Dual HCSL Oscillator Nominal Performance Parameters (Unless specified otherwise: T=25° C, VDD=3.3 V) 2.5 Phase Jitter (ps RMS) 50MHz-HCSL 106MHz-HCSL 2.0 156MHz-HCSL 1.5 212MHz-HCSL 1.0 0.5 0.0 0 200 400 600 800 1000 Low-end of integration BW: x kHz to 20 MHz HCSL Phase jitter (integrated phase noise) Output Waveform: HCSL tR Output tF 80% 675 830 mvmV 50% Output 20% tEN 1/f o tDA VIH Enable VIL _____________________________________________________________________________________________________________________________ _________________ DSC2044 Page 5 MK-Q-B-P-D-12042614-2 DSC2044 Low-Jitter Configurable Dual HCSL Oscillator Solder Reflow Profile 20-40 Sec Se 3C / 217°C 200°C 60-150 Sec . ax cM Se 3C / 25°C a x. Reflow 60-180 Sec cM 150°C Se 6C/ Temperature (°C) cM ax . 260°C Cool Pre heat Time 8 min max MSL 1 @ 260°C refer to JSTD-020C Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max. Preheat Time 150°C to 200°C 60-180 Sec Time maintained above 217°C 60-150 Sec 255-260°C Peak Temperature Time within 5°C of actual Peak 20-40 Sec 6°C/Sec Max. Ramp-Down Rate Time 25°C to Peak Temperature 8 min Max. Package Dimensions 3.2 x 2.5 mm 14 Lead Plastic Package Disclaimer: Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. MICREL, Inc. Phone: +1 (408) 944-0800 ● ● 2180 Fortune Drive, Fax: +1 (408) 474-1000 San Jose, California 95131 ● Email: [email protected] ● ● USA www.micrel.com _____________________________________________________________________________________________________________________________ _________________ DSC2044 Page 6 MK-Q-B-P-D-12042614-2