AD ADG5213BRUZ High voltage latch-up proof, quad spst switches 0.07 pc charge injection Datasheet

High Voltage Latch-Up Proof,
Quad SPST Switches
ADG5212/ADG5213
FUNCTIONAL BLOCK DIAGRAMS
Latch-up proof
3 pF off source capacitance
5 pF off drain capacitance
0.07 pC charge injection
Low leakage: 0.2 nA maximum at 85ºC
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VSS to VDD analog signal range
S1
S1
IN1
IN1
D1
D1
S2
S2
IN2
IN2
D2
ADG5212
D2
ADG5213
S3
IN3
D3
D3
S4
APPLICATIONS
S4
IN4
IN4
D4
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG5212/ADG5213 contain four independent singlepole/single-throw (SPST) switches. The ADG5212 switches
turn on with Logic 1. The ADG5213 has two switches with
digital control logic similar to that of the ADG5212; however,
the logic is inverted on the other two switches. Each switch
conducts equally well in both directions when on, and each
switch has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.
1.
The ADG5212 and ADG5213 do not have a VL pin. The digital
inputs are compatible with 3 V logic inputs over the full
operating supply range.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required.
Fast switching speed together with high signal bandwidth make
the parts suitable for video signal switching.
S3
IN3
09767-001
FEATURES
2.
3.
4.
5.
6.
Trench Isolation Guards Against Latch-Up.
A dielectric trench separates the P and N channel transistors,
thereby preventing latch-up even under severe overvoltage
conditions.
Ultralow Capacitance and <1 pC Charge Injection.
Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5212/ADG5213 can be operated from dual supplies of
up to ±22 V.
Single-Supply Operation.
For applications where the analog signal is unipolar, the
ADG5212/ADG5213 can be operated from a single rail
power supply of up to 40 V.
3 V Logic-Compatible Digital Inputs.
VINH = 2.0 V, VINL = 0.8 V.
No VL Logic Power Supply Required.
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADG5212/ADG5213
TABLE OF CONTENTS
Features .............................................................................................. 1
Continuous Current per Channel, Sx or Dx..............................7
Applications....................................................................................... 1
Absolute Maximum Ratings ............................................................8
Functional Block Diagrams............................................................. 1
ESD Caution...................................................................................8
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ............................9
Product Highlights ........................................................................... 1
Typical Performance Characteristics ........................................... 10
Revision History ............................................................................... 2
Test Circuits..................................................................................... 14
Specifications..................................................................................... 3
Terminology .................................................................................... 16
±15 V Dual Supply ....................................................................... 3
Trench Isolation.............................................................................. 17
±20 V Dual Supply ....................................................................... 4
Applications Information .............................................................. 18
12 V Single Supply........................................................................ 5
Outline Dimensions ....................................................................... 19
36 V Single Supply........................................................................ 6
Ordering Guide .......................................................................... 19
REVISION HISTORY
4/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG5212/ADG5213
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
−40°C to +85°C
−40°C to +125°C
Unit
VDD to VSS
V max
Ω typ
160
200
2
8
38
50
250
280
9
10
65
70
tOFF
Break-Before-Make Time Delay, tD
(ADG5213 Only)
nA typ
0.1
0.01
0.2
0.4
0.1
0.02
0.2
0.2
0.4
0.25
0.9
2.0
0.8
0.002
3
175
210
140
170
40
255
280
195
215
20
VIN = VGND or VDD
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 30
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V, see Figure 29
VS = 0 V, RS = 0 Ω, CL = 1 nF,
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 27
RL = 50 Ω, CL = 5 pF, see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 28
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
−105
dB typ
Channel-to-Channel Crosstalk
−105
dB typ
−3 dB Bandwidth
Insertion Loss
435
−6.8
MHz typ
dB typ
3
5
8
pF typ
pF typ
pF typ
70
1
±9/±22
Guaranteed by design; not subject to production test.
Rev. 0 | Page 3 of 20
VS = ±10 V, VD = ∓10 V,
see Figure 23
V min
V max
μA typ
μA max
pF typ
Off Isolation
45
55
0.001
VS = ±10 V, VD = ∓10 V,
see Figure 23
VS = VD = ±10 V, see Figure 26
ns min
pC typ
VDD/VSS
VS = ±10 V, IS = −1 mA
nA max
nA typ
nA max
0.07
ISS
1
nA max
nA typ
Charge Injection, QINJ
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
VS = ±10 V, IS = −1 mA,
see Figure 24
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
VDD = +16.5 V, VSS = −16.5 V
0.01
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
μA typ
μA max
μA typ
μA max
V min/V max
Digital inputs = 0 V or VDD
GND = 0 V
ADG5212/ADG5213
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
25°C
−40°C to +85°C
−40°C to +125°C
Unit
VDD to VSS
V max
Ω typ
140
160
1.5
200
230
Ω max
Ω typ
8
33
45
9
10
55
60
Ω max
Ω typ
Ω max
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
0.01
0.1
0.01
0.2
Drain Off Leakage, ID (Off )
0.1
0.02
0.2
0.2
0.4
0.25
0.9
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
tOFF
Break-Before-Make Time Delay, tD
(ADG5213 Only)
VS = ±15 V, IS = −1 mA,
see Figure 24
VDD = +18 V, VSS = −18 V
VS = ±15 V, IS = −1 mA
VS = ±15 V, IS = −1 mA
VDD = +22 V, VSS = −22 V
nA typ
0.4
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
Test Conditions/Comments
3
155
195
145
165
35
235
255
185
210
20
nA max
nA typ
VS = ±15 V, VD = ∓15 V,
see Figure 23
nA max
nA typ
nA max
VS = VD = ±15 V, see Figure 26
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 30
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V, see Figure 29
VS = 0 V, RS = 0 Ω, CL = 1 nF,
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 27
RL = 50 Ω, CL = 5 pF, see
Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 28
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
Charge Injection, QINJ
−0.5
ns min
pC typ
Off Isolation
−105
dB typ
Channel-to-Channel Crosstalk
−105
dB typ
−3 dB Bandwidth
460
MHz typ
Insertion Loss
−6
dB typ
CS (Off )
CD (Off )
CD (On), CS (On)
2.8
4.8
8
pF typ
pF typ
pF typ
Rev. 0 | Page 4 of 20
VS = ±15 V, VD = ∓15 V,
see Figure 23
ADG5212/ADG5213
Parameter
POWER REQUIREMENTS
IDD
ISS
25°C
−40°C to +85°C
50
70
0.001
110
1
±9/±22
VDD/VSS
1
−40°C to +125°C
Unit
μA typ
μA max
μA typ
μA max
V min/V max
Test Conditions/Comments
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
25°C
−40°C to +85°C
Unit
0 V to VDD
V max
Ω typ
350
500
4
20
160
280
610
700
21
22
335
370
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.01
0.1
0.01
0.2
Drain Off Leakage, ID (Off)
0.1
0.02
0.2
Channel On Leakage, ID (On), IS (On)
0.2
0.25
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
−40°C to +125°C
nA typ
0.4
0.4
tOFF
Break-Before-Make Time Delay, tD
(ADG5213 Only)
nA max
nA typ
VS = 0 V to 10 V, IS = −1 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V,
see Figure 23
VS = 1 V/10 V, VD = 10 V/1 V,
see Figure 23
VS = VD = 1 V/10 V,
see Figure 26
nA max
2.0
0.8
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 30
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V, see Figure 29
VS = 6 V, RS = 0 Ω, CL = 1 nF,
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 27
RL = 50 Ω, CL = 5 pF, see
Figure 28
0.002
3
235
290
165
205
85
nA max
nA typ
VS = 0 V to 10 V, IS = −1 mA,
see Figure 24
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
0.9
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
360
410
235
260
Charge Injection, QINJ
−0.5
50
ns min
pC typ
Off Isolation
−105
dB typ
Channel-to-Channel Crosstalk
−105
dB typ
−3 dB Bandwidth
340
MHz typ
Rev. 0 | Page 5 of 20
ADG5212/ADG5213
Parameter
Insertion Loss
25°C
−11
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
3.5
5.5
9
−40°C to +85°C
Unit
dB typ
pF typ
pF typ
pF typ
40
65
9/40
VDD
1
−40°C to +125°C
μA typ
μA max
V min/V max
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 28
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
25°C
−40°C to +85°C
Unit
0 V to VDD
V max
Ω typ
150
170
1.6
8
35
50
215
245
9
10
60
65
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.01
0.1
0.01
0.2
Drain Off Leakage, ID (Off)
0.1
0.02
0.2
Channel On Leakage, ID (On), IS (On)
0.2
0.25
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
−40°C to +125°C
nA typ
0.4
0.4
tOFF
Break-Before-Make Time Delay, tD
(ADG5213 Only)
nA max
nA typ
VS = 0 V to 30 V, IS = −1 mA
VDD =39.6 V, VSS = 0 V
VS = 1 V/30 V, VD = 30 V/1 V,
see Figure 23
VS = 1 V/30 V, VD = 30 V/1 V,
see Figure 23
VS = VD = 1 V/30 V,
see Figure 26
nA max
2.0
0.8
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 30
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 18 V, see Figure 29
VS = 18 V, RS = 0 Ω, CL = 1 nF,
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
Figure 27
0.002
3
190
230
175
215
45
nA max
nA typ
VS = 0 V to 30 V, IS = −1 mA,
see Figure 24
VDD = 32.4 V, VSS = 0 V
VS = 0 V to 30 V, IS = −1 mA
0.9
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
255
265
230
245
Charge Injection, QINJ
−0.5
25
ns min
pC typ
Off Isolation
−105
dB typ
Channel-to-Channel Crosstalk
−105
dB typ
Rev. 0 | Page 6 of 20
ADG5212/ADG5213
Parameter
−3 dB Bandwidth
25°C
410
Insertion Loss
−6.8
dB typ
3
5
8
pF typ
pF typ
pF typ
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
IDD
−40°C to +85°C
80
100
Unit
MHz typ
μA typ
μA max
V min/V max
130
9/40
VDD
1
−40°C to +125°C
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF,
see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 28
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter
CONTINUOUS CURRENT, Sx or Dx
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
25°C
85°C
125°C
Unit
18
32
10
15
5
6
mA maximum
mA maximum
29
50
16
22
8
9
mA maximum
mA maximum
18
32
12
17
7
8
mA maximum
mA maximum
34
59
18
24
8
9
mA maximum
mA maximum
Rev. 0 | Page 7 of 20
ADG5212/ADG5213
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, Sx or Dx Pin
Continuous Current, Sx or Dx2
Temperature
Operating Range
Storage Range
Junction
Thermal Impedance, θJA
16-Lead TSSOP (4-Layer Board)
16-Lead LFCSP (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb Free
1
2
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
60 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Data + 15%
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
112.6°C/W
30.4°C/W
260(+0/−5)°C
Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
See Table 5.
Rev. 0 | Page 8 of 20
ADG5212/ADG5213
S1 1
VSS 2
TOP VIEW 12 NC
(Not to Scale)
S4 6
11 S3
GND 5
D3
IN4 8
9
IN3
NC = NO CONNECT
TOP VIEW
(Not to Scale)
D4 5
10
S4 4
09767-002
D4 7
GND 3
ADG5212/
ADG5213
12 S2
11 VDD
10 NC
9 S3
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
2. NC = NO CONNECT.
09767-003
VDD
ADG5212/
ADG5213
14 IN2
S2
13
VSS 4
13 D2
14
D3 8
D2
S1 3
15 IN1
IN2
15
IN3 7
16
D1 2
IN4 6
IN1 1
16 D1
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. LFCSP Pin Configuration
Figure 2. TSSOP Pin Configuration
Table 7. Pin Function Descriptions
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
N/A1
1
Pin No.
LFCSP
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
EP
Mnemonic
IN1
D1
S1
VSS
GND
S4
D4
IN4
IN3
D3
S3
NC
VDD
S2
D2
IN2
Exposed pad
Description
Logic Control Input.
Drain Terminal. This pin can be an input or an output.
Source Terminal. This pin can be an input or an output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Logic Control Input.
Logic Control Input.
Drain Terminal. This pin can be an input or an output.
Source Terminal. This pin can be an input or an output.
No Connect. These pins are open.
Most Positive Power Supply Potential.
Source Terminal. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Logic Control Input.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the
solder joints and maximum thermal capability, it is recommended that the pad be
soldered to the substrate, VSS.
N/A means not applicable.
Table 8. ADG5212 Truth Table
ADG5212 INx
1
0
Switch Condition
On
Off
Table 9. ADG5213 Truth Table
ADG5213 INx
0
1
S1, S4
Off
On
S2, S3
On
Off
Rev. 0 | Page 9 of 20
ADG5212/ADG5213
TYPICAL PERFORMANCE CHARACTERISTICS
160
TA = 25°C
140
VDD = +18V
VSS = –18V
ON RESISTANCE (Ω)
100
VDD = +20V
VSS = –20V
80
VDD = +22V
VSS = –22V
60
100
60
40
20
20
–20
–15
–10
–5
0
5
10
15
20
25
VS, VD (V)
0
0
TA = 25°C
5
10
15
20
25
30
35
40
VS, VD (V)
Figure 4. RON as a Function of VS, VD (Dual Supply)
250
VDD = 39.6V
VSS = 0V
VDD = 36V
VSS = 0V
80
40
0
–25
VDD = 32.4V
VSS = 0V
120
09767-104
ON RESISTANCE (Ω)
120
TA = 25°C
140
09767-107
160
Figure 7. RON as a Function of VS, VD (Single Supply)
250
VDD = +9V
VSS = –9V
200
VDD = +15V
VSS = –15V
200
ON RESISTANCE (Ω)
150
VDD = +13.2V
VSS = –13.2V
100
VDD = +16.5V
VSS = –16.5V
VDD = +15V
VSS = –15V
TA = –40°C
50
–15
–10
–5
0
5
10
15
20
VS, VD (V)
0
–15
09767-105
0
–20
500
TA = 25°C
160
ON RESISTANCE (Ω)
300
250
200
150
140
80
TA = –40°C
60
6
8
10
12
VS, VD (V)
14
09767-106
20
0
Figure 6. RON as a Function of VS, VD (Single Supply)
TA = +85°C
TA = +25°C
50
4
15
TA = +125°C
100
40
2
10
120
100
0
5
180
VDD = 12V
VSS = 0V
VDD = 13.2V
VSS = 0V
350
0
200
VDD = 10.8V
VSS = 0V
400
–5
Figure 8. RON as a Function of VS, VD for Different Temperatures,
±15 V Dual Supply
VDD = 9V
VSS = 0V
450
–10
VS, VD (V)
Figure 5. RON as a Function of VS, VD (Dual Supply)
ON RESISTANCE (Ω)
TA = +25°C
100
09767-108
50
TA = +85°C
150
VDD = +20V
VSS = –20V
0
–20
–15
–10
–5
0
5
10
15
20
VS, VD (V)
Figure 9. RON as a Function of VS, VD for Different Temperatures,
±20 V Dual Supply
Rev. 0 | Page 10 of 20
09767-109
ON RESISTANCE (Ω)
TA = +125°C
ADG5212/ADG5213
100
400
TA = +125°C
340
TA = +85°C
300
TA = +25°C
250
200
TA = –40°C
150
100
VDD = 12V
VSS = 0V
0
IS (OFF) – +
–50
ID (OFF) + –
–100
ID, IS (ON) – –
2
4
6
8
10
12
VS, VD (V)
–200
0
40
TA = +85°C
TA = +25°C
100
TA = –40°C
50
125
ID, IS (ON) + +
ID (OFF) – +
0
10
15
20
25
30
35
IS (OFF) – +
–40
–60
ID (OFF) + –
–80
–100
VS, VD (V)
0
25
75
100
50
IS (OFF) + –
IS (OFF) + –
ID, IS (ON) + +
ID (OFF) – +
0
LEAKAGE CURRENT (pA)
0
–20
IS (OFF) – +
–40
–60
ID (OFF) + –
–80
–100
ID, IS (ON) – –
50
75
100
IS (OFF) – +
–50
–100
ID (OFF) + –
–150
ID, IS (ON) – –
–200
125
TEMPERATURE (°C)
09767-112
VDD = +15V
–120
VSS = –15V
VBIAS = +10V/–10V
–140
0
25
125
Figure 14. Leakage Currents vs. Temperature, 12 V Single Supply
ID, IS (ON) + +
ID (OFF) – +
50
TEMPERATURE (°C)
Figure 11. RON as a Function of VS,VD for Different Temperatures,
36 V Single Supply
20
ID, IS (ON) – –
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
–140
09767-111
0
IS (OFF) + –
–20
–120
LEAKAGE CURRENT (pA)
100
09767-114
LEAKAGE CURRENT (pA)
TA = +125°C
150
40
75
20
200
5
50
Figure 13. Leakage Currents vs. Temperature, ±20 V Dual Supply
VDD = 36V
VSS = 0V
0
25
TEMPERATURE (°C)
Figure 10. RON as a Function of VS, VD for Different Temperatures,
12 V Single Supply
250
VDD = +20V
VSS = –20V
VBIAS = +15V/–15V
Figure 12. Leakage Currents vs. Temperature, ±15 V Dual Supply
VDD = 36V
VSS = 0V
VBIAS = 1V/30V
–250
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 15. Leakage Currents vs. Temperature, 36 V Single Supply
Rev. 0 | Page 11 of 20
09767-115
0
09767-110
0
ID, IS (ON) + +
ID (OFF) – +
–150
50
ON RESISTANCE (Ω)
IS (OFF) + –
50
LEAKAGE CURRENT (pA)
ON RESISTANCE (Ω)
450
09767-113
500
ADG5212/ADG5213
0
0
–20
TA = 25°C
VDD = +15V
VSS = –15V
–40
–40
ACPSRR (dB)
OFF ISOLATION (dB)
TA = 25°C
VDD = +15V
–20 VSS = –15V
–60
–80
NO DECOUPLING CAPACITORS
–60
–80
–100
–100
–120
1M
10M
100M
1G
FREQUENCY (Hz)
09767-120
100k
–120
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 16. Off Isolation vs. Frequency, ±15 V Dual Supply
09767-123
DECOUPLING CAPACITORS
–140
10k
Figure 19. ACPSRR vs. Frequency, ±15 V Dual Supply
0
0
TA = 25°C
–2 VDD = +15V
VSS = –15V
TA = 25°C
VDD = +15V
–20 VSS = –15V
–4
ATTENUATION (dB)
CROSSTALK (dB)
–40
–60
–80
–100
–6
–8
–10
–12
–14
–16
–120
1M
10M
100M
1G
FREQUENCY (Hz)
–20
100k
09767-121
100k
1M
VDD = +20V
VSS = –20V
10
CAPACITANCE (pF)
SOURCE/DRAIN ON
VDD = +15V
VSS = –15V
2
1
VDD = +36V
VSS = 0V
0
VDD = +12V
VSS = 0V
–1
–10
0
10
20
8
6
DRAIN OFF
4
SOURCE OFF
2
30
VS (V)
40
0
–15
–10
–5
0
5
VS (V)
Figure 21. Capacitance
Figure 18. Charge Injection vs. Source Voltage
Rev. 0 | Page 12 of 20
10
15
09767-127
3
–2
–20
1G
TA = 25°C
VDD = +15V
VSS = –15V
4
09767-122
CHARGE INJECTION (pC)
5
12
TA = 25°C
SOURCE TO DRAIN
100M
Figure 20. Bandwidth
Figure 17. Crosstalk vs. Frequency, ±15 V Dual Supply
6
10M
FREQUENCY (Hz)
09767-125
–18
–140
10k
ADG5212/ADG5213
0
–20
TA = 25°C
VDD = +15V
VSS = –15V
TON (+12V)
TON (+36V)
TOFF (+36V)
TOFF (±20V)
TOFF (±15V)
–60
–80
TON (±15V)
TOFF (+12V)
TON (±20V)
–100
–120
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
09767-126
TIME (ns)
–40
Figure 22. tON, tOFF Times vs. Temperature
Rev. 0 | Page 13 of 20
ADG5212/ADG5213
TEST CIRCUITS
S
D
ID (OFF)
A
S
VD
A
VS
09767-015
VS
ID (ON)
D
VD
Figure 26. On Leakage
Figure 23. Off Leakage
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
VOUT
VDD
VSS
S1
RL
50Ω
Dx
IDS
VS
GND
V1
D
RON = V1/IDS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 24. On Resistance
VDD
Figure 27. Channel-to-Channel Crosstalk
VDD
VSS
0.1µF
VDD
NETWORK
ANALYZER
VSS
Sx
INx
VSS
0.1µF
0.1µF
VDD
Dx
RL
50Ω
GND
VS
Dx
VOUT
OFF ISOLATION = 20 log
50Ω
INx
VS
VIN
NETWORK
ANALYZER
VSS
Sx
50Ω
50Ω
VIN
RL
50Ω
GND
VOUT
VS
09767-020
0.1µF
VOUT
VS
09767-021
VS
09767-014
S
RL
50Ω
S2
OFF ISOLATION = 20 log
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 28. Bandwidth
Figure 25. Off Isolation
Rev. 0 | Page 14 of 20
VOUT
09767-028
A
09767-016
IS (OFF)
ADG5212/ADG5213
VDD
VSS
VSS
D1
S2
D2
CL
35pF
RL
300Ω
IN1,
IN2
RL
300Ω
VOUT2
CL
35pF
VOUT1
VOUT2
ADG5213
50%
90%
90%
0V
90%
90%
0V
GND
tD
tD
Figure 29. Break-Before-Make Time Delay, tD
VDD
VSS
0.1µF
0.1µF
VIN
Sx
VS
ADG5212
50%
50%
VSS
VOUT
Dx
CL
35pF
RL
300Ω
INx
90%
VOUT
90%
GND
tOFF
tON
09767-018
VDD
Figure 30. Switching Times
RS
VS
VDD
VSS
VDD
VSS
S
D
VOUT
VIN
ADG5212
ON
OFF
CL
1nF
IN
VOUT
QINJ = CL × ∆VOUT
GND
∆VOUT
09767-019
VS2
VOUT1
50%
0V
Figure 31. Charge Injection
Rev. 0 | Page 15 of 20
09767-017
VDD
S1
VS1
VIN
0.1µF
0.1µF
ADG5212/ADG5213
TERMINOLOGY
IDD
IDD represents the positive supply current.
CIN
CIN is the digital input capacitance.
ISS
ISS represents the negative supply current.
tON
tON represents the delay between applying the digital control
input and the output switching on (see Figure 30).
VD, VS
VD and VS represent the analog voltage on Terminal Dx and
Terminal Sx, respectively.
RON
RON represents the ohmic resistance between Terminal Dx and
Terminal Sx.
ΔRON
ΔRON represents the difference between the RON of any two
channels.
RFLAT(ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range is represented by RFLAT(ON).
IS (Off)
IS (Off) is the source leakage current with the switch off.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
tOFF
tOFF represents the delay between applying the digital control
input and the output switching off (see Figure 30).
tD
tD represents the off time measured between the 80% point of
both switches when switching from one address state to
another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
VINH
VINH is the minimum input voltage for Logic 1.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
AC Power Supply Rejection Ratio (ACPSRR)
AC power supply rejection ratio (ACPSRR) is the ratio of the
amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the device to avoid coupling
noise and spurious signals that appear on the supply voltage pin to
the output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Rev. 0 | Page 16 of 20
ADG5212/ADG5213
TRENCH ISOLATION
In the ADG5212 and ADG5213, an insulating oxide layer
(trench) is placed between the NMOS and the PMOS transistors
of each CMOS switch. Parasitic junctions, which occur between
the transistors in junction isolated switches, are eliminated, and
the result is a completely latch-up proof switch.
PMOS
P WELL
N WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 32. Trench Isolation
Rev. 0 | Page 17 of 20
09767-022
In junction isolation, the N and P wells of the PMOS and NMOS
transistors form a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
can become forward-biased. A silicon controlled rectifier (SCR)
type circuit is formed by the two transistors, causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed and the result is a latchup proof switch.
NMOS
ADG5212/ADG5213
APPLICATIONS INFORMATION
The ADG52xx family of switches and multiplexers provides a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persists until the power supply is
turned off. The ADG5212/ADG5213 high voltage switches
allow single-supply operation from 9 V to 40 V and dual-supply
operation from ±9 V to ±22 V.
Rev. 0 | Page 18 of 20
ADG5212/ADG5213
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.35
0.30
0.25
0.65
BSC
16
13
PIN 1
INDICATOR
12
1
EXPOSED
PAD
4
2.70
2.60 SQ
2.50
9
0.80
0.75
0.70
0.45
0.40
0.35
8
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
08-16-2010-C
TOP VIEW
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG5212BRUZ
ADG5212BRUZ-RL7
ADG5212BCPZ-RL7
ADG5213BRUZ
ADG5213BRUZ-RL7
ADG5213BCPZ-RL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
Package Option
RU-16
RU-16
CP-16-17
RU-16
RU-16
CP-16-17
ADG5212/ADG5213
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09767-0-4/11(0)
Rev. 0 | Page 20 of 20