AD AD6673BCPZRL7-250 80 mhz bandwidth, dual if receiver Datasheet

80 MHz Bandwidth, Dual IF Receiver
AD6673
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
DVDD
AGND
DGND DRGND
AD6673
VIN+A
VIN–A
PIPELINE
11-BIT ADC
JESD-204B
INTERFACE
NSR
VCM
VIN+B
VIN–B
SYSREF±
SYNCINB±
CLK±
RFCLK
PIPELINE
11-BIT ADC
HIGH
SPEED
SERIALIZERS
SERDOUT0±
CML, TX
OUTPUTS
SERDOUT1±
NSR
CMOS
DIGITAL
INPUT
PDWN
CMOS
DIGITAL
OUTPUT
FDA
FDB
CONTROL
REGISTERS
CLOCK
GENERATION
CMOS
DIGITAL
INPUT/OUTPUT
RST
SDIO SCLK
CS
FAST
DETECT
10632-001
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 71.9 dBFS at 185 MHz AIN and
250 MSPS with NSR set to 33%
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz
AIN and 250 MSPS
Total power consumption: 707 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
Figure 1.
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, WCDMA,
CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
General-purpose software radios
PRODUCT HIGHLIGHTS
1. The configurable JESD204B output block with an integrated
phase-locked loop (PLL) to support up to 5 Gbps per lane
with up to two lanes.
2. IF receiver includes two, 11-bit, 250 MSPS ADCs with
programmable noise shaping requantizer (NSR) function that
allows for improved SNR within a reduced bandwidth of 22%
or 33% of the sample rate.
3. Support for an optional RF clock input to ease system board
design.
4. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
5. An on-chip integer, 1-to-8 input clock divider and SYNC
input allows synchronization of multiple devices.
6. Operation from a single 1.8 V power supply.
7. Standard serial port interface (SPI) that supports various
product features and functions, such as controlling the clock
DCS, power-down, test modes, voltage reference mode,
overrange fast detection, and serial output configuration.
This product may be protected by one or more U.S. or international patents.
Rev. C
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Last Content Update: 03/25/2017
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REFERENCE MATERIALS
Informational
• JESD204 Serial Interface
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AD6673
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
33% Bandwidth Mode (>60 MHz at 184.32 MSPS) .............. 25
Applications ....................................................................................... 1
Digital Outputs ............................................................................... 26
Functional Block Diagram .............................................................. 1
JESD204B Transmit Top Level Description ............................ 26
Product Highlights ........................................................................... 1
JESD204B Overview .................................................................. 26
Revision History ............................................................................... 3
Synchronization .......................................................................... 27
General Description ......................................................................... 4
ADC Overrange and Gain Control.......................................... 33
Specifications..................................................................................... 5
ADC Overrange (OR)................................................................ 33
ADC DC Specifications ............................................................... 5
Gain Switching ............................................................................ 33
ADC AC Specifications ............................................................... 6
DC Correction ................................................................................ 35
Digital Specifications ................................................................... 7
DC Correction Bandwidth........................................................ 35
Switching Specifications .............................................................. 9
DC Correction Readback .......................................................... 35
Timing Specifications ................................................................ 10
DC Correction Freeze ................................................................ 35
Absolute Maximum Ratings .......................................................... 11
DC Correction (DCC) Enable Bits .......................................... 35
Thermal Characteristics ............................................................ 11
Serial Port Interface (SPI) .............................................................. 36
ESD Caution ................................................................................ 11
Configuration Using the SPI ..................................................... 36
Pin Configuration and Function Descriptions ........................... 12
Hardware Interface ..................................................................... 36
Typical Performance Characteristics ........................................... 14
SPI Accessible Features .............................................................. 37
Equivalent Circuits ......................................................................... 16
Memory Map .................................................................................. 38
Theory of Operation ...................................................................... 18
Reading the Memory Map Register Table............................... 38
ADC Architecture ...................................................................... 18
Memory Map Register Table ..................................................... 39
Analog Input Considerations.................................................... 18
Memory Map Register Description ......................................... 43
Voltage Reference ....................................................................... 20
Applications Information .............................................................. 44
Clock Input Considerations ...................................................... 20
Design Guidelines ...................................................................... 44
Power Dissipation and Standby Mode..................................... 23
Outline Dimensions ....................................................................... 45
Noise Shaping Requantizer ........................................................... 24
Ordering Guide .......................................................................... 45
22% Bandwidth Mode (>40 MHz at 184.32 MSPS) .............. 24
Rev. C | Page 2 of 45
Data Sheet
AD6673
REVISION HISTORY
12/15—Rev. B to Rev. C
Changes to Nyquist Clock Input Options Section ......................20
Added Synchronization Section ....................................................27
Added Clock Adjustment Register Writes Section .....................28
Changes to Link Setup Parameters Section .................................28
Changes to Additional Digital Output Configuration Options
Section ..............................................................................................30
Added Table 14; Renumbered Sequentially .................................31
Changes to Table 18 ........................................................................39
Changes to Figure 57 Caption .......................................................45
12/13—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Changes to Functional Block Diagram .......................................... 1
Changes to Table 4 ............................................................................ 8
Change to Figure 3 ............................................................................ 9
Changes to Table 8 ..........................................................................11
Change to Figure 20, Figure 21, and Figure 24 ...........................15
Added Figure 26; Renumbered Sequentially ............................... 16
Changes to Table 9 .......................................................................... 18
Changes to JESD204B Overview Section .................................... 25
Changes to JESD204B Synchronization Section ......................... 26
Change to Table 10 .......................................................................... 26
Change to Configure Detailed Options Section ......................... 27
Changes to Figure 50 ...................................................................... 29
Changes to Figure 52, Figure 53, and Figure 54 .......................... 30
Deleted Built-In Self-Test (BIST) and Output Test Section ...... 33
Changes to Table 17 ........................................................................ 37
Changes to Power and Ground Recommendations Section ..... 41
Updated Outline Dimensions........................................................ 42
10/12—Rev.0 to Rev. A
Changes to Applications Section and Figure 1.............................. 1
10/12—Revision 0: Initial Version
Rev. C | Page 3 of 45
AD6673
Data Sheet
GENERAL DESCRIPTION
The AD6673 is an 11-bit, 250 MSPS, dual-channel intermediate
frequency (IF) receiver specifically designed to support multiantenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of two high performance analog-to-digital
converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined
architecture with integrated output error correction logic, and
each ADC features a wide bandwidth switched capacitor sampling
network within the first stage of the differential pipeline. An
integrated voltage reference eases design considerations. A duty
cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent
performance.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
SPI. With the NSR feature enabled, the outputs of the ADCs
are processed such that the AD6673 supports enhanced SNR
performance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution.
The NSR block can be programmed to provide a bandwidth of
either 22% or 33% of the sample clock. For example, with a sample
clock rate of 250 MSPS, the AD6673 can achieve up to 76.3 dBFS
SNR for a 55 MHz bandwidth in the 22% mode and up to
73.5 dBFS SNR for a 82 MHz bandwidth in the 33% mode.
When the NSR block is disabled, the ADC data is provided directly
to the output at a resolution of 11 bits. The AD6673 can achieve
up to 65.9 dBFS SNR for the entire Nyquist bandwidth when
operated in this mode. This allows the AD6673 to be used in
telecommunication applications such as a digital predistortion
observation path where wider bandwidths are required.
By default, the ADC output data is routed directly to the two
external JESD204B serial output lanes. These outputs are at current
mode logic (CML) voltage levels. Two modes are supported such
that output coded data is either sent through one lane or two
(L = 1; F = 4 or L = 2; F = 2). Single lane operation supports
converter rates up to 125 MSPS. Synchronization input controls
(SYNCINB± and SYSREF±) are provided.
The AD6673 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of a separate
antenna. This IF sampling architecture greatly reduces component
cost and complexity compared with traditional analog techniques
or less integrated digital methods.
Flexible power-down options allow significant power savings,
when desired. Programmable overrange level detection is
supported for each channel via dedicated fast detect pins.
Programming for setup and control are accomplished using a
3-wire SPI-compatible serial interface with numerous modes to
support board level system testing.
The AD6673 is available in a 48-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
Rev. C | Page 4 of 45
Data Sheet
AD6673
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, DCS enabled, link parameters used are M = 2 and L = 2, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span
Input Capacitance2
Input Resistance3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
DVDD
Supply Current
IAVDD
IDRVDD + IDVDD
NSR Disabled
NSR Enabled, 22% Mode
NSR Enabled, 33% Mode
POWER CONSUMPTION
Sine Wave Input
NSR Disabled
NSR Enabled, 22% Mode
NSR Enabled, 33% Mode
Standby Power4
Power-Down Power
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Min
11
Typ
Max
Unit
Bits
+16
+2.5
±0.6
mV
%FSR
LSB
LSB
LSB
LSB
Guaranteed
−16
−6
±0.25
±0.7
±0.3
Full
Full
−15
−2
+15
+3
mV
%FSR
Full
Full
±2
±50
ppm/°C
ppm/°C
25°C
0.32
LSB rms
Full
Full
Full
Full
1.75
2.5
20
0.9
V p-p
pF
kΩ
V
Full
Full
Full
1.7
1.7
1.7
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.8
1.8
1.8
1.9
1.9
1.9
V
V
V
254
282
139
187
211
150
mA
mA
mA
mA
mA
707
794
837
334
9
1
Measured with a low input frequency, full-scale sine wave.
Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3
Input resistance refers to the effective resistance between one differential input pin and its complement.
4
Standby power is measured with a dc input and the CLK± pin active.
2
Rev. C | Page 5 of 45
mW
mW
mW
mW
mW
AD6673
Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, DCS enabled, link parameters used are M = 2 and L = 2, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
NSR Disabled
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
Temperature
25°C
25°C
25°C
25°C
Full
25°C
fIN = 220 MHz
NSR Enabled 22% Bandwidth Mode
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
25°C
25°C
25°C
25°C
Full
25°C
fIN = 220 MHz
NSR Enabled 33% Bandwidth Mode
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
25°C
25°C
25°C
25°C
Full
25°C
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
25°C
25°C
25°C
25°C
Full
25°C
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
Rev. C | Page 6 of 45
Min
Typ
Max
66.6
66.2
66.4
66.2
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
65.6
65.9
76.3
75.7
74.8
74.2
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
72.6
73.6
73.5
72.1
72.6
71.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
70.0
71.4
65.5
65.4
65.2
65.1
64.7
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
25°C
10.6
10.6
10.5
10.5
10.5
Bits
Bits
Bits
Bits
Bits
25°C
25°C
25°C
25°C
Full
25°C
−90
−87
−86
−88
dBc
dBc
dBc
dBc
dBc
dBc
64.5
−80
−86
Data Sheet
AD6673
Parameter1
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
Temperature
25°C
25°C
25°C
25°C
Full
25°C
fIN = 220 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 184.12 MHz (−7 dBFS), 187.12 MHz (−7 dBFS)
CROSSTALK2
FULL POWER BANDWIDTH3
1
2
3
Min
Typ
Max
90
87
86
88
Unit
dBc
dBc
dBc
dBc
dBc
dBc
80
86
25°C
25°C
25°C
25°C
Full
25°C
−96
−94
−94
−94
−91
dBc
dBc
dBc
dBc
dBc
dBc
25°C
Full
25°C
88
95
1000
dBc
dB
MHz
−80
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
Full power bandwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 dB.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, DCS enabled, link parameters used are M = 2 and L = 2, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Input CLK± Clock Rate
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
RF CLOCK INPUT (RFCLK)
Input CLK± Clock Rate
Logic Compliance
Internal Bias
Input Voltage Range
Input Voltage Level
High
Low
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance (AC-Coupled)
Temperature
Min
Full
40
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. C | Page 7 of 45
Typ
Max
Unit
625
MHz
CMOS/LVDS/LVPECL
0.9
12
V
V p-p
V
V
µA
µA
pF
kΩ
1500
MHz
AGND
AVDD
V
V
1.2
AGND
0
−150
AVDD
0.6
+150
0
0.3
AGND
0.9
0
−60
8
3.6
AVDD
1.4
+60
0
4
10
650
CMOS/LVDS/LVPECL
0.9
8
1
10
12
V
V
µA
µA
pF
kΩ
AD6673
Parameter
SYNCIN INPUT (SYNCINB+, SYNCINB−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage Range
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYSREF INPUT (SYSREF+/SYSREF−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage Range
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (RST, CS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK, PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS (SERDOUT0±, SERDOUT1±)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
DIGITAL OUTPUTS (SDIO, FDA, FDB)
High Level Output Voltage (VOH)
IOH = 50 µA
IOH = 0.5 mA
Data Sheet
Temperature
Min
Typ
Max
Unit
LVDS
Full
Full
Full
Full
Full
Full
Full
Full
0.9
0.3
AGND
0.9
−5
−5
12
3.6
DVDD
1.4
+5
+5
1
16
20
V
V p-p
V
V
µA
µA
pF
kΩ
LVDS
Full
Full
Full
Full
Full
Full
Full
Full
0.9
0.3
AGND
0.9
−5
−5
8
Full
Full
Full
Full
Full
Full
1.22
0
−5
−100
Full
Full
Full
Full
Full
Full
1.22
0
45
−10
Full
Full
Full
Full
Full
Full
1.22
0
−10
−100
4
10
12
V
V
µA
µA
kΩ
pF
2.1
0.6
100
+10
V
V
µA
µA
kΩ
pF
2.1
0.6
+10
−45
V
V
µA
µA
kΩ
pF
750
1.05
mV
V
26
2
26
5
400
0.75
Full
Full
Full
1.79
1.75
CML
600
DRVDD/2
V
V p-p
V
V
µA
µA
pF
kΩ
2.1
0.6
+5
−45
26
2
Full
Full
Full
Rev. C | Page 8 of 45
3.6
AVDD
1.4
+5
+5
V
V
Data Sheet
AD6673
Parameter
Low Level Output Voltage (VOL)
IOL = 1.6 mA
IOL = 50 µA
1
2
Temperature
Full
Full
Full
Min
Typ
Max
Unit
0.2
0.05
V
V
Max
Unit
250
MSPS
ns
ns
ns
ns
2.2
2.1
1.0
0.16
ns
ns
ns
ns
ps rms
Full
25°C
25°C
25°C
L/(20 × M × fS)
50
0.78
25
Seconds
%
UI
µs
25°C
25°C
25°C
Full
10
250
50
5
µs
ms
ms
Multiframes
Full
5
Multiframes
Full
1
Multiframe
Pull-up.
Pull-down.
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Conversion Rate1
SYSREF± Setup Time to Rising Edge CLK±2
SYSREF± Hold Time from Rising Edge CLK±2
SYSREF± Setup Time to Rising Edge RFCLK2
SYSREF± Hold Time from Rising Edge RFCLK2
CLK± Pulse Width High
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-by-8 Mode
Aperture Delay
Aperture Uncertainty (Jitter)
DATA OUTPUT PARAMETERS
Data Output Period or Unit Interval (UI)
Data Output Duty Cycle
Data Valid Time
PLL Lock Time (tLOCK)
Wake-Up
Time (Standby)
Time ADC (Power-Down)3
Time Output (Power-Down)4
Subclass 0: SYNCINB± Falling Edge to First Valid K.28
Characters (Delay Required for Rx CGS Start)
Subclass 1: SYSREF± Rising Edge to First Valid K.28
Characters (Delay Required for SYNCB± Rising
Edge/Rx CGS Start)
CGS Phase K.28 Characters Duration
Pipeline Delay
JESD204B M1, L1 Mode (Latency)
JESD204B M1, L2 Mode (Latency)
JESD204B M2, L1 Mode (Latency)
JESD204B M2, L2 Mode (Latency)
Additional Pipeline Latency with NSR Enabled
Fast Detect (Latency)
Data Rate per Lane
Uncorrelated Bounded High Probability (UBHP) Jitter
Random Jitter at 5.0 Gbps
Output Rise/Fall Time
Differential Termination Resistance
Out-of-Range Recovery Time
Symbol
Temperature
Min
fS
tREFS
tREFH
tREFSRF
tREFHRF
tCH
Full
Full
Full
Full
Full
40
Full
Full
Full
Full
Full
1.8
1.9
0.8
tA
tJ
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
1
Typ
0.31
0
0.50
0
2.0
2.0
36
59
25
36
2
7
5.0
8
1.7
60
100
3
Conversion rate is the clock rate after the divider.
Refer to Figure 3 for timing diagram.
Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode.
4
Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode.
5
Cycles refers to ADC conversion rate cycles.
2
3
Rev. C | Page 9 of 45
Cycles5
Cycles
Cycles
Cycles
Cycles
Cycles
Gbps
ps
ps rms
ps
Ω
Cycles
AD6673
Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
SPI TIMING REQUIREMENTS (See Figure 56)
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
tSPI_RST
Test Conditions/Comments
Min
Typ
Max
Unit
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CS and SCLK
Hold time between CS and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge (not shown in figures)
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge (not shown in figures)
Time required after hard or soft reset until SPI access is available
(not shown in figures)
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
500
µs
Timing Diagrams
SAMPLE N
N – 36
N+1
N – 35
ANALOG
INPUT
SIGNAL
N – 34
N–1
N – 33
CLK–
CLK+
CLK–
CLK+
SERDOUT1±
SAMPLE N – 36
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE N – 35
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE N – 34
ENCODED INTO 2
8b/10b SYMBOLS
Figure 2. Data Output Timing
RFCLK
CLK+
SYSREF+
tREFS
tREFSRF
tREFH
SYSREF+
SYSREF–
SYSREF–
NOTES
1. CLOCK INPUT IS EITHER RFCLK OR CLK±, NOT BOTH.
Figure 3. SYSREF± Setup and Hold Timing
Rev. C | Page 10 of 45
tREFHRF
10632-003
CLK–
10632-002
SERDOUT0±
Data Sheet
AD6673
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
ELECTRICAL
AVDD to AGND
DRVDD to AGND
DVDD to DGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
RFCLK to AGND
VCM to AGND
CS, PDWN to AGND
SCLK to AGND
SDIO to AGND
RST to DGND
FDA, FDB to DGND
SERDOUT0+, SERDOUT0−,
SERDOUT1+, SERDOUT1− to AGND
SYNCINB+, SYNCINB− to DGND
SYSREF+, SYSREF− to AGND
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +85°C
150°C
The exposed paddle must be soldered to the ground plane for
the LFCSP package. This increases the reliability of the solder
joints, maximizing the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
48-Lead LFCSP
7 mm × 7 mm
(CP-48-13)
Airflow
Velocity
(m/sec)
0
1.0
2.5
θJA1, 2
25
22
20
θJC1, 3
2
θJB1, 4
14
Unit
°C/W
°C/W
°C/W
1
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-STD-883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
Typical θJA is specified for a 4-layer printed circuit board (PCB)
with a solid ground plane. As shown in Table 7, airflow increases
heat dissipation, which reduces θJA. In addition, metal in direct
contact with the package leads from metal traces, through holes,
ground, and power planes reduces the θJA.
ESD CAUTION
−65°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 11 of 45
AD6673
Data Sheet
48
47
46
45
44
43
42
41
40
39
38
37
AVDD
AVDD
VIN–B
VIN+B
AVDD
AVDD
VCM
AVDD
AVDD
VIN+A
VIN–A
AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
AD6673
TOP VIEW
(Not to Scale)
AVDD
DNC
PDWN
CS
SCLK
SDIO
DVDD
DNC
DNC
FDA
FDB
DVDD
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE
PACKAGE PROVIDES THE GROUND REFENCE FOR DRVDD
AND AVDD. THIS EXPOSED PADDLE MUST BE CONNECTED
TO GROUND FOR PROPER OPERATION.
10632-004
DVDD
SYNCINB+
SYNCINB–
DVDD
DGND
SERDOUT1+
SERDOUT1–
DRVDD
SERDOUT0–
SERDOUT0+
DGND
DVDD
13
14
15
16
17
18
19
20
21
22
23
24
AVDD 1
RFCLK 2
CLK– 3
CLK+ 4
AVDD 5
SYSREF+ 6
SYSREF– 7
AVDD 8
DVDD 9
RST 10
DVDD 11
DNC 12
Figure 4. Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
ADC Power Supplies
1, 5, 8, 36, 37, 40, 41, 43, 44, 47, 48
9, 11, 13, 16, 24, 25, 30
12, 28, 29, 35
17, 23
20
Exposed Paddle
ADC Analog
2
3
4
38
39
42
45
46
ADC Fast Detect Outputs
26
27
Digital Inputs
6
7
14
15
Mnemonic
Type
Description
AVDD
DVDD
DNC
DGND
DRVDD
Supply
Supply
AGND/DRGND
Ground
Analog Power Supply (1.8 V Nominal).
Digital Power Supply (1.8 V Nominal).
Do Not Connect.
Ground Reference for DVDD.
JESD204B PHY Serial Output Driver Supply (1.8 V Nominal).
Note that the DRVDD power is referenced to the AGND Plane.
The exposed thermal paddle on the bottom of the package
provides the ground reference for DRVDD and AVDD. This
exposed paddle must be connected to ground for proper
operation.
RFCLK
CLK−
CLK+
VIN−A
VIN+A
VCM
Input
Input
Input
Input
Input
Output
VIN+B
VIN−B
Input
Input
ADC RF Clock Input.
ADC Nyquist Clock Input—Complement.
ADC Nyquist Clock Input—True.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel A.
Common-Mode Level Bias Output for Analog Inputs. Decouple
this pin to ground using a 0.1 µF capacitor.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
FDB
FDA
Output
Output
Channel B Fast Detect Indicator (CMOS Levels).
Channel A Fast Detect Indicator (CMOS Levels).
SYSREF+
SYSREF−
SYNCINB+
SYNCINB−
Input
Input
Input
Input
JESD204B LVDS SYSREF Input—True
JESD204B LVDS SYSREF Input—Complement.
JESD204B LVDS SYNC Input—True
JESD204B LVDS SYNC Input—Complement.
Supply
Rev. C | Page 12 of 45
Data Sheet
Pin No.
Data Outputs
18
19
21
22
DUT Controls
10
31
32
33
34
AD6673
Mnemonic
Type
Description
SERDOUT1+
SERDOUT1−
SERDOUT0−
SERDOUT0+
Output
Output
Output
Output
Lane B CML Output Data—True.
Lane B CML Output Data—Complement.
Lane A CML Output Data—Complement.
Lane A CML Output Data—True.
RST
SDIO
SCLK
CS
PDWN
Input
Input/Output
Input
Input
Input
Digital Reset (Active Low).
SPI Serial Data I/O.
SPI Serial Clock.
SPI Chip Select (Active Low).
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as powerdown or standby (see Table 18).
Rev. C | Page 13 of 45
AD6673
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, sample rate is 250 MSPS, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS,
32k sample, TA = 25°C, link parameters used were M = 2 and L = 2, unless otherwise noted.
0
SNR: 66.5dBFS
SFDR: 84dBc
100
SNR/SFDR (dBc AND dBFS)
–20
AMPLITUDE (dBFS)
120
fIN: 90.1MHz
fS: 250MSPS
–40
–60
–80
–100
SFDR (dBFS)
80
SNR (dBFS)
60
SFDR (dBc)
40
20
50
100
FREQUENCY (MHz)
10632-005
0
–60
–40
–20
0
INPUT AMPLITUDE (dBFS)
100
fIN: 185.1MHz
fS: 250MSPS
SFDR, CHANNEL A (dBFS)
95
SNR/SFDR (dBc and dBFS)
SNR: 66.2dBFS
–20 SFDR: 84dBc
AMPLITUDE (dBFS)
–80
Figure 8. AD6673-250 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 185.1 MHz
Figure 5. AD6673-250 Single-Tone FFT with fIN = 90.1 MHz
0
0
–100
10632-008
SNR (dBc)
–120
–40
–60
–80
90
85
80
SFDR, CHANNEL B (dBFS)
75
SNR, CHANNEL A (dBFS)
70
–100
65
50
100
FREQUENCY (MHz)
100
200
300
400
FREQUENCY (MHz)
0
fIN: 305.1MHz
fS: 250MSPS
SNR: 65.5dBFS
–20 SFDR: 82dBc
SFDR (dBc)
SFDR/IMD (dBc and dBFS)
–20
–40
–60
–80
–40
IMD (dBc)
–60
SFDR (dBFS)
–80
–100
–100
–120
–120
–100
0
50
100
FREQUENCY (MHz)
Figure 7. AD6673-250 Single-Tone FFT with fIN = 305.1 MHz
–90
–80
–70
–60
–50
–40
–30
INPUT AMPLITUDE (dBFS)
–20
–10
0
10632-010
IMD (dBFS)
10632-007
AMPLITUDE (dBFS)
0
Figure 9. AD6673-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
Figure 6. AD6673-250 Single-Tone FFT with fIN = 185.1 MHz
0
60
10632-006
0
10632-009
SNR, CHANNEL B (dBFS)
–120
Figure 10. AD6673-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz
Rev. C | Page 14 of 45
Data Sheet
AD6673
0
100
SFDR, CHANNEL A (dBFS)
SFDR (dBc)
95
SFDR, CHANNEL B (dBFS)
SNR/SFDR (dBc AND dBFS)
SFDR/IMD (dBc and dBFS)
–20
–40
IMD (dBc)
–60
SFDR (dBFS)
–80
90
85
80
75
SNR, CHANNEL B (dBFS)
70
–100
65
IMD (dBFS)
–80
–70
–60
–50
–40
–30
SNR, CHANNEL A (dBFS)
–20
–10
0
INPUT AMPLITUDE (dBFS)
60
40
190
240
Figure 14. AD6673-250 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90.1 MHz
2,000,000
fS: 250MSPS
fIN1: 89.12MHz AT –7dBFS
fIN2: 92.12MHz AT –7dBFS
2,097,124 TOTAL HITS
1779257
1,800,000
–20 SFDR: 85dBc
1,600,000
–40
NUMBER OF HITS
AMPLITUDE (dBFS)
140
SAMPLE RATE (MSPS)
Figure 11. AD6673-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz
0
90
10632-014
–90
10632-011
–120
–100
–60
–80
1,400,000
1,200,000
1,000,000
800,000
600,000
400,000
–100
317867
50
100
FREQUENCY (MHz)
Figure 12. AD6673-250 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz
0
fS: 250MSPS
fIN1: 184.12MHz AT –7dBFS
fIN2: 187.12MHz AT –7dBFS
–40
–60
–80
–100
–120
0
50
100
FREQUENCY (MHz)
10632-013
AMPLITUDE (dBFS)
–20 SFDR: 84dBc
Figure 13. AD6673-250 Two-Tone FFT with fIN1 = 184.12 MHz,
fIN2 = 187.12 MHz
Rev. C | Page 15 of 45
0
N
N+1
OUTPUT CODE
Figure 15. AD6673-250 Grounded Input Histogram
10632-015
0
10632-012
200,000
–120
AD6673
Data Sheet
EQUIVALENT CIRCUITS
AVDD
AVDD
VIN+A
VIN+B
VIN–A
VIN–B
400Ω
SDIO
10632-022
10632-016
31kΩ
Figure 16. Equivalent Analog Input Circuit
Figure 20. Equivalent SDIO Circuit
AVDD
AVDD
AVDD
AVDD
0.9V
15kΩ
PDWN,
SCLK
15kΩ
CLK+
400Ω
31kΩ
10632-017
10632-021
CLK–
Figure 21. Equivalent SCLK or PDWN Input Circuit
Figure 17. Equivalent Clock lnput Circuit
DVDD
DRVDD
DRVDD
DRVDD
3mA
RTERM
SERDOUT0+
SERDOUT1+
DVDD
3mA
17kΩ
SERDOUT0–
SERDOUT1–
VCM
17kΩ
SYNCINB+
SYNCINB–
3mA
10632-217
10632-019
3mA
DVDD
0.9V
Figure 18. Digital CML Output Circuit
AVDD
Figure 22. Equivalent SYNCINB± Input Circuit
0.5pF
AVDD
INTERNAL
CLOCK DRIVER
RFCLK
AVDD
AVDD
0.9V
10kΩ
17kΩ
17kΩ
10632-317
BIAS
CONTROL
SYSREF–
10632-018
SYSREF+
Figure 19. Equivalent RF Clock lnput Circuit
Figure 23. Equivalent SYSREF± Input Circuit
Rev. C | Page 16 of 45
Data Sheet
AD6673
DVDD
AVDD
AVDD
DVDD
28kΩ
CS
400Ω
Figure 24. Equivalent CS Input Circuit
28kΩ
Figure 26. RST Equivalent Circuit
AVDD
10632-123
400Ω
VCM
400Ω
10632-126
10632-020
RST
Figure 25. Equivalent VCM Circuit
Rev. C | Page 17 of 45
AD6673
Data Sheet
THEORY OF OPERATION
The dual ADC design can be used for diversity reception of signals,
where the ADCs operate identically on the same carrier but from
two separate antennae. The ADCs can also be operated with
independent analog inputs. The user can sample frequencies
from dc to 300 MHz using appropriate low-pass or band-pass
filtering at the ADC inputs with little loss in ADC performance.
Operation to 400 MHz analog input is permitted but occurs at
the expense of increased ADC noise and distortion.
A synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD6673 are accomplished
using a 3-pin, SPI-compatible serial interface.
ADC ARCHITECTURE
The AD6673 architecture consists of a dual, front-end, sampleand-hold circuit, followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 11-bit result in the digital correction logic. Alternately, the
11-bit result can be processed through the NSR block before it
is sent to the digital correction logic.
The pipelined architecture permits the first stage to operate on
a new input sample and the remaining stages to operate on the
preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor digital-toanalog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-ended
modes. The output staging block aligns the data, corrects errors,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing digital output noise to
be separated from the analog core.
The AD6673 dual IF receiver can simultaneously digitize two
channels, making it ideal for diversity reception and digital
predistortion (DPD) observation paths in telecommunication
systems. The dual IF receiver design can be used for diversity
reception of signals, whereas the ADCs operate identically on
the same carrier but from two separate antennae. The ADCs can
also be operated with independent analog inputs. The user can
input frequencies from dc to 300 MHz using appropriate lowpass or band-pass filtering at the ADC inputs with little loss in
performance. Operation to a 400 MHz analog input is permitted;
however, it occurs at the expense of increased ADC noise and
distortion. A synchronization capability is provided to allow
synchronized timing between multiple devices. Programming
and control of the AD6673 are accomplished using a 3-wire
SPI-compatible serial interface.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6673 is a differential, switched
capacitor circuit that has been designed for optimum
performance while processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see the configuration shown in Figure 27).
When the input is switched into sample mode, the signal source
must be capable of charging the sampling capacitors and settling
within 1/2 clock cycle.
A small resistor in series with each input can help reduce the
peak transient current that is required from the output stage of
the driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, reduce
the shunt capacitors. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth.
Refer to the AN-742 Application Note, Frequency Domain
Response of Switched-Capacitor ADCs; the AN-827 Application
Note, A Resonant Approach to Interfacing Amplifiers to SwitchedCapacitor ADCs; and the Analog Dialogue article, “TransformerCoupled Front-End for Wideband A/D Converters,” for more
information on this subject.
BIAS
S
S
CFB
CS
VIN+
CPAR1
CPAR2
S
S
H
CS
VIN–
CPAR1
CPAR2
S
CFB
S
BIAS
10632-023
The AD6673 has two analog input channels and two JESD204B
output lanes. The signal passes through several stages before
appearing at the output port(s).
Figure 27. Switched-Capacitor Input
For best dynamic performance, match the source impedances
driving VIN+ and VIN− and differentially balance the inputs.
Rev. C | Page 18 of 45
Data Sheet
AD6673
Input Common Mode
C2
The analog inputs of the AD6673 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD (or
0.9 V) is recommended for optimum performance. An on-board
common-mode voltage reference is included in the design and is
available from the VCM pin. Using the VCM output to set the
input common mode is recommended. Optimum performance
is achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically 0.5 × AVDD). Decouple
the VCM pin to ground by using a 0.1 µF capacitor, as described
in the Applications Information section. Place this decoupling
capacitor close to the pin to minimize the series resistance and
inductance between the part and this capacitor.
R3
VIN–
33Ω
15Ω
VCM
15pF
0.1µF
10632-024
200Ω
33Ω
Table 9. Example RC Network
Figure 28. Differential Input Configuration Using the ADA4930-2
Frequency
Range
(MHz)
0 to 100
100 to 300
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 29. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
C1
Differential
(pF)
8.2
3.9
R1
Series
(Ω)
33
15
C2
R3
R1
0.1µF
0.1µF
R2
2V p-p
VIN+
33Ω
S
S
P
ADC
C1
0.1µF
33Ω
0.1µF
R1
R2
R3
VIN–
33Ω
C2
Figure 30. Differential Double Balun Input Configuration
Rev. C | Page 19 of 45
VCM
0.1µF
10632-026
P
0.1µF
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters,
the value of the input resistors and capacitors may need to be
adjusted or some components may need to be removed. Table 9
displays recommended values to set the RC network for different
input frequency ranges. However, these values are dependent on
the input signal and bandwidth and should be used only as a
starting guide. Note that the values given in Table 9 are for each R1,
R2, C1, C2, and R3 components shown in Figure 29 and Figure 30.
AVDD
VIN+
120Ω
33Ω
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD6673. For applications where
SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 30). In this
configuration, the input is ac-coupled and the VCM voltage is
provided to each input through a 33 Ω resistor. These resistors
compensate for losses in the input baluns to provide a 50 Ω
impedance to the driver.
ADC
ADA4930-2
R3
VCM
Consider the signal characteristics when selecting a transformer.
Most RF transformers saturate at frequencies below a few
megahertz. Excessive signal power can also cause core
saturation, which leads to distortion.
5pF
0.1µF
VIN–
Figure 29. Differential Transformer-Coupled Configuration
200Ω
15Ω
ADC
R2
C2
15pF
33Ω
C1
0.1µF
The output common-mode voltage of the ADA4930-2 is easily
set with the VCM pin of the AD6673 (see Figure 28), and the
driver can be configured in a Sallen-Key filter topology to
provide band-limiting of the input signal.
90Ω
49.9Ω
R1
Optimum performance is achieved while driving the AD6673 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-2, ADA4938-2, and ADA4930-2 differential
drivers provide excellent performance and a flexible interface to
the ADC.
76.8Ω
VIN+
10632-025
2V p-p
Differential Input Configurations
VIN
R2
R1
R2
Series
(Ω)
0
0
C2
Shunt
(pF)
15
8.2
R3
Shunt
(Ω)
24.9
24.9
AD6673
Data Sheet
AVDD
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use an amplifier with variable
gain. The AD8375 or AD8376 digital variable gain amplifier
(DVGA) provides good performance for driving the AD6673.
Figure 31 shows an example of the AD8376 driving the AD6673
through a band-pass antialiasing filter.
4pF
10632-028
165Ω
VPOS
5.1pF
1nF
4pF
Figure 32. Equivalent Nyquist Clock Input Circuit
ADC
3.9pF
301Ω
15pF
VCM
165Ω
1nF
20kΩ║2.5pF
68nH
10632-027
1000pF 180nH 220nH
NOTES
1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS WITH THE
EXCEPTION OF THE 1µH CHOKE INDUCTORS (COILCRAFT 0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER
CENTERED AT 140MHz.
Figure 31. Differential Input Configuration Using the AD8376
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD6673.
The full-scale input range can be adjusted by varying the reference
voltage via the SPI. The input span of the ADC tracks the
reference voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
The AD6673 has two options for deriving the input sampling
clock, a differential Nyquist sampling clock input or an RF clock
input (which is internally divided by 4). The clock input is selected
in Register 0x09 and, by default, is configured for the Nyquist clock
input. For optimum performance, clock the AD6673 Nyquist
sample clock input, CLK+ and CLK−, with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased internally
(see Figure 32) and require no external bias. If the clock inputs
are floated, CLK− is pulled slightly lower than CLK+ to prevent
spurious clocking.
For applications where a single-ended low jitter clock between
40 MHz to 200 MHz is available, an RF transformer is recommended. An example using an RF transformer in the clock
network is shown in Figure 33. At frequencies above 200 MHz,
an RF balun is recommended, as seen in Figure 34. The back-toback Schottky diodes across the transformer secondary limit
clock excursions into the AD6673 to approximately 0.8 V p-p
differential. This limit helps prevent the large voltage swings of
the clock from feeding through to other portions of the AD6673,
yet preserves the fast rise and fall times of the clock, which are
critical to low jitter performance.
The Nyquist clock input pins, CLK+ and CLK−, are internally
biased to 0.9 V and have a typical input impedance of 4 pF in
parallel with 10 kΩ (see Figure 32). The input clock is typically
ac-coupled to CLK+ and CLK−. Some typical clock drive circuits
are presented in Figure 33 through Figure 36 for reference.
50Ω
ADC
CLK+
100Ω
390pF
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 33. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLOCK
INPUT
390pF
25Ω
ADC
390pF
CLK+
390pF
1nF
CLK–
25Ω
Nyquist Clock Input Options
The AD6673 Nyquist clock input supports a differential clock
between 40 MHz to 625 MHz. The clock input structure supports
differential input voltages from 0.3 V to 3.6 V and is therefore
compatible with various logic family inputs, such as CMOS,
LVDS, and LVPECL. A sine wave input is also accepted, but
higher slew rates typically provide optimal performance. Clock
source jitter is a critical parameter that can affect performance, as
described in the Jitter Considerations section. If the inputs are
floated, pull the CLK− pin low to prevent spurious clocking.
390pF
CLOCK
INPUT
Mini-Circuits®
ADT1-1WT, 1:1Z
390pF
XFMR
10632-029
1µH
CLK–
180nH 220nH
1µH
AD8376
CLK+
SCHOTTKY
DIODES:
HSMS2822
10632-030
1000pF
0.9V
Figure 34. Balun-Coupled Differential Clock (Up to 625 MHz)
In some cases, it is desirable to buffer or generate multiple
clocks from a single source. In those cases, Analog Devices, Inc.,
offers clock drivers with excellent jitter performance. Figure 35
shows a typical PECL driver circuit that uses PECL drivers such
as the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515,
AD9516-0, AD9516-1, AD9516-2, AD9516-3, AD9516-4,
AD9516-5, AD9517-0, AD9517-1, AD9517-2, AD9517-3,
AD9517-4, AD9518-0, AD9518-1, AD9518-2, AD9518-3,
AD9518-4, AD9520-0, AD9520-1, AD9520-2, AD9520-3,
AD9520-4, AD9520-5, AD9522-0, AD9522-1, AD9522-2,
AD9522-3, AD9522-4, AD9522-5, AD9523, AD9524, ADCLK905,
ADCLK907, and ADCLK925.
Rev. C | Page 20 of 45
Data Sheet
AD6673
1pF
CLK+
AD95xx
100Ω
10kΩ
0.1µF
CLK–
50kΩ
240Ω
50kΩ
240Ω
BIAS
CONTROL
Figure 37. Equivalent RF Clock Input Circuit
Figure 35. Differential PECL Sample Clock (Up to 625 MHz)
It is recommended that the RF clock input of the AD6673 be
driven with a PECL or sine wave signal with a minimum signal
amplitude of 600 mV peak to peak. Regardless of the type of
signal being used, clock source jitter is of the most concern, as
described in the Jitter Considerations section. Figure 38 shows the
preferred method of clocking when using the RF clock input on
the AD6673. It is recommended that a 50 Ω transmission line
be used to route the clock signal to the RF clock input of the
AD6673 due to the high frequency nature of the signal and
terminate the transmission line close to the RF clock input.
Analog Devices also offers LVDS clock drivers with excellent
jitter performance. A typical circuit is shown in Figure 36 and
uses LVDS drivers such as the AD9510, AD9511, AD9512,
AD9513, AD9514, AD9515, AD9516-0, AD9516-1, AD9516-2,
AD9516-3, AD9516-4, AD9516-5, AD9517-0, AD9517-1,
AD9517-2, AD9517-3, AD9517-4, AD9518-0, AD9518-1,
AD9518-2, AD9518-3, AD9518-4, AD9520-0, AD9520-1,
AD9520-2, AD9520-3, AD9520-4, AD9520-5, AD9522-0,
AD9522-1, AD9522-2, AD9522-3, AD9522-4, AD9522-5,
AD9523, and AD9524.
0.1µF
0.1µF
CLOCK
INPUT
0.1µF
RF CLOCK
INPUT
100Ω
0.1µF
LVDS DRIVER
50Ω Tx LINE
RFCLK
CLK–
50kΩ
0.1µF
50Ω
50kΩ
10632-032
CLOCK
INPUT
ADC
ADC
CLK+
AD95xx
10632-033
PECL DRIVER
Figure 38. Typical RF Clock Input Circuit
Figure 39 shows the RF clock input of the AD6673 being driven
from the LVPECL outputs of the AD9515. The differential
LVPECL output signal from the AD9515 is converted to a singleended signal using an RF balun or RF transformer. The RF balun
configuration is recommended for clock frequencies associated
with the RF clock input.
Figure 36. Differential LVDS Sample Clock (Up to 625 MHz)
RF Clock Input Options
The AD6673 RF clock input supports a single-ended clock
between 625 GHz to 1.5 GHz. The equivalent RF clock input
circuit is shown in Figure 37. The input is self biased to 0.9 V and is
typically ac-coupled. The input has a typical input impedance of
10 kΩ in parallel with 1 pF at the RFCLK pin.
VDD
127Ω
0.1µF
ADC
127Ω
0.1µF
50Ω Tx LINE
0.1µF
RFCLK
CLOCK INPUT
AD9515
0.1µF
50Ω
LVPECL
DRIVER
0.1µF
CLOCK INPUT
82.5Ω
82.5Ω
Figure 39. Differential PECL RF Clock Input Circuit
Rev. C | Page 21 of 45
10632-035
0.1µF
INTERNAL
CLOCK DRIVER
RFCLK
10632-031
CLOCK
INPUT
ADC
0.1µF
10632-034
0.1µF
CLOCK
INPUT
AD6673
Data Sheet
Input Clock Divider
Jitter Considerations
The AD6673 contains an input clock divider with the ability to
divide the Nyquist input clock by integer values between 1 and 8.
The RF clock input uses an on-chip predivider to divide the clock
input by four before it reaches the 1-to-8 divider. This allows for
higher input frequencies to be achieved on the RF clock input. The
divide ratios can be selected using Register 0x09 and Register 0x0B.
Register 0x09 is used to set the RF clock input, and Register 0x0B
can be used to set the divide ratio of the 1-to-8 divider for both
the RF clock input and the Nyquist clock input. For divide ratios
other than 1, the duty-cycle stabilizer is automatically enabled.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input frequency
(fIN) due to jitter (tJ) can be calculated by
SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 ( − SNRLF /10) ]
In the equation, the rms aperture jitter represents the root-meansquare of all jitter sources, which include the clock input, the
analog input signal, and the ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter,
as shown in Figure 41.
70
÷4
68
÷1 TO ÷8
DIVIDER
66
10632-036
64
Figure 40. AD6673 Clock Divider Circuit
The AD6673 clock divider can be synchronized using the external
system reference (SYSREF) input. Bit 1 and Bit 2 of Register 0x3A
allow the clock divider to be resynchronized on every SYSREF
signal or only on the first signal after the register is written. A
valid SYSREF causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
SNR (dBc)
NYQUIST
CLOCK
The AD6673 contains a DCS that retimes the nonsampling (falling)
edge, providing an internal clock signal with a nominal 50% duty
cycle. This allows the user to provide a wide range of clock input
duty cycles without affecting the performance of the AD6673.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The duty
cycle control loop does not function for clock rates of less than
40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate can change
dynamically. A wait time of 1.5 µs to 5 µs is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time that the
loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
60
58
56
0.05 ps
0.20 ps
0.50 ps
1.00 ps
1.50 ps
MEASURED
54
52
50
1
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
62
10
100
INPUT FREQUENCY (MHz)
1000
10632-037
RFCLK
Figure 41. AD6673-250 SNR vs. Input Frequency and Jitter
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD6673. Separate the
power supplies for the clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter, crystal controlled oscillators make the best clock
sources. If the clock is generated from another type of source (by
gating, dividing, or another method), retime it by the original
clock at the last step.
Refer to the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance, and the AN-756 Application Note,
Sampled Systems and the Effects of Clock Phase Noise and Jitter, for
more information about jitter performance as it relates to ADCs.
Rev. C | Page 22 of 45
Data Sheet
AD6673
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 42, the power dissipated by the AD6673 is
proportional to its sample rate. The data in Figure 42 was taken
using the same operating conditions as those used for the Typical
Performance Characteristics section.
0.8
0.7
TOTAL POWER
0.5
POWER (AVDD)
0.4
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section and the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI, for additional details.
0.3
POWER (DVDD + DRVDD)
0.2
0.1
0
40
90
140
190
ENCODE FREQUENCY (MSPS)
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
240
10632-038
TOTAL POWER (W)
0.6
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD6673 is placed in power-down mode.
In this state, the ADC typically dissipates about 9 mW. Asserting the
PDWN pin low returns the AD6673 to its normal operating mode.
Figure 42. AD6673-250 Power vs. Encode Rate
Rev. C | Page 23 of 45
AD6673
Data Sheet
NOISE SHAPING REQUANTIZER
fS = 250MSPS
fIN = 185.1MHz AT –1dBFS
SNR = 74.3dB
SFDR = 85dBc
–20
Two different bandwidth modes are provided; the mode can be
selected from the SPI port. In each of the two modes, the center
frequency of the band can be tuned such that IFs can be placed
anywhere in the Nyquist band.
–40
–60
–80
–100
–120
22% BANDWIDTH MODE (>40 MHz AT
184.32 MSPS)
0
50
100
FREQUENCY (MHz)
10632-040
The NSR feature can be independently controlled per channel
via the SPI.
0
AMPLITUDE (dBFS)
The AD6673 features a NSR to allow higher than 11-bit SNR to
be maintained in a subset of the Nyquist band. The harmonic
performance of the receiver is unaffected by the NSR feature. When
enabled, the NSR contributes an additional 0.6 dB of loss to the
input signal, such that a 0 dBFS input is reduced to −0.6 dBFS at
the output pins.
Figure 44. 22% Bandwidth Mode, Tuning Word = 28 (fS/4 Tuning)
0
fS = 250MSPS
fIN = 185.1MHz AT –1dBFS
SNR = 74.3dB
SFDR = 85dBc
–20
AMPLITUDE (dBFS)
The first bandwidth mode offers excellent noise performance
over 22% of the ADC sample rate (44% of the Nyquist band) and
can be centered by setting the NSR mode bits in the NSR control
register (Address 0x3C) to 0. In this mode, the useful frequency
range can be set using the 6-bit tuning word in the NSR tuning
register (Address 0x3E). There are 57 possible tuning words
(TW); each step is 0.5% of the ADC sample rate. The following
three equations describe the left band edge (f0), the channel
center (fCENTER), and the right band edge (f1), respectively:
f0 = fADC × .005 × TW
–40
–60
–80
–100
–120
f1 = f0 + 0.22 × fADC
Figure 43 to Figure 45 show the typical spectrum that can be
expected from the AD6673 in the 22% bandwidth mode for
three different tuning words.
0
fS = 250MSPS
fIN = 185.1MHz AT –1dBFS
SNR = 74dB
SFDR = 85dBc
AMPLITUDE (dBFS)
–20
–40
–60
–80
0
–120
0
50
100
10632-039
–100
Figure 43. 22% Bandwidth Mode, Tuning Word = 13
Rev. C | Page 24 of 45
0
50
100
FREQUENCY (MHz)
Figure 45. 22% Bandwidth Mode, Tuning Word = 41
10632-041
fCENTER = f0 + 0.11 × fADC
Data Sheet
AD6673
33% BANDWIDTH MODE (>60 MHz AT
184.32 MSPS)
0
–60
–80
0
50
100
FREQUENCY (MHz)
Figure 47. 33% Bandwidth Mode, Tuning Word = 17 (fS/4 Tuning)
f1 = f0 + 0.33 × fADC
0
–20
AMPLITUDE (dBFS)
0
fS = 250MSPS
fIN = 185.1MHz AT –1dBFS
SNR = 72dB
SFDR = 85dBc
–40
fS = 250MSPS
fIN = 185.1MHz AT –1dBFS
SNR = 72dB
SFDR = 85dBc
–40
–60
–80
–60
–100
–80
–120
0
50
100
FREQUENCY (MHz)
–100
–120
50
100
FREQUENCY (MHz)
10632-042
Figure 48. 33% Bandwidth Mode, Tuning Word = 27
Figure 46. 33% Bandwidth Mode, Tuning Word = 5
Rev. C | Page 25 of 45
10632-044
Figure 46 to Figure 48 show the typical spectrum that can be
expected from the AD6673 in the 33% bandwidth mode for
three different tuning words.
0
10632-043
–120
fCENTER = f0 + 0.165 × fADC
AMPLITUDE (dBFS)
–40
–100
f0 = fADC × .005 × TW
–20
SNR = 72dB
SFDR = 85dBc
–20
AMPLITUDE (dBFS)
The second bandwidth mode offers excellent noise performance
over 33% of the ADC sample rate (66% of the Nyquist band) and
can be centered by setting the NSR mode bits in the NSR control
register (Address 0x3C) to 1. In this mode, the useful frequency
range can be set using the 6-bit tuning word in the NSR tuning
register (Address 0x3E). There are 57 possible tuning words (TW);
each step is 0.5% of the ADC sample rate. The following three
equations describe the left band edge (f0), the channel center
(fCENTER), and the right band edge (f1), respectively:
fS = 250MSPS
fIN = 185.1MHz AT –1dBFS
AD6673
Data Sheet
DIGITAL OUTPUTS
JESD204B TRANSMIT TOP LEVEL DESCRIPTION
The AD6673 digital output uses the JEDEC Standard No.
JESD204B, Serial Interface for Data Converters. JESD204B is a
protocol to link the AD6673 to a digital processing device over a
serial interface of up to 5 Gbps link speeds (2.75 Gbps, 11-bit ADC
data rate). The benefits of the JESD204B interface include a
reduction in required board area for data interface routing and
the enabling of smaller packages for converter and logic devices.
The AD6673 supports single or dual lane interfaces.
JESD204B OVERVIEW
The JESD204B data transmit block assembles the parallel data from
the ADC into frames and uses 8b/10b encoding as well as optional
scrambling to form serial output data. Lane synchronization is
supported using special characters during the initial establishment
of the link, and additional synchronization is embedded in the
data stream thereafter. A matching external receiver is required
to lock onto the serial data stream and recover the data and clock.
For additional details on the JESD204B interface, refer to the
JESD204B standard.
The AD6673 JESD204B transmit block maps the output of the
two ADCs over a link. A link can be configured to use either
single or dual serial differential outputs that are called lanes.
The JESD204B specification refers to a number of parameters to
define the link, and these parameters must match between the
JESD204B transmitter (AD6673 output) and receiver.
The JESD204B link is described according to the following
parameters:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
S = samples transmitted/single converter/frame cycle
(AD6673 value = 1)
M = number of converters/converter device
(AD6673 value = 2 by default, or can be set to 1)
L = number of lanes/converter device
(AD6673 value = 1 or 2)
N = converter resolution (AD6673 value = 11)
N’ = total number of bits per sample (AD6673 value = 16)
CF = number of control words/frame clock cycle/converter
device (AD6673 value = 0)
CS = number of control bits/conversion sample
(configurable on the AD6673 up to 2 bits)
K = number of frames per multiframe (configurable on
the AD6673)
HD = high density mode (AD6673 value = 0)
F = octets/frame (AD6673 value = 2 or 4, dependent upon
L = 2 or 1)
C = control bit (overrange, overflow, underflow; available
on the AD6673)
T = tail bit (available on the AD6673)
SCR = scrambler enable/disable (configurable on the AD6673)
FCHK = checksum for the JESD204B parameters
(automatically calculated and stored in register map)
Figure 49 shows a simplified block diagram of the AD6673
JESD204B link. By default, the AD6673 is configured to use
two converters and two lanes. Converter A data is output to
SERDOUT0+/SERDOUT0−, and Converter B is output to
SERDOUT1+/SERDOUT1−. The AD6673 allows for other
configurations such as combining the outputs of both converters
onto a single lane or changing the mapping of the A and B
digital output paths. These modes are setup through a quick
configuration register in the SPI register map, along with
additional customizable options.
By default in the AD6673, the 11-bit converter word from each
converter is broken into two octets (8 bits of data). Bit 13 (MSB)
through Bit 6 are in the first octet (Bits[13:11] are Logic 0). The
second octet contains Bit 5 through Bit 0 (LSB), and two tail bits
are added to fill the second octet. The tail bits can be configured
as zeros, pseudorandom number sequences, or control bits
indicating overrange, underrange, or valid data conditions.
The two resulting octets can be scrambled. Scrambling is
optional; however, it is available to avoid spectral peaks when
transmitting similar digital data patterns. The scrambler uses a
self synchronizing, polynomial-based algorithm defined by the
equation 1 + x14 + x15. The descrambler in the receiver should be
a self-synchronizing version of the scrambler polynomial.
The two octets are then encoded with an 8b/10b encoder. The
8b/10b encoder works by taking eight bits of data (an octet) and
encoding them into a 10-bit symbol. Figure 50 shows how the
11-bit data is taken from the ADC, the tail bits are added, the two
octets are scrambled, and how the octets are encoded into two
10-bit symbols. Figure 50 illustrates the default data format.
At the data link layer, in addition to the 8b/10b encoding, the
character replacement is used to allow the receiver to monitor
frame alignment. The character replacement process occurs on the
frame and multiframe boundaries, and implementation depends
on which boundary is occurring, and if scrambling is enabled.
If scrambling is disabled, the following applies. If the last scrambled
octet of the last frame of the multiframe equals the last octet of
the previous frame, the transmitter replaces the last octet with
the control character /A/ = /K28.3/. On other frames within the
multiframe, if the last octet in the frame equals the last octet of
the previous frame, the transmitter replaces the last octet with
the control character /F/= /K28.7/.
If scrambling is enabled, the following applies. If the last octet of
the last frame of the multiframe equals 0x7C, the transmitter
replaces the last octet with the control character /A/ = /K28.3/.
On other frames within the multiframe, if the last octet equals
0xFC, the transmitter replaces the last octet with the control
character /F/ = /K28.7/.
Refer to JEDEC Standard No. 204B-July 2011 for additional
information about the JESD204B interface. Section 5.1 covers
the transport layer and data format details, and Section 5.2
covers scrambling and descrambling.
Rev. C | Page 26 of 45
Data Sheet
AD6673
SYNCHRONIZATION
11. Enable the JESD204B receiver, and initiate a link.
The AD6673 requires internal synchronization to process the
ADC data and produce a JESD204B output. To accommodate
extreme temperature changes and inconsistent power-up
conditions that may occur, the timing of these circuits requires
an additional margin. To increase the timing margin, a
procedure is required to maintain internal timing
synchronization and JESD204B link quality.
Subclass 0 and Harmonic Input Clock
There are four specific cases to consider: JESD204B Subclass 0
or Subclass 1 operation, and Nyquist or harmonic clocking.
Harmonic clocking uses an input clock, where the AD6673
internal clock divider can be set to divide by a multiple of
between 2 and 8 of the ADC sample rate (using Register 0x0B).
See Table 14 for a description of how the JESD204B link modes
of operation are configured using Register 0x3A.
Subclass 0 and Nyquist Input Clock
For Subclass 0 and Nyquist input clock (deterministic latency is
not required and an external SYSREF signal is not used),
1.
Apply power to the AD6673. Allow the voltages and clocks
to stabilize.
2. Apply a soft reset by writing 0x3C to Register 0x00.
3. Wait at least 500 µs.
4. Set Register 0xEE and Register 0xEF to 0x80.
5. Configure the AD6673 as desired, including the JESD204B
parameters. Configure the link setup parameters (see the
Link Setup Parameters section).
6. Establish an internal local multiframe clock (LMFC)
within the AD6673 by writing 0xFF to Register 0xF3.
7. Wait at least six LMFCs.
8. Perform the clock adjustment register writes (see the Clock
Adjustment Register Writes section).
9. Wait at least six LMFCs.
10. Enable the JESD204B receiver, and initiate a link.
For Subclass 0 and the harmonic input clock,
1.
Apply power to the AD6673. Allow the voltages and clocks
to stabilize.
2. Assert a power-down by either using the PDWN input or
by setting Register 0x08 to 0x05.
3. Configure the proper clock divide setting in Register 0x0B.
Commit the clock divide setting by writing 0x01 to
Register 0xFF.
4. Set Register 0xEE and Register 0xEF to 0x80.
5. Configure the AD6673 as desired including the JESD204B
parameters. Configure the link setup parameters (see the
Link Setup Parameters section).
6. Deassert the power-down, and wait at least 250 ms.
7. Force an internal alignment within the AD6673 by writing
0xFF to Register 0xF3.
8. Wait at least six LMFCs.
9. Perform the clock adjustment register writes (see the Clock
Adjustment Register Writes section).
10. Wait at least six LMFCs.
11. Enable the JESD204B receiver, and initiate a link.
Subclass 1 and Harmonic Input Clock
For Subclass 1 and the harmonic input clock,
1.
2.
3.
4.
5.
Subclass 1 and Nyquist Input Clock
For Subclass 1 and the Nyquist input clock (when deterministic
latency is required and an external SYSREF is used),
1.
Apply power to the AD6673. Allow the voltages and clocks
to stabilize.
2. Apply a soft reset by writing 0x3C to Register 0x00.
3. Wait at least 500 µs.
4. Set Register 0xEE and Register 0xEF to 0x80.
5. Configure the AD6673 as desired including the JESD204B
parameters. Configure the link setup parameters (see the
Link Setup Parameters section).
6. Force an internal alignment within the AD6673 by writing
0xFF to Register 0xF3.
7. Wait at least six LMFCs.
8. Establish a LMFC within the AD6673 by providing a
SYSREF signal.
9. Perform the clock adjustment register writes (see the Clock
Adjustment Register Writes section).
10. Wait at least six LMFCs.
6.
7.
8.
9.
10.
11.
12.
13.
Apply power to the AD6673. Allow the voltages and clocks
to stabilize.
Assert a power-down by either using the PDWN input or
by setting Register 0x08 to 0x05.
Configure the proper clock divide setting in Register 0x0B.
Commit the clock divide setting by writing 0x01 to
Register 0xFF.
Set Register 0xEE and Register 0xEF to 0x80.
Configure the AD6673 as desired including the JESD204B
parameters. Configure the link setup parameters (see the
Link Setup Parameters section).
Deassert the power-down, and wait at least 250 ms.
Force an internal alignment within the AD6673 by writing
0xFF to Register 0xF3.
Wait at least six LMFCs.
Set the LMFC using the SYSREF signal for JESD204B
Subclass 1 operation.
Perform the clock adjustment register writes (see the Clock
Adjustment Register Writes section).
Enable the JESD204B receiver, and initiate a link.
Wait at least six LMFCs.
Bring the JESD204B receiver out of reset.
If the AD6673 has been configured for continuous SYSREF± mode
of operation using Register 0x3A, Bit 2 = 1, it is important to
disable the internal SYSREF± buffer by setting Register 0x3A,
Bit 0 = 0, to remove the impact of external false triggers that
affects the digital path.
Rev. C | Page 27 of 45
AD6673
Data Sheet
Clock Adjustment Register Writes
transmit four multiframes. Dummy samples are inserted between
the required characters so that full multiframes are transmitted.
The four multiframes include the following:
Perform the clock adjustment writes in the following order:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Set Register 0xEE to 0x81.
Set Register 0xEF to 0x81.
Set Register 0xEE to 0x82.
Set Register 0xEF to 0x82.
Set Register 0xEE to 0x83.
Set Register 0xEF to 0x83.
Set Register 0xEE to 0x84.
Set Register 0xEF to 0x84.
Set Register 0xEE to 0x85.
Set Register 0xEF to 0x85.
Set Register 0xEE to 0x86.
Set Register 0xEF to 0x86.
Set Register 0xEE to 0x87.
Set Register 0xEF to 0x87.
•
•
•
•
Multiframe 1: Begins with an /R/ character [K28.0] and
ends with an /A/ character [K28.3].
Multiframe 2: Begins with an /R/ character followed by a /Q/
[K28.4] character, followed by link configuration parameters
over 14 configuration octets (see Table 10), and ends with
an /A/ character. Many of the values of the parameters are
of the notation of the value – 1.
Multiframe 3: Is the same as Multiframe 1.
Multiframe 4: Is the same as Multiframe 1.
Data Transmission Phase
In the data transmission phase, frame alignment is monitored
with control characters. Character replacement is used at the
end of frames. Character replacement in the transmitter occurs
in the following instances:
JESD204B Synchronization Details
The AD6673 supports JESD204B Subclass 0 and Subclass 1, and
establishes synchronization of the link through one or two control
signals, SYNC and, for Subclass 1, SYSREF, and a common device
clock. SYSREF and SYNC are common to all converter devices
for alignment purposes at the system level.
•
The synchronization process is accomplished over three phases:
code group synchronization (CGS), initial lane alignment sequence
(ILAS), and data transmission. If scrambling is enabled, the bits are
not actually scrambled until the data transmission phase, and
the CGS phase and ILAS phase do not use scrambling.
Table 10. Fourteen Configuration Octets of the ILAS Phase
CGS Phase
In the CGS phase, the JESD204B transmit block transmits
/K28.5/ characters. The receiver (external logic device) must
locate K28.5 characters in its input data stream using clock and
data recovery (CDR) techniques.
When in Subclass 1 mode, the receiver locks on to the K28.5
characters. Once detected, the receiver initiates a SYSREF edge
so that the AD6673 transmit data establishes an LMFC internally.
The SYSREF edge also resets any sampling edges within the ADC
to align sampling instances to the LMFC. This is important to
maintain synchronization across multiple devices.
At the internal clock of the next receiver, if Subclass 0, or at the
LMFC boundary of the next receiver, if Subclass 1, the receiver
or logic device deasserts the SYNC~ signal (SYNCINB± goes
high), and the transmitter block begins the ILAS phase.
ILAS Phase
•
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
If scrambling is disabled and the last octet of the frame or
multiframe equals the octet value of the previous frame.
If scrambling is enabled and the last octet of the multiframe is
equal to 0x7C, or the last octet of a frame is equal to 0xFC.
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4 Bit 3
DID[7:0]
Bit 2
Bit 1
Bit 0
(LSB)
BID[3:0]
LID[4:0]
L[4:0]
SCR
F[7:0]
K[4:0]
M[7:0]
CS[1:0]
SUBCLASS[2:0]
JESDV[2:0]
HD
N[4:0]
N’[4:0]
S[4:0]
CF[4:0]
Reserved, Don’t Care
Reserved, Don’t Care
FCHK[7:0]
Link Setup Parameters
The following sections demonstrate how to configure the
AD6673 JESD204B interface paremeters. These details are a
subset of the setup details provided in the Synchronization
section. The steps to configure the output include the following:
In the ILAS phase, the transmitter sends out a known pattern,
and the receiver aligns all lanes of the link and verifies the
parameters of the link.
1.
2.
3.
4.
The ILAS phase begins after SYNC~ has been deasserted (goes
high). If Subclass 0, the transmitter begins ILAS at the internal
clock of the next transmitter. If Subclass 1, at the LMFC boundary of the next transmitter, the transmit block begins to
5.
6.
Rev. C | Page 28 of 45
Disable the lanes before changing the configuration.
Select the quick configuration option.
Configure the detailed options.
Verify FCHK, the checksum of the JESD204B interface
parameters.
Set additional digital output configuration options.
Reenable the lane(s).
Data Sheet
AD6673
•
Disable Lanes Before Changing Configuration
Before modifying the JESD204B link parameters, disable the
link and hold it in reset. This is accomplished by writing Logic 1
to Register 0x5F, Bit 0.
The JESD204B specification also calls for the number of
octets per multiframe (K × F) to be between 17 and 1024.
The F value is fixed through the quick configuration
setting to ensure that this relationship is true.
Select Quick Configuration Option
Table 11. JESD204B Configurable Identification Values
Write to Register 0x5E, the 204B quick configuration register, to
select the configuration options. See Table 13 for configuration
options and resulting JESD204B parameter values.
DID Value
LID (Lane 0)
LID (Lane 1)
DID
BID
•
•
•
•
0x11 = one converter, one lane
0x12 = one converter, two lanes
0x21 = two converters, one lane
0x22 = two converters, two lanes
•
Configure the tail bits and control bits.
•
•
With N’ = 16 and N = 11, there are two bits available per
sample for transmitting additional information over the
JESD204B link. The options are tail bits or control bits. By
default, tail bits of 0b00 value are used.
Tail bits are dummy bits sent over the link to complete the
two octets and do not convey any information about the input
signal. Tail bits can be fixed zeros (default) or pseudorandom
numbers (Register 0x5F, Bit 6).
One or two control bits can be used instead of the tail bits
through Register 0x72, Bits[7:6]. The tail bits can be set
using Register 0x14, Bits[7:5], and tail bits can be enabled
using Address 0x5F, Bit 6.
Set lane identification values.
•
•
•
Per the JESD204B specification, a multiframe is defined as a
group of K successive frames, where K is between 1 and 32,
and it requires that the number of octets be between 17 and
1024. The K value is set to 32 by default in Register 0x70,
Bits[7:0]. Note that the K value is the register value plus 1.
The K value can be changed; however, it must comply with
a few conditions. The AD6673 uses a fixed value for octets
per frame [F] based on the JESD204B quick configuration
setting. K must also be a multiple of 4 and conform to the
following equation:
32 ≥ K ≥ Ceil (17/F)
Scrambling can be enabled or disabled by setting Register 0x6E,
Bit 7. By default, scrambling is enabled. Per the JESD204B
protocol, scrambling is functional only after the lane
synchronization has completed.
Select lane synchronization options.
Most of the synchronization features of the JESD204B interface
are enabled by default for typical applications. In some cases,
these features can be disabled or modified as follows:
•
ILAS enabling is controlled in Register 0x5F, Bits[3:2] and
by default is enabled. Optionally, to support some unique
instances of the interfaces (such as NMCDA-SL), the
JESD204B interface can be programmed to either disable the
ILAS sequence or continually repeat the ILAS sequence.
The AD6673 has fixed values of some of the JESD204B interface
parameters, and they are as follows:
•
JESD204B allows parameters to identify the device and lane.
These parameters are transmitted during the ILAS phase,
and they are accessible in the internal registers.
There are three identification values: device identification
(DID), bank identification (BID), and lane identification
(LID). DID and BID are device specific; therefore, they can
be used for link identification.
Set number of frames per multiframe, K.
•
Value Range
0…31
0…31
0…255
0…15
Scramble, SCR.
Configure Detailed Options
•
Register, Bits
0x67, [4:0]
0x68, [4:0]
0x64, [7:0]
0x65, [3:0]
•
•
[N] = 11: number of bits per converter is 11, in Register 0x72,
Bits[3:0]; Register 0x72 represents a value of N – 1.
[N’] = 16: number of bits per sample is 16, in Register 0x73,
Bits[3:0]; Register 0x73 represents a value of N' – 1.
[CF] = 0: number of control words/frame clock cycle/
converter is 0, in Register 0x75, Bits[4:0].
Verify read only values: lanes per link (L), octets per frame (F),
number of converters (M), and samples per converter per frame
(S). The AD6673 calculates values for some JESD204B parameters
based on other settings, particularly the quick configuration
register selection. The read only values here are available in the
register map for verification.
•
•
•
•
•
Rev. C | Page 29 of 45
[L] = lanes per link can be 1 or 2; read the values from
Register 0x6E, Bit 0
[F] = octets per frame can be 1, 2, or 4; read the value from
Register 0x6F, Bits[7:0]
[HD] = high density mode can be 0 or 1; read the value
from Register 0x75, Bit 7
[M] = number of converters per link can be 1 or 2; read
value from Register 0x71, Bits[7:0]
[S] = samples per converter per frame can be 1 or 2: read
the value from Register 0x74, Bits[4:0]
AD6673
Data Sheet
Verify FCHK, Checksum of JESD204B Interface Parameters
Additional Digital Output Configuration Options
The JESD204B parameters can be verified through the checksum
value [FCHK] of the JESD204B interface parameters. Each lane has
an FCHK value associated with it. The FCHK value is transmitted
during the ILAS second multiframe and can be read from the
internal registers.
Other data format controls include the following:
The checksum value is the modulo 256 sum of the parameters
listed in the No. column of Table 12. The checksum is calculated
by adding the parameter fields before they are packed into the
octets shown in Table 12.
•
The FCHK for the lane configuration for data coming out of
Lane 0 can be read from Register 0x78. Similarly, the FCHK for
the lane configuration for data coming out of Lane 1 can be read
from Register 0x79.
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4 Bit 3
DID[7:0]
Bit 2
Bit 1
Invert the polarity of the serial output data: Register 0x60,
Bit 1.
ADC data format (offset binary, twos complement):
Register 0x14, Bits[1:0].
Options for interpreting SYSREF± and SYNCINB± signals in
Register 0x3A. See Table 14 for additional descriptions of
Register 0x3A controls.
Option to remap converter and lane assignments,
Register 0x82 and Register 0x83. See Figure 49 for a
simplified block diagram.
•
•
Reenable Lanes After Configuration
Table 12. JESD204B Configuration Table Used in ILAS and
CHKSUM Calculation
No.
0
1
2
3
4
5
6
7
8
9
10
•
Bit 0
(LSB)
After modifying the JESD204B link parameters, enable the link
so that the synchronization process can begin. This is accomplished
by writing Logic 0 to Register 0x5F, Bit 0.
BID[3:0]
LID[4:0]
L[4:0]
SCR
F[7:0]
K[4:0]
M[7:0]
CS[1:0]
SUBCLASS[2:0]
JESDV[2:0]
N[4:0]
N’[4:0]
S[4:0]
CF[4:0]
AD6673 DUAL IF RECEIVER
CONVERTER A
INPUT
CONVERTER A
CONVERTER A
SAMPLE
A
PRIMARY CONVERTER
INPUT [0]
PRIMARY LANE
OUTPUT [0]
SERDOUT0
LANE 0
JESD204B LANE CONTROL
(M = 1, 2; L = 1, 2)
B
SECONDARY CONVERTER
INPUT [1]
SECONDARY LANE
OUTPUT [1]
LANE 1
LANE MUX
(SPI REGISTER
MAPPING: 0x82,0x83)
A
CONVERTER B
INPUT
SECONDARY CONVERTER
INPUT [1]
SECONDARY LANE
OUTPUT [1]
LANE 1
JESD204B LANE CONTROL
(M = 1, 2; L = 1, 2)
CONVERTER B
CONVERTER B
SAMPLE
B
PRIMARY CONVERTER
INPUT [0]
PRIMARY LANE
OUTPUT [0]
LANE 0
10632-045
SYSREF
SERDOUT1
SYNCINB
Figure 49. AD6673 Transmit Link Simplified Block Diagram
Rev. C | Page 30 of 45
Data Sheet
A PATH
(LSB)
JESD204B
TEST PATTERN
10-BIT
8B/10B
ENCODER/
CHARACTER
REPLACEMENT
OPTIONAL
SCRAMBLER
1 + x14 + x15
A6
A7
A8
A9
A10
A11
A12
A13
C0
C1
A0
A1
A2
A3
A4
A5
S8
S9
S10
S11
S12
S13
S14
S15
S0
S1
S2
S3
S4
S5
S6
S7
SERDOUT±
SERIALIZER
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
E19 . . . E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
~SYNC
t
SYSREF
10632-046
ADC
VINA–
JESD204B
TEST PATTERN
8-BIT
OCTET1
VINA+
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ADC
TEST PATTERN
16-BIT
OCTET0
(MSB)
AD6673
Figure 50. AD6673 Digital Processing of JESD204B Lanes
Table 13. AD6673 JESD204B Typical Configurations
M (No. of Converters),
Register 0x71,
Bits[7:0]
1
1
2
2
DATA
FROM
ADC
L (No. of Lanes),
Register 0x6E,
Bit 0
1
2
1
2
FRAME
ASSEMBLER
(ADD TAIL BITS)
F (Octets/Frame),
Register 0x6F,
Bits[7:0], Read Only
2
1
4
2
OPTIONAL
SCRAMBLER
1 + x14 + x15
S (Samples/ADC/Frame),
Register 0x74, Bits[4:0],
Read Only
1
1
1
1
8B/10B
ENCODER
TO
RECEIVER
HD (High Density Mode),
Register 0x75, Bit 7,
Read Only
0
1
0
0
10632-047
JESD204B
Configure
Setting
0x11
0x12
0x21
0x22 (Default)
Figure 51. AD6673 ADC Output Data Path
Table 14. AD6673 JESD204B Configuration Using Register 0x3A
Bit
0
Bit Name
Enable internal
SYSREF± buffer
1
SYSREF± enable
2
SYSREF± mode
Description
This bit controls the on-chip buffer for SYSREF±. By default, this bit is 0, which disables the buffer. If the
AD6673 is configured for JESD204B Subclass 1 operation, the SYSREF signal is required to align the JESD204B
link and this bit must be set to 1.
To avoid a false trigger as a result of transients that are caused when enabling the buffer (particularly for oneshot SYSREF signal configuration), set this bit first and then, in a consecutive SPI register write, configure all
remaining bits in Register 0x3A to the desired JESD204B link configuration, including keeping this bit at 1.
A setting of 0 (default) gates the SYSREF signal so that the internal logic is not affected by an external SYSREF
signal. Set this bit to 0 when in Subclass 0, that is, when the SYSREF signal is not used.
If using Subclass 1 with one-shot SYSREF± mode, enable the buffer while the SYSREF signal is established;
however, it is recommended that the buffer be disabled during normal operation.
If using Subclass 1 with continuous SYSREF± mode, keep the buffer enabled for normal operation.
This bit can be used to enable the circuitry that uses the SYSREF± input signal and must be on to enable
Subclass 1 operation. Set this bit to 1 when using JESD204B Subclass 1 operation.
This bit is self clearing after a valid SYSREF± occurs when the SYSREF± mode bit (Register 0x3A, Bit 2) is set to
1 (configured for one-shot SYSREF± operation).
The SYSREF signal is still used in some digital circuitry even if this bit is 0. To disable the SYSREF± signal
internally, Register 0x3A, Bit 0 must be set to 0.
This bit is used in Subclass 1 operation to define one-shot or continuous SYSREF± mode. To configure
continuous (or gapped periodic) SYSREF± mode, this bit is set to 0. For one-shot operation, this bit is set to 1.
In one-shot mode, it is recommended that the SYSREF buffer be disabled after the SYSREF signal has
occurred by setting Register 0x3A[0] to 0.
Rev. C | Page 31 of 45
AD6673
Data Sheet
Bit
3
Bit Name
Realign on SYSREF±;
for Subclass 1 only
4
Realign on
SYNCINB±; for
Subclass 1 only
Description
When this bit is set to 1 and an active SYSREF signal occurs, the internal clock alignment for the JESD204B
timing is forced. Setting this bit is only recommended for one-shot mode and must be done only prior to
initially establishing a link. This bit resets the JESD204B link on the active SYSREF signal and requires
additional clock alignment register writes after realignment to properly set up the timing margin over
temperature. See the Synchronization section for the clock alignment procedure. For continuous SYSREF±
mode, this bit must be set to 0 during normal operation.
When this bit is set to 1 and an active SYNC occurs, the internal clock alignment for the JESD204B timing is
forced. An active SYNC requires an SYNCINB± input to be logic low for at least four consecutive LMFCs.
Table 15. AD6673 JESD204B Frame Alignment Monitoring and Correction Replacement Characters
Character to be Replaced
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame equals D28.7
Last octet in frame equals D28.3
Last octet in frame equals D28.7
Last Octet in
Multiframe
No
Yes
Not applicable
No
Yes
Not applicable
Frame and Lane Alignment Monitoring and Correction
Frame alignment monitoring and correction is part of the JESD204B
specification. The 11-bit word requires two octets to transmit all
the data. The two octets (MSB and LSB), where F = 2, make up
a frame. During normal operating conditions, frame alignment
is monitored via alignment characters, which are inserted under
certain conditions at the end of a frame. Table 15 summarizes the
conditions for character insertion along with the expected characters
under the various operation modes. If lane synchronization is
enabled, the replacement character value depends on whether
the octet is at the end of a frame or at the end of a multiframe.
Based on the operating mode, the receiver can ensure that it is
still synchronized to the frame boundary by correctly receiving
the replacement characters.
Digital Outputs and Timing
The AD6673 has differential digital outputs that power up by
default. The driver current is derived on-chip and sets the output
current at each output equal to a nominal 4 mA. Each output
presents a 100 Ω dynamic internal termination to reduce
unwanted reflections.
Place a 100 Ω differential termination resistor at each receiver
input to result in a nominal 300 mV peak-to-peak swing at
the receiver (see Figure 52). Alternatively, single-ended 50 Ω
termination can be used. When single-ended termination is
used, the termination voltage should be DRVDD/2; otherwise,
ac coupling capacitors can be used to terminate to any singleended voltage.
Replacement Character
K28.7
K28.3
K28.7
K28.7
K28.3
K28.7
VRXCM
DRVDD
100Ω
DIFFERENTIAL
0.1µF TRACE PAIR
SERDOUTx+
100Ω
OR
RECEIVER
SERDOUTx–
0.1µF
OUTPUT SWING = VOD
(SEE TABLE 3)
VCM = Rx VCM
10632-048
Lane Synchronization
On
On
Off
On
On
Off
Figure 52. AC-Coupled Digital Output Termination Example
The AD6673 digital outputs can interface with custom ASICs and
FPGA receivers, providing superior switching performance in
noisy environments. Single point-to-point network topologies are
recommended with a single differential 100 Ω termination resistor
placed as close to the receiver logic as possible. The common
mode of the digital output automatically biases itself to half the
supply of the receiver (that is, the common-mode voltage is 0.9 V
for a receiver supply of 1.8 V) if dc-coupled connecting is used
(see Figure 53). For receiver logic that is not within the bounds
of the DRVDD supply, use an ac-coupled connection. Simply
place a 0.1 µF capacitor on each output pin and derive a 100 Ω
differential termination close to the receiver side.
DRVDD
100Ω
DIFFERENTIAL
TRACE PAIR
SERDOUTx+
100Ω
RECEIVER
SERDOUTx–
OUTPUT SWING = VOD
(SEE TABLE 3)
VCM = DRVDD/2
Figure 53. DC-Coupled Digital Output Termination Example
Rev. C | Page 32 of 45
10632-049
Scrambling
Off
Off
Off
On
On
On
Data Sheet
AD6673
Using the SPI port, the user can provide a threshold above which
the FD output is active. Bit 0 of Register 0x45 enables the fast
detect feature. Register 0x47 to Register 0x4B allow the user to
set the threshold levels. As long as the signal is below the selected
threshold, the FD output remains low. In this mode, the magnitude
of the data is considered in the calculation of the condition, but
the sign of the data is not considered. The threshold detection
responds identically to positive and negative signals outside the
desired range (magnitude).
If there is no far-end receiver termination, or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches, and that the differential output traces be
close together and at equal lengths.
Figure 54 shows an example of the digital output (default) data eye
and time interval error (TIE) jitter histogram and bathtub curve for
the AD6673 lane running at 5 Gbps.
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs to drive longer
trace lengths (see Register 0x15 in Table 17). The power
dissipation of the DRVDD supply increases when this option is
used. See the Memory Map section for more details.
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 36 ADC clock cycles. An overrange at the
input is indicated by this bit 36 clock cycles after it occurs.
The format of the output data is twos complement by default.
To change the output data format to offset binary, see the
Memory Map section (Register 0x14 in Table 17).
GAIN SWITCHING
ADC OVERRANGE AND GAIN CONTROL
The AD6673 includes circuitry that is useful in applications
either where large dynamic ranges exist, or where gain ranging
amplifiers are employed. This circuitry allows digital thresholds
to be set such that an upper threshold and a lower threshold can
be programmed.
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides delayed information
on the state of the analog input that is of limited value in
preventing clipping. Therefore, it is helpful to have a
programmable threshold below full scale that allows time to
reduce the gain before the clip occurs. In addition, because
input signals can have significant slew rates, latency of this
function is of concern.
HEIGHT1: EYE DIAGRAM
400
1
3
–
6000
200
TJ@BER1: BATHTUB
2
–
300
–
1–2
1–4
5000
100
1–6
0
4000
BER
HITS
1–8
3000
–100
1–10
2000
–200
–300
1–12
1000
1–14
EYE: TRANSITION BITS OFFSET: –0.0072
–400 UIs: 8000; 999992 TOTAL: 8000.999992
–200
–100
0
TIME (ps)
100
0
200
–10
0
TIME (ps)
10
1–16
–0.5
0.78 UI
0
UIs
Figure 54. AD6673 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations at 5 Gbps
Rev. C | Page 33 of 45
0.5
10632-050
VOLTAGE (mV)
PERIOD1: HISTOGRAM
7000
1
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
AD6673
Data Sheet
Fast Threshold Detection (FDA and FDB)
detect lower threshold register is a 16-bit register that is compared
with the signal magnitude at the output of the ADC. This comparison is subject to the ADC pipeline latency but is accurate in
terms of converter resolution. The lower threshold magnitude is
defined by
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located in Register 0x47 and Register 0x48. The selected threshold
register is compared with the signal magnitude at the output of
the ADC. The fast upper threshold detection has a latency of
4 clock cycles. The approximate upper threshold magnitude is
defined by
Lower Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/216)
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located in Register 0x4B and Register 0x4C.
Upper Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/216)
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Register 0x49 and Register 0x4A. The fast
The operation of the upper threshold and lower threshold registers,
along with the dwell time registers, is shown in Figure 55.
UPPER THRESHOLD
DWELL TIME
LOWER THRESHOLD
DWELL TIME
FDA OR FDB
Figure 55. Threshold Settings for FDA and FDB Signals
Rev. C | Page 34 of 45
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE LT
10632-051
MIDSCALE
TIMER RESET BY
RISE ABOVE LT
Data Sheet
AD6673
DC CORRECTION
Because the dc offset of the ADC may be significantly larger than
the signal being measured, a dc correction circuit is included to
null the dc offset before measuring the power. The dc correction
circuit can also be switched into the main signal path; however,
this may not be appropriate if the ADC is digitizing a time-varying
signal with significant dc content, such as GSM.
DC CORRECTION BANDWIDTH
The dc correction circuit is a high-pass filter with a programmable
bandwidth (ranging between 0.29 Hz and 2.387 kHz at
245.76 MSPS). The bandwidth is controlled by writing to
the 4-bit dc correction bandwidth select register, located at
Register 0x40, Bits[5:2]. The following equation can be used to
compute the bandwidth value for the dc correction circuit:
DC CORRECTION READBACK
The current dc correction value can be read back in Register 0x41
and Register 0x42 for each channel. The dc correction value is a
16-bit value that can span the entire input range of the ADC.
DC CORRECTION FREEZE
Setting Bit 6 of Register 0x40 freezes the dc correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
DC CORRECTION (DCC) ENABLE BITS
Setting Bit 1 of Register 0x40 enables dc correction for use in
the output data signal path.
DC_Corr_BW = 2−k−14 × fCLK/(2 × π)
where:
k is the 4-bit value programmed in Bits[5:2] of Register 0x40
(values between 0 and 13 are valid for k).
fCLK is the AD6673 ADC sample rate in hertz.
Rev. C | Page 35 of 45
AD6673
Data Sheet
SERIAL PORT INTERFACE (SPI)
The AD6673 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields. These fields are documented
in the Memory Map section. For detailed operational information,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CS pin (see Table 16). The SCLK (serial clock) pin is
used to synchronize the read and write data presented from/to the
ADC. The SDIO (serial data input/output) pin is a dual-purpose
pin that allows data to be sent and read from the internal ADC
memory map registers. The CS (chip select bar) pin is an active low
control that enables or disables the read and write cycles.
Table 16. Serial Port Interface Pins
Pin
SCLK
SDIO
CS
Function
Serial Clock. The serial shift clock input, which is used to
synchronize serial interface, reads and writes.
Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip Select Bar. An active low control that gates the read
and write cycles.
The falling edge of CS, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 56 and
Table 5.
Other modes involving CS are available. CS can be held low
indefinitely, which permanently enables the device; this is called
streaming. CS can stall high between bytes to allow for additional
external timing. When CS is tied high, SPI functions are placed
in a high impedance mode. This mode turns on any SPI pin
secondary functions.
All data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether a read or write command is
issued. This allows the SDIO pin to change direction from an
input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the SDIO pin to change
direction from an input to an output at the appropriate point in
the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 16 comprise the physical interface
between the user programming device and the serial port of the
AD6673. The SCLK pin and the CS pin function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
Do not activate the SPI port during periods when the full dynamic
performance of the converter is required. Because the SCLK signal,
the CS signal, and the SDIO signal are typically asynchronous to
the ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD6673 to prevent these signals from transitioning at the
converter inputs during critical sampling periods.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and the W1 bits.
Rev. C | Page 36 of 45
Data Sheet
AD6673
SPI ACCESSIBLE FEATURES
Table 17 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD6673 part-specific features are described in the
Memory Map Register Description section.
Table 17. Features Accessible Using the SPI
Feature Name
Mode
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
Description
Allows the user to set either power-down mode or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the converter offset
Allows the user to set test modes to have known data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
tDS
tS
tHIGH
tH
tCLK
tDH
tLOW
CS
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 56. Serial Port Interface Timing Diagram
Rev. C | Page 37 of 45
D4
D3
D2
D1
D0
DON’T CARE
10632-052
SCLK DON’T CARE
AD6673
Data Sheet
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Logic Levels
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into three sections: the
chip configuration registers (Address 0x00 to Address 0x02);
the channel index and transfer registers (Address 0x05 and
Address 0xFF); and the ADC functions registers, including
setup, control, and test (Address 0x08 to Address 0xA8).
An explanation of logic level terminology follows:
The memory map register table (see Table 18) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the
default hexadecimal value given. For example, Address 0x14,
the output mode register, has a hexadecimal default value of
0x01. This means that Bit 0 = 1, and the remaining bits are 0s.
This setting is the default output format value, which is twos
complement. For more information on this function and others,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI. This document details the functions controlled
by Register 0x00 to Register 0x25. The remaining registers,
Register 0x3A and Register 0x59, are documented in Table 18.
Open and Reserved Locations
All address and bit locations that are not included in Table 18
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), do not write to this address
location.
Default Values
After the AD6673 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 18.
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x09, Address 0x0B, Address 0x14, Address 0x18, and
Address 0x3A to Address 0x4C are shadowed. Writes to these
addresses do not affect part operation until a transfer command is
issued by writing 0x01 to Address 0xFF, setting the transfer bit. This
allows these registers to be updated internally and simultaneously
when the transfer bit is set. The internal update takes place when
the transfer bit is set, and then the bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed to a different value for each
channel. In these cases, channel address locations are internally
duplicated for each channel. These registers and bits are designated
in Table 18 as local. These local registers and bits can be accessed
by setting the appropriate Channel A or Channel B bits in
Register 0x05. If both bits are set, the subsequent write affects
the registers of both channels. In a read cycle, only Channel A
or Channel B should be set to read one of the two registers. If
both bits are set during an SPI read cycle, the part returns the
value for Channel A. Registers and bits designated as global in
Table 18 affect the entire part and the channel features for which
independent settings are not allowed between channels. The
settings in Register 0x05 do not affect the global registers and bits.
Rev. C | Page 38 of 45
Data Sheet
AD6673
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 18 are not currently supported for this device.
Table 18. Memory Map Registers
Reg
Addr
(Hex)
0x00
0x01
Register
Name
Global SPI
config
CHIP ID
Bit 7
(MSB)
0
0x02
Chip info
0x05
Channel
index
0x08
PDWN
modes
0x09
Global clock
Reserved
0x0A
PLL status
PLL locked
status
0x0B
Global clock
divider
0x0D
Test control
register
Bit 6
LSB first
Bit 5
Soft reset
Bit 4
1
Bit 3
1
Bit 2
Soft reset
Bit 1
LSB first
Bit 0 (LSB)
0
AD6673 8-bit CHIP ID is 0xBA
Speed grade
00 = 250 MSPS
JTX in
standby;
0 = 204B
core is
unaffected
in
standby;
1 = 204B
core is
powered
down
except for
PLL during
standby
Clock selection:
00 = Nyquist clock
10 = RF clock divide by 4
11 = clock off
External
PDWN
mode;
0=
PDWN is
full power
down;
1=
PDWN
puts
device in
standby
User test mode cycle;
00 = repeat pattern
(User Pattern 1, 2, 3, 4, 1,
2, 3, 4, 1, …);
10 = single pattern
(User Pattern 1, 2, 3, 4,
then all zeros)
[LOCAL]
Reserved for chip die revision currently
0x0
SPI write to
SPI write
ADC A path
to ADC B
path
Chip power modes;
JESD204B power
00 = normal mode
modes;
(power up);
00 = normal mode
01 = power-down mode,
(power up);
digital datapath clocks
01 = power-down
disabled, digital datapath
mode: PLL off, serializer
held in reset; most analog
off, clocks stopped,
paths powered off;
digital held in reset;
10 = standby mode;
10 = standby mode: PLL
digital datapath clocks
on, serializer off, clocks
disabled, digital datapath
stopped, digital held in
held in reset, some
reset
analog paths powered off
[LOCAL]
Clock duty
cycle
stabilizer
enable
204B link is
ready
Clock divider ratio relative to the encode
Clock divide phase relative to the
clock;
encode clock;
0x00 = divide by 1;
0x0 = 0 input clock cycles delayed;
0x01 = divide by 2;
0x1 = 1 input clock cycles delayed;
0x02 = divide by 3;
0x2 = 2 input clock cycles delayed;
…
…
0x7 = divide by 8;
0x7 = 7 input clock cycles delayed
using a CLKDIV_DIVIDE_RATIO > 0
(Divide Ratio > 1) causes the DCS to be
automatically enabled
Data output test generation mode;
Short
Long
0000 = off (normal mode);
pseudopseudo0001 = midscale short;
random
random
0010 = positive full scale;
number
number
0011 = negative full scale;
generator generator
0100 = alternating checker board;
reset;
reset;
0101 = PN sequence long;
0 = short
0 = long
0110 = PN sequence short;
PRN
PRN
0111 = 1/0 word toggle;
enabled;
enabled;
1000 = user test mode (use with Register 0x0D, Bit 7
1 = short
1 = long
and User Pattern 1, 2, 3, 4);
PRN held
PRN held
1001 to 1110 = unused;
in reset
in reset
1111 = ramp output
[LOCAL]
[LOCAL]
[LOCAL]
Rev. C | Page 39 of 45
Default
0x18
Notes
0xBA
Read
only
0x00
0x03
0x00
0x01
0x00
0x00
DCS
enabled
if clock
divider
enabled
Read
only
AD6673
Reg
Addr
(Hex)
0x10
Register
Name
Offset
adjust
(local)
0x14
Output
mode
0x15
CML output
adjust
0x18
ADC VREF
0x19
User Test
Pattern 1 L
User Test
Pattern 1 M
User Test
Pattern 2 L
User Test
Pattern 2 M
User Test
Pattern 3 L
User Test
Pattern 3 M
User Test
Pattern 4 L
User Test
Pattern 4 M
PLL low
encode
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x24
0x25
Data Sheet
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Offset adjust in LSBs from +31 to −32 (twos complement format);
01 1111 = adjust output by +31;
01 1110 = adjust output by +30;
…
00 0001 = adjust output by +1;
00 0000 = adjust output by 0 (default);
…
10 0001 = adjust output by −31;
10 0000 = adjust output by −32
[LOCAL]
Digital datapath output
Invert ADC
Disable
JTX CS bits assignment (in
data format select (DFS)
data;
output
conjunction with Register 0x72)
(local);
0 = normal
from ADC
000 = {overrange||underrange, valid}
00 = offset binary;
(default);
001 = {overrange||underrange}
01 = twos complement
1=
010 = {overrange||underrange, blank}
[LOCAL]
inverted
011 = {blank, valid}
[LOCAL]
100 = {blank, blank}
All others = {overrange||underrange,
valid}
JESD204B CML differential output drive
level adjustment;
000 = 81% of nominal (that is, 478 mV);
001 = 89% of nominal (that is, 526 mV);
010 = 98% of nominal (that is, 574 mV);
011 = nominal [default] (that is, 588 mV);
110 = 126% of nominal (that is, 738 mV)
Main reference full-scale VREF adjustment;
0 1111 = internal 2.087 V p-p;
…
0 0001 = internal 1.772 V p-p;
0 0000 = internal 1.75 V p-p (default);
1 1111 = internal 1.727 V p-p;
…
1 0000 = internal 1.383 V p-p
User Test Pattern 1 LSB; use in conjunction with Register 0x0D and Register 0x61
Default
0x00
0x01
0x03
0x00
0x00
User Test Pattern 1 MSB
0x00
User Test Pattern 2 LSB
0x00
User Test Pattern 2 MSB
0x00
User Test Pattern 3 LSB
0x00
User Test Pattern 3 MSB
0x00
User Test Pattern 4 LSB
0x00
User Test Pattern 4 MSB
0x00
00 = for lane speeds >
2 Gbps;
01 = for lane speeds <
2 Gbps
0x00
BIST
MISR_LSB
BIST
MISR_MSB
0x00
0x00
Rev. C | Page 40 of 45
Notes
Read
only
Read
only
Data Sheet
Reg
Addr
(Hex)
0x3A
Register
Name
SYNCINB±/
SYSREF±
CTRL
0x3C
NSR CTRL
0x3E
NSR tuning
0x40
DCC CTRL
0x41
DCC value
LSB
DCC value
MSB
Fast detect
control
0x42
0x45
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x5E
FD upper
threshold
FD upper
threshold
FD lower
threshold
FD lower
threshold
FD dwell
time
FD dwell
time
204B quick
config
AD6673
Bit 7
(MSB)
Bit 6
Freeze dc
correction;
0=
calculate;
1 = freeze
value
Bit 5
Bit 4
Realign on
SYNCINB±;
for
Subclass 1
only: 0 =
normal
mode;
1 = realign
lanes on
every
active
SYNCINB±
Bit 3
Realign
on
SYSREF±;
for
Subclass
1 only: 0
= normal
mode;
1=
realign
lanes on
every
active
SYSREF±;
use with
one-shot
SYSREF in
Subclass 1
mode
Bit 2
SYSREF±
mode;
0=
continuous
reset clock
dividers;
1 = sync on
next
SYSREF±
rising edge
only
Bit 1
SYSREF±
enable;
0=
disabled;
1=
enabled
NOTE: This
bit will
self-clear
after
SYSREF if
SYSREF±
mode = 1
Bit 0 (LSB)
Enable
internal
SYSREF±
buffer;
0 = buffer
disabled,
external
SYSREF±
pin
ignored;
1 = buffer
enabled,
use
external
SYSREF±
signal
Bandwidth NSR enable
mode;
0 = 22%;
1 = 33%
Noise shaped requantizer tuning frequency;
selects the center frequency of the noise transfer function (NTF);
57 possible tuning words (TW) exist; each step is 0.5% of the ADC sample rate
Enable
DC correction bandwidth select;
DCC
correction bandwidth is 2387.32 Hz/reg value;
there are 14 possible values;
0000 = 2387.32 Hz;
0001 = 1193.66 Hz;
1101 = 0.29 Hz
DC Correction Value[7:0]
DC Correction Value[15:8]
Force
value of
FDA/FDB
pins;
if force
pins is true,
this value
is output
on FD pins
Fast Detect Upper Threshold[7:0]
Pin
function;
0 = fast
detect;
1=
overrange
Force
FDA/FDB
pins;
0=
normal
function;
1 = force
to value
Default
0x00
0x00
0x1C
0x00
0x00
0x00
Enable fast
detect
output
Fast Detect Upper Threshold[14:8]
Fast Detect Lower Threshold[7:0]
Fast Detect Lower Threshold[14:8]
0x00
0x00
0x00
0x00
0x00
Fast Detect Dwell Time[7:0]
0x00
Fast Detect Dwell Time[15:8]
0x00
Quick configuration register, always reads back 0x00;
0x11 = M = 1, L = 1; one converter, one lane; second converter is not automatically powered down;
0x12 = M = 1, L = 2; one converter, two lanes; second converter is not automatically powered down;
0x21 = M = 2, L = 1; two converters, one lane;
0x22 = M = 2, L = 2; two converters, two lanes
0x00
Rev. C | Page 41 of 45
Notes
Always
reads
back
0x00
AD6673
Reg
Addr
(Hex)
0x5F
Data Sheet
Register
Name
204B Link
CTRL 1
Bit 7
(MSB)
0x60
204B Link
CTRL 2
Reserved;
set to 0
Bit 6
Tail bits: If
CS bits
are not
enabled,
0 = extra
bits are 0;
1 = extra
bits are
9-bit PN
Reserved;
set to 0
0x61
204B Link
CTRL 3
Reserved;
set to 0
Reserved;
set to 0
0x62
204B Link
CTRL 4
204B Link
CTRL 5
204B DID
config
204B BID
config
204B LID
config 0
204B LID
config 1
204B
parameters
SCR/L
0x63
0x64
0x65
0x66
0x67
0x6E
0x6F
0x70
0x71
0x72
204B
parameters,
F
204B
parameters,
K
204B
parameters,
M
204B
parameters,
CS/N
Bit 5
JESD204B
test
sample
enabled
Bit 4
Reserved;
set to 1
Reserved;
set to 0
Test data injection
point;
01 = 10-bit data at
8b/10b output;
10 = 8-bit data at
scrambler input
Bit 3
Bit 2
ILAS mode;
01 = ILAS normal mode
enabled;
11 = ILAS always on, test
mode
Bit 1
Reserved;
set to 1
Bit 0 (LSB)
Powerdown
JESD204B
link; set
high while
configuring
link
parameters
Invert
logic of
JESD204B
bits
JESD204B test mode patterns;
0000 = normal operation (test mode disabled);
0001 = alternating checker board;
0010 = 1/0 word toggle;
0011 = PN sequence PN23;
0100 = PN sequence PN9;
0101= continuous/repeat user test mode;
0110 = single user test mode;
0111 = reserved;
1000 = modified RPAT test sequence, must be used
with JTX_TEST_GEN_SEL = 01 (output of 8b/10b);
1100 = PN sequence PN7;
1101 = PN sequence PN15;
other settings are unused
Reserved
Default
0x14
0x00
0x00
0x00
Reserved
0x00
JESD204B DID value
0x00
JESD204B BID value
0x00
Lane 0 LID value
0x00
Lane 1 LID value
0x01
JESD204B
lanes (L);
0 = 1 lane;
1 = 2 lanes
JESD204B
scrambling
(SCR);
0=
disabled;
1=
enabled
0x81
JESD204B number of octets per frame (F); calculated value
[Note that this value is in x – 1 format]
0x01
JESD204B number of frames per multiframe (K); set value of K per JESD204B specifications, but also must be a
multiple of 4 octets
[Note that this value is in x – 1 format]
JESD204B number of converters (M);
0 = 1 converter;
1 = 2 converters
ADC converter resolution (N),
Number of control bits
0xA = 11-bit converter (N = 11)
(CS);
00 = no control bits
(CS = 0);
01 = 1 control bit
(CS = 1);
10 = 2 control bits
(CS = 2)
0x1F
Rev. C | Page 42 of 45
Notes
0x01
0x0A
Read
Only
Data Sheet
Reg
Addr
(Hex)
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x82
Register
Name
204B
parameters,
subclass/Np
204B
parameters,
S
204B
parameters,
HD and CF
204B RESV1
204B RESV2
204B
CHKSUM0
204B
CHKSUM1
204B Lane
Assign 1
AD6673
Bit 7
(MSB)
Bit 6
Bit 5
JESD204B subclass;
0x0 = Subclass 0;
0x1 = Subclass 1
(default)
Reserved;
set to 1
JESD204B
HD value;
read only
Bit 4
Bit 3
Bit 2
Bit 1
JESD204B N’ value;
0xF = N’ = 16
Bit 0 (LSB)
Default
0x2F
JESD204B samples per converter frame cycle (S); read only
[Note that this value is in x – 1 format]
0x20
JESD204B control words per frame clock cycle per link (CF); read only
0x00
Reserved Field Number 1
Reserved Field Number 2
JESD204B serial checksum value for Lane 0
Notes
Read
Only
0x00
0x00
JESD204B serial checksum value for Lane 1
Reserved;
set to 1
00 = assign Logical
Lane 0 to Physical Lane
A [default];
01 = assign Logical
Lane 0 to Physical Lane B
Reserved;
Reserved;
set to 1
set to 1
0x83
204B Lane
Assign 2
0x8B
204B LMFC
offset
0xA8
204B
preemphasis
0xEE
Internal
digital clock
delay
Enable
internal
clock delay
0xEF
Internal
digital clock
delay
Enable
internal
clock delay
0xF3
Internal
digital clock
alignment
0xFF
Device
update
(global)
Reserved;
set to 0
00 = assign Logical Lane 1
to Physical Lane A;
01 = assign Logical Lane 1
to Physical Lane B
(default)
Local multiframe clock (LMFC) phase offset value; reset value for
LMFC phase counter when SYSREF is asserted; used for
deterministic delay applications
JESD204B preemphasis enable option (consult factory for more detail);
set value to 0x04 for preemphasis off;
set value to 0x14 for preemphasis on
Use incrementing values from 0 to 7 to increase
Set to 0
Set to 0
Set to 0
internal digital clock delay; for internal data latching
purposes, this does not affect external timing
Set to 0
Set to 0
Set to 0
Force
manual
realignment on
Lane 1,
self
clearing
Lane 1
alignment
complete
Use incrementing values from 0 to 7 to increase
internal digital clock delay; for internal data latching
purposes, this does not affect external timing
Force
manual
realignment on
Lane 0,
self
clearing
Lane 0
alignment
complete
For more information on functions controlled in Register 0x00
to Register 0x25, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
Rev. C | Page 43 of 45
0x31
0x00
0x04
0x00
0x00
0x14
Transfer
settings
MEMORY MAP REGISTER DESCRIPTION
0x02
Typically
not
required
See the
Synchronization
section
for use
See the
Synchronization
section
for use
See the
Synchronization
section
for use
AD6673
Data Sheet
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting system level design and layout of the AD6673, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD6673, use two separate 1.8 V
power supplies. The power supply for AVDD can be isolated and
for DVDD and DRVDD it can be tied together, in which case
isolation between DVDD and DRVDD is required. Isolation can
be achieved using a ferrite bead or an inductor of approximately
1 µH. An unfiltered switching regulator is not recommended
for the DRVDD supply as it impacts the performance of the
JESD204B serial transmission lines and may result in link
problems. Alternately, the JESD204B PHY power (DRVDD)
and analog (AVDD) supplies can be tied together, and a
separate supply can be used for the digital outputs (DVDD).
exposed (no solder mask) copper plane on the PCB to the
AD6673 exposed paddle, Pin 0.
The copper plane must have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow
through the bottom of the PCB. Fill or plug these vias with
nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, overlay a silkscreen to partition the continuous plane
on the PCB into several uniform sections. This provides several tie
points between the ADC and the PCB during the reflow process.
Using one continuous plane with no partitions guarantees only
one tie point between the ADC and the PCB. See the evaluation
board for a PCB layout example. For detailed information about
the packaging and PCB layout of chip scale packages, refer to
the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).
VCM
The designer can employ several different decoupling capacitors
to cover both high and low frequencies. Locate these capacitors
close to the point of entry at the PC board level and close to the
pins of the part with minimal trace length. Each power supply
domain must have local high frequency decoupling capacitors.
This is especially important for DRVDD and AVDD to
maintain analog performance.
Decouple the VCM pin to ground with a 0.1 μF capacitor, as
shown in Figure 29. For optimal channel-to-channel isolation,
include a 33 Ω resistor between the AD6673 VCM pin and the
Channel A analog input network connection, as well as between
the AD6673 VCM pin and the Channel B analog input network
connection.
When using the AD6673, a single PCB ground plane is sufficient.
With proper decoupling and smart partitioning of the PCB analog,
digital, and clock sections, optimum performance is easily
achieved.
When the full dynamic performance of the converter is required,
do not activate the SPI port during periods. Because the SCLK,
CS, and SDIO signals are typically asynchronous to the ADC clock,
noise from these signals can degrade converter performance. If
the on-board SPI bus is used for other devices, it may be necessary
to provide buffers between this bus and the AD6673 to keep
these signals from transitioning at the converter input pins
during critical sampling periods.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. Mate a continuous,
SPI Port
Rev. C | Page 44 of 45
Data Sheet
AD6673
OUTLINE DIMENSIONS
0.30
0.25
0.20
PIN 1
INDICATOR
37
36
48
1
0.50
BSC
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
5.60 SQ
5.50
13
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
*5.70
EXPOSED
PAD
24
PIN 1
INDICATOR
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-2
WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.
10-15-2015-D
7.10
7.00 SQ
6.90
Figure 57. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD6673BCPZ-250
AD6673BCPZRL7-250
AD6673-250EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board with AD6673-250
Z = RoHS Compliant Part.
©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10632-0-12/15(C)
Rev. C | Page 45 of 45
Package Option
CP-48-13
CP-48-13