AD ADXRS450BRGZ High performance, digital output gyroscope Datasheet

High Performance,
Digital Output Gyroscope
ADXRS450
Preliminary Technical Data
FEATURES
GENERAL DESCRIPTION
Complete rate gyroscope on a single chip
±300°/sec angular rate sensing
High vibration rejection over a wide frequency range
Excellent 25°/hr null offset stability
Internally temperature compensated
2000 g powered shock survivability
SPI digital output with 16-bit data-word
Low noise and low power
3.3 V and 5V operation
−40°C to +105°C operation
Ultra small, light, and RoHS compliant
Two package options
Low cost SOIC_CAV package for yaw rate (Z-axis) response
Innovative ceramic vertical mount package, which can be
oriented for pitch, roll, or yaw response
The ADXRS450 is an angular rate sensor (gyroscope) intended
for industrial, medical, instrumentation, stabilization, and other
high performance applications. An advanced, differential, quad
sensor design rejects the influence of linear acceleration, enabling
the ADXRS450 to operate in exceedingly harsh environments
where shock and vibration are present.
The ADXRS450 utilizes an internal, continuous self-test architecture. The integrity of the electromechanical system is checked
by applying a high frequency electrostatic force to the sense
structure to generate a rate signal that can be differentiated from
the baseband rate data and internally analyzed.
The ADXRS450 is capable of sensing angular rate of up to
±300°/sec. Angular rate data is presented as a 16-bit word, as
part of a 32-bit SPI message.
APPLICATIONS
The ADXRS450 is available in a cavity plastic 16-lead SOIC
(SOIC_CAV) and an SMT-compatible vertical mount package
(LCC_V), and is capable of operating across both a wide voltage
range (3.3 V to 5 V) and temperature range (−40°C to +105°C).
Rotation sensing medical applications
Rotation sensing industrial and instrumentation
High performance platform stabilization
FUNCTIONAL BLOCK DIAGRAM
VX
HIGH VOLTAGE
GENERATION
PDD
ADXRS450
LDO
REGULATOR
HV DRIVE
Z-AXIS ANGULAR
RATE SENSOR
Q DAQ
P DAQ
ADC 12
DECIMATION
FILTER
DEMOD
TEMPERATURE
CALIBRATION
FAULT
DETECTION
Q FILTER
REGISTERS/MEMORY
ALU
CLOCK
PHASE
DIVIDER
LOCKED
LOOP AMPLITUDE
DETECT
BAND-PASS
FILTER
DVDD
AVDD
SPI
INTERFACE
MOSI
MISO
SCLK
CS
DVSS
ST
CONTROL
PSS
EEPROM
AVSS
08952-001
CP5
Figure 1.
Rev. PrA
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©2010 Analog Devices, Inc. All rights reserved.
ADXRS450
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Circuits ................................................................. 10
Applications ....................................................................................... 1
ADXRS450 Signal Chain Timing ............................................. 10
General Description ......................................................................... 1
SPI Communication Protocol ....................................................... 12
Functional Block Diagram .............................................................. 1
Command/response ................................................................... 12
Specifications..................................................................................... 3
SPI Communications Characteristics...................................... 13
Absolute Maximum Ratings............................................................ 4
SPI Applications .......................................................................... 14
Thermal Resistance ...................................................................... 4
SPI Rate Data Format..................................................................... 19
Rate Sensitive Axis ........................................................................ 4
Memory Map and Registers .......................................................... 20
ESD Caution .................................................................................. 4
Memory Map .............................................................................. 20
Pin Configurations and Function Descriptions ........................... 5
Memory Register Definitions ................................................... 21
Typical Performance Characteristics ............................................. 7
Package Orientation and Layout information ............................ 23
Theory of Operation ........................................................................ 9
Solder Profile .............................................................................. 25
Continuous Self-Test .................................................................... 9
Package Marking Codes ............................................................ 26
Applications Information .............................................................. 10
Outline Dimensions ....................................................................... 27
Calibrated Performance ............................................................. 10
Ordering Guide .......................................................................... 28
Mechanical Considerations for Mounting .............................. 10
Rev. PrA | Page 2 of 28
Preliminary Technical Data
ADXRS450
SPECIFICATIONS
Specification conditions @ TA = TMIN to TMAX, PDD = 5 V, angular rate = 0°/sec, bandwidth = 80 Hz ±1 g, continuous self-test on.
Table 1.
Parameter
MEASUREMENT RANGE
SENSITIVITY
Nominal Sensitivity
Sensitivity Tolerance
Nonlinearity 1
Cross-Axis Sensitivity 2
NULL
Null Accuracy
NOISE PERFORMANCE
Rate Noise Density
LOW-PASS FILTER
Cut-Off (−3dB) Frequency
Group Delay 3
SHOCK AND VIBRATION IMMUNITY
Sensitivity to Linear Acceleration
Vibration Rectification
SELF-TEST
Magnitude
Fault Register Threshold
Sensor Data Status Threshold
Frequency
ST Low-Pass Filter
−3 dB Frequency
Group Delay3
SPI COMMUNICATIONS
Clock Frequency
Voltage Input High
Test Conditions/Comments
Full-scale range
See Figure 2
Symbol
FSR
Min
±300
Typ
80
±3
0.05
±3
Best fit straight line
TA = 25°C
f0/200, see Figure 6
f = 0 Hz
fLP
tLP
3.25
DC to 5 kHz
Max
±400
0.25
Unit
°/sec
LSB/°/sec
%
% FSR rms
%
±3
°/sec
0.015
°/sec/√Hz
80
4
Hz
ms
4.75
0.03
0.003
°/sec/g
°/sec/g2
See Continuous Self-Test
2559
Compared to LOCST data
Compared to LOCST data
f0/32
2239
1279
fST
2879
3839
500
f0/800, see Figure 7
52
2
64
LSB
LSB
LSB
Hz
76
Hz
ms
MHz
V
MOSI, CS, SCLK
0.85 × PDD
8.08
PDD + 0.3
Voltage Input Low
MOSI, CS SCLK
−0.3
PDD × 0.15
V
Output Voltage Low
Output Voltage High
MISO, current = 3 mA
MISO, current = −2 mA
0.5
V
V
Pull up Current
CS, PDD = 3.3 V, CS = 0.75 × PDD
50
200
μA
CS, PDD = 5 V, CS = 0.75 × PDD
70
300
μA
MEMORY REGISTERS
Temperature Sensor
Value at 45°C
Scale Factor
Quad, ST, Rate, DNC Registers
Scale Factor
POWER SUPPLY
Supply Voltage
Quiescent Supply Current
Turn-On Time
TEMPERATURE RANGE
PDD − 0.5
See Memory Register Definitions
Power on to 0.5°/sec of final
Independent of package type
PDD
IDD
3.15
TMIN, TMAX
−40
1
Rev. PrA | Page 3 of 28
LSB
LSB/°C
80
LSB/°/sec
6.0
100
Maximum limit is guaranteed through ADI characterization.
Cross-axis sensitivity specification does not include effects due to device mounting on a printed circuit board (PCB).
3
Minimum and maximum limits are guaranteed by design.
2
0
5
5.25
10.0
+105
V
mA
ms
°C
ADXRS450
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
RATE SENSITIVE AXIS
Parameter
Acceleration (Any Axis, Unpowered, 0.5 ms)
Acceleration (Any Axis, Powered, 0.5 ms)
Supply Voltage (PDD)
Output Short-Circuit Duration (Any Pin to
Ground)
Temperature Range
Operating
LCC_V Package
SOIC_CAV Package
Storage
LCC_V Package
SOIC_CAV Package
Rating
2000 g
2000 g
−0.3 V to +6.0 V
Indefinite
−40°C to +125°C
−40°C to +125°C
−65°C to +150°C
−40°C to +150°C
The ADXRS450 is available in two package options. The
SOIC_CAV package configuration is for applications that
require a Z-axis (yaw) rate sensing device. The device transmits
a positive going LSB count for clockwise rotation about the axis
normal to the package top. Conversely, a negative going LSB
count is transmitted for counterclockwise rotation about the
Z-zxis. The vertical mount package (LCC_V) option is for
applications that require rate sensing in the axes parallel to the
plane of the PCB (pitch and roll). The same principles of LSB
count transmission for clockwise and counterclockwise rotation
about the parallel axes apply to the LCC_V option. See Figure 2
for details.
RATE
AXIS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, for a device
soldered in a printed circuit board (PCB) for surface-mount
packages.
Z-AXIS
LONGITUDINAL
AXIS
7
1
A1
θJA
191.5
185.5
θJC
25
23
ABCDEFG
LATERAL AXIS
RATE
AXIS
+
8
7
1
VMP PACKAGE
Figure 2. Rate Signal Increases with Clockwise Rotation
ESD CAUTION
Table 3. Thermal Resistance
Package Type
16-Lead SOIC_CAV
14-Lead Ceramic LCC_V
+
Unit
°C/W
°C/W
Rev. PrA | Page 4 of 28
08952-002
Table 2.
Preliminary Technical Data
ADXRS450
DVDD
1
16
SCLK
RSVD
2
15
MOSI
RSVD
3
14
AVDD
CS
4
13
DVSS
MISO
5
12
RSVD
PDD
6
11
AVSS
PSS
7
10
RSVD
VX
8
9
ADXRS450
TOP VIEW
(Not to Scale)
CP5
08952-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. SOIC_CAV Pin Configuration
Table 4. 14-Lead SOIC_CAV Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
DVDD
RSVD
NC
CS
Description
Digital Regulated Voltage. See Figure 21 for the applications circuit diagram.
Reserved. This pin must be connected to DVSS.
Reserved. This pin must be connected to DVSS.
Chip Select.
5
6
7
8
9
10
11
12
13
14
15
16
MISO
PDD
PSS
VX
CP5
NC
AVSS
NC
DVSS
AVDD
MOSI
SCLK
Master In/Slave Out.
Supply Voltage.
Switching Regulator Ground.
High Voltage Switching Node. See Figure 21 for the applications circuit diagram.
High Voltage Supply. See Figure 21 for the applications circuit diagram.
Reserved. This pin must be connected to DVSS.
Analog Ground.
Reserved. This pin must be connected to DVSS.
Digital Signal Ground.
Analog Regulated Voltage. See Figure 21 for the applications circuit diagram.
Master Out/Slave In.
SPI Clock.
Rev. PrA | Page 5 of 28
SCLK
DVDD
MISO
AVDD
AVSS
RSVD
VX
TOP VIEW
(Not to Scale)
NC = NO
CONNECT
Figure 4. LCC_V Pin Configuration
BACK VIEW
(Not to Scale)
14
08952-037
7
PDD
6
CS
5
PSS
CP5
9 10 11 12 13
4
CS
DVSS
MOSI
RSVD
8
3
08952-005
RSVD
1
9
RSVD
2
VX
5 4 3
11 10
CP5
AVDD
6
DVSS
2
7
12
SCLK
1
8
MOSI
13
DVDD
PSS
14
MISO
PDD
Preliminary Technical Data
AVSS
ADXRS450
Figure 5. LCC_V Pin Configuration, Horizontal Layout
Table 5. 14_Lead LCC_V Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
AVSS
AVDD
MISO
DVDD
SCLK
CP5
RSVD
RSVD
VX
CS
Description
Analog Ground.
Analog Regulated Voltage. See Figure 22 for the applications circuit diagram.
Master In/Slave Out.
Digital Regulated Voltage. See Figure 22 for the applications circuit diagram.
SPI Clock.
High Voltage Supply. See Figure 22 for the applications circuit diagram.
Reserved. This pin must be connected to DVSS.
Reserved. This pin must be connected to DVSS.
High Voltage Switching Node. See Figure 22 for the applications circuit diagram.
Chip Select.
11
12
13
14
DVSS
MOSI
PSS
PDD
Digital Signal Ground.
Master Out/Slave In.
Switching Regulator Ground.
Supply Voltage.
Rev. PrA | Page 6 of 28
Preliminary Technical Data
ADXRS450
TYPICAL PERFORMANCE CHARACTERISTICS
0.40
0.20
0.18
0.35
0.16
% OF POPULATION
% OF POPULATION
0.30
0.14
0.12
0.10
0.08
0.06
0.25
0.20
0.15
0.10
0.04
2.0
ERROR (°/sec)
0
–2.0
08952-006
1.6
1.2
–1.6 –1.2
0.30
0.25
0.25
3.0
08952-010
2.5
2.0
1.5
1.0
0
–0.5
CHANGE IN SENSITIVITY (%)
Figure 8. SOIC_CAV Sensitivity Error @ 25°C
Figure 11. LCC_V Sensitivity Error @ 25°C
Rev. PrA | Page 7 of 28
08952-029
0.020
0.015
0.010
0.005
0
–0.005
–0.010
3.0
08952-008
2.5
2.0
0
1.5
0
1.0
0.05
0
0.05
–0.015
0.10
–0.025
0.10
0.15
–0.030
0.15
0.5
0.030
0.20
–0.5
0.025
0.20
% OF POPULATION
0.25
–1.0
2.0
Figure 10. LCC_V Null Drift over Temperature
0.25
–1.5
1.6
ERROR (°/sec)
Figure 7. SOIC_CAV Null Drift over Temperature
CHANGE IN SENSITIVITY (%)
–0.5
–3.0
3.0
ERROR (°/sec)
08952-007
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
0
–1.5
0
–2.0
0.05
–2.5
0.05
–2.0
1.2
0.10
–1.0
0.10
–2.5
0.8
0.15
–1.5
0.15
–3.0
0.4
0.20
–2.0
0.20
–2.5
% OF POPULATION
0.30
–3.0
% OF POPULATION
0
Figure 9. LCC_V Null Error @ 25°C
Figure 6. SOIC_CAV Null Error @ 25°C
% OF POPULATION
–0.8 –0.4
ERROR (°/sec)
–0.020
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
–2.0
0
08952-009
0.05
0.02
ADXRS450
Preliminary Technical Data
0.45
0.30
0.40
0.25
% OF POPULATION
% OF POPULATION
0.35
0.20
0.15
0.10
0.30
0.25
0.20
0.15
0.10
0.05
CHANGE IN SENSITIVITY (%)
Figure 12. SOIC_CAV Sensitivity Drift over Temperature
Figure 15. LCC_V Sensitivity Drift over Temperature
40
60
DUT1
DUT2
DUT AVERAGE (°/s)
REF
GYRO OUTPUT (°/s)
20
(g2/Hz)
0.1
0.001
0
1k
2k
3k
4k
5k
6k
VIBRATION FREQUENCY (Hz)
30
0
20
–10
10
–20
0
–30
–10
0.15
0.20
0.25
0.30
–20
0.40
0.35
TIME (sec)
Figure 13. Typical Response to Random Vibration, 15 g rms, 50 Hz to 5 kHz
Figure 16. Typical Shock Response
3
3
N = 16
N = 16
2
1
1
0
0
–1
–2
–2
–30
–10
10
30
50
70
90
110
DUT TEMPERATURE (°C)
08952-032
–1
Figure 14. Null Output over Temperature, Device Soldered on PCB
–3
–50
–30
–10
10
30
50
70
90
110
DUT TEMPERATURE (°C)
Figure 17. Sensitivity over Temperature, Device Soldered to PCB
Rev. PrA | Page 8 of 28
08952-035
% ERROR
2
–3
–50
40
10
–40
0.1
08952-031
0.01
50
INPUT ACCELERATION (g)
30
08952-034
1
(°/sec)
3
2
1
0
–1
–3
08952-030
3
2
1
0
–1
–2
–3
DRIFT (%)
–2
0
0
08952-033
0.05
Preliminary Technical Data
ADXRS450
THEORY OF OPERATION
When the sensing structure is exposed to angular rate, the
resulting Coriolis force couples into an outer sense frame,
which contains movable fingers that are placed between fixed
pickoff fingers. This forms a capacitive pickoff structure that
senses Coriolis motion. The resulting signal is fed to a series of
gain and demodulation stages that produce the electrical rate
signal output. The quad sensor design rejects linear and angular
acceleration, including external g-forces and vibration. This is
achieved by mechanically coupling the four sensing structures
such that external g-forces appear as common-mode signals
that can be removed by the fully differential architecture
implemented in the ADXRS450.
CONTINUOUS SELF-TEST
The ADXRS450 gyroscope utilizes a complete electromechanical self test. An electrostatic force is applied to the
gyroscope frame, resulting in a deflection of the capacitive
sense fingers. This deflection is exactly equivalent to deflection
that occurs as a result of external rate input. The output from
the beam structure is processed by the same signal chain as a
true rate output signal, providing complete coverage of both the
electrical and mechanical components.
The electromechanical self test is performed continuously
during operation at a rate higher than the output bandwidth of
the device. The self-test routine generates equivalent positive
and negative rate deflections. This information can then be
filtered with no overall effect on the demodulated rate output.
RATE SIGNAL WITH
CONTINUOUS SELF TEST SIGNAL.
SELF TEST AMPLITUDE. INTERNALLY
COMPARED TO THE SPECIFICATION
TABLE LIMITS.
LOW FREQUENCY RATE INFORMATION.
08952-012
The ADXRS450 operates on the principle of a resonator gyroscope. Figure 18 shows a simplified version of one of four
polysilicon sensing structures. Each sensing structure contains a
dither frame that is electrostatically driven to resonance. This
produces the necessary velocity element to produce a Coriolis
force when experiencing angular rate. In the SOIC_CAV
package, the ADXRS450 is designed to sense a Z-axis (yaw)
angular rate; whereas the vertical mount package orients the
device such that it can sense pitch or roll angular rate on the
same PCB.
Figure 19. Continuous Self-Test Demodulation
X
Y
08952-011
Z
Figure 18. Simplified Gyroscope Sensing Structure
The resonator requires 22.5 V (typical) for operation. Because
only 5 V is typically available in most applications, a switching
regulator is included on-chip.
The difference amplitude between the positive and negative
self-test deflections is filtered to 2 Hz, and continuously
monitored and compared to hardcoded self-test limits. If the
measured amplitude exceeds these limits (listed in Table 1), one
of two error conditions is asserted depending on the magnitude
of self-test error. For less severe self-test error magnitudes, the
CST bit of the fault register is asserted; however, the status bits
(ST[1:0]) in the sensor data response remain set to 0b01 for
valid sensor data. For more severe self-test errors, the CST bit of
the fault register is asserted and the status bits (ST[1:0]) in the
sensor data response are set to 0b00 for invalid sensor data. The
thresholds for both of these failure conditions are listed in Table
1. If desired, the user can access the self-test information by
issuing a read command to the self-test memory register
(Address 0x04). See the SPI Communication Protocol section
for more information about error reporting.
Rev. PrA | Page 9 of 28
ADXRS450
Preliminary Technical Data
APPLICATIONS INFORMATION
CALIBRATED PERFORMANCE
1 DVDD
1µF
Each ADXRS450 gyroscope uses internal EEPROM memory to
store its temperature calibration information. The calibration
information is encoded into the device during factory test. The
calibration data is used to perform offset, gain, and self-test
corrections over temperature. By storing this information
internally, it removes the burden from the customer of
performing system level temperature calibration.
GND
3.3V TO 5V
MOSI
RSVD
AVDD
CS
DVSS
MISO
RSVD
PDD
AVSS
PSS
RSVD
VX
CP5
1µF
100nF
GND
DIODE
>24V BREAKDOWN
Figure 21. Recommended Applications Circuit, SOIC_CAV Package
3.3V TO 5V
TOP VIEW
1
14
AVSS
PDD
AVDD
PSS
MISO
MOSI
DVDD
DVSS
SCLK
CS
CP5
VX
1µF
1µF
1µF
RSVD
470µH
RSVD
08952-013
GND
DIODE
>24V BREAKDOWN
APPLICATIONS CIRCUITS
Figure 21 and Figure 22 show the recommended application
circuits for the ADXRS450 gyroscope. These application circuits
provide a connection reference for the available package types.
Note that DVDD, AVDD, and PDD are all individually connected to
ground through 1 μF capacitors; do not connect these supplies
together. Additionally, an external diode and inductor must be
connected for proper operation of the internal shunt regulator.
These components allow for the internal resonator drive voltage
to reach its required level, as listed in the Specifications section.
Table 6.
Description
470 μH
>24 V breakdown voltage
1 μF
100 nF
08952-015
GND
Figure 20. Incorrectly Placed Gyroscope
Qty
1
1
3
1
GND
100nF
PCB
Component
Inductor
Diode
Capacitor
Capacitor
08952-014
470µH
GND
GYROSCOPE
MOUNTING POINTS
RSVD
1µF
MECHANICAL CONSIDERATIONS FOR MOUNTING
Mount the ADXRS450 in a location close to a hard mounting
point of the PCB to the case. Mounting the ADXRS450 at an
unsupported PCB location (that is, at the end of a lever, or in
the middle of a trampoline), as shown in Figure 20, can result in
apparent measurement errors, as the gyroscope is subject to the
resonant vibration of the PCB. Locating the gyroscope near a
hard mounting point helps to ensure that any PCB resonances
at the gyroscope are above the frequency at which harmful
aliasing with the internal electronics can occur. To ensure that
aliased signals do not couple into the baseband measurement
range, design the module wherein the first system level
resonance occurs at a frequency higher than 800 Hz.
SCLK 16
Figure 22. Recommended Applications Circuit, Ceramic LCC_V Package
ADXRS450 SIGNAL CHAIN TIMING
The ADXRS450 primary signal chain is shown in Figure 23. It is
the series of necessary functional circuit blocks through which
the rate data is generated and processed. This sequence of electromechanical elements determines how quickly the device is capable
of translating an external rate input stimulus into an SPI word
to be sent to the master device. The group delay, which is a function of the filter characteristic, is the time required for the output
of the low-pass filter to be within 10% of the external rate input,
and is seen to be ~4 ms. Additional delay can be observed due
to the timing of SPI transactions and the population of the rate
data into the internal device registers. Figure 23 anatomizes this
delay, wherein the delay through each element of the signal chain
is presented.
Rev. PrA | Page 10 of 28
Preliminary Technical Data
ADXRS450
The transfer function for the Continuous Self-Test LPF is given as
The transfer function for the Rate Data LPF is given as
⎡ 1 − Z −64 ⎤
⎢
−1 ⎥
⎣ 1− Z ⎦
2
1
64 − 63Z −1
where:
16
T=
= 1ms (typ)
f0
where:
1
1
=
f 0 16 kHz (typ)
PRIMARY SIGNAL CHAIN
4ms
GROUP DELAY
<5µs
DELAY
BAND-PASS
FILTER
ARITHMETIC
LOGIC UNIT
<5µs
DELAY
ADC 12
DEMOD
RATE DATA
LPF
CONTINUOUS
SELF-TEST
LPF
Z-AXIS ANGULAR
RATE SENSOR
<64ms
GROUP DELAY
Figure 23. Primary Signal Chain and Associated Delays
Rev. PrA | Page 11 of 28
<2.2ms
DELAY
SPI
TRANSACTION
08952-016
<5µs
DELAY
REGISTERS/MEMORY
T=
ADXRS450
Preliminary Technical Data
SPI COMMUNICATION PROTOCOL
COMMAND/RESPONSE
Input/output is handled through a 32-bit, command/response
SPI interface. The command set and the format for the interface
is defined as follows:
Clock phase = clock polarity = 0
Additionally, the device response to the initial command is
0x00000001. This prevents the transmission of random data to
the master device upon the initial command/response exchange.
Table 7. SPI Signals
Signal
Symbol
Description
Serial Clock
SCLK
Exactly 32 clock cycles during CS active
Chip Select
CS
Active low
Master Out
Slave In
Master In
Slave Out
MOSI
Data sent to the gyroscope device
from the main controller
Data sent to the main controller
from the gyroscope
MISO
CS
32 CLOCK
CYCLES
32 CLOCK
CYCLES
COMMAND N
COMMAND N + 1
SCLK
MOSI
08952-017
MISO
RESPONSE N
RESPONSE N – 1
Figure 24. SPI Protocol
Table 8. SPI Commands
Bit
Command 31
30
29 28
27
26
25 24 23 22 21 20 19 18 17 16
15
14
13
12
11
10 9
8
7
6
5
4
3
2
1
0
Sensor
Data
SQ1 SQ0 1
SQ2
CHK P
Read
1
0
0
SM2 SM1 SM0 A8 A7 A6 A5 A4 A3 A2 A1 A0
P
Write
0
1
0
SM2 SM1 SM0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
P
Table 9. SPI Responses
Bit
Command 31 30 29 28 27 26 25 24 23
22
21
20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Sensor
Data
SQ2 SQ1 SQ0 P0 ST1 ST0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Read
0
1
0
P0 1
1
1
0
SM2 SM1 SM0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
P1
Write
0
0
1
P0 1
1
1
0
SM2 SM1 SM0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
P1
R/W
Error
0
0
0
P0 1
1
1
0
SM2 SM1 SM0 0
0
SPI RE
DU
Rev. PrA | Page 12 of 28
PLL Q NVM POR PWR CST CHK P1
PLL Q NVM POR PWR CST CHK P1
Preliminary Technical Data
ADXRS450
SPI COMMUNICATIONS CHARACTERISTICS
Table 10. SPI Command/Response Timing Characteristics
Note the following conditions for Table 10:
Symbol
fOP
•
•
•
•
•
•
•
All minimum and maximum timing values are guaranteed
through characterization.
All timing is shown with respect to 10% VDD and 90% of
the actual delivered voltage waveform.
All minimum and maximum timing values are valid for
3.0 V ≤ VDD ≤ 5.5 V.
Capacitive load for all signals is assumed to be ≤80 pF.
Ambient temperature is –40°C ≤ TA ≤ +105°C.
MISO pull-up of 47 kΩ or 110 μA.
Sequential transfer increases to 17 ms following any write
operation limited by the EEPROM.
tSCLKH
tSCLKL
tSCLK
tF
tR
tSU
tHIGH
tA
tV
tLAG
tDIS
tLEAD
tLAG_CS
tTD
f0
Rev. PrA | Page 13 of 28
Description
SPI operating
frequency
Clock (SCLK)
high time
Clock (SCLK) low
time
SCLK period
Clock (SCLK) fall
time
Clock (SCLK) rise
time
Data input
(MOSI) setup
time
Data input
(MOSI) hold time
Data output
(MISO) access
time
Data output
(MISO) valid after
SCLK
Data output
(MISO) lag time
Data output
(MISO) disable
time
Enable (CS) lead
time
Enable (CS) lag
time
Sequential
transfer delay
Gyroscope
resonant
frequency
Min
Max
8.08
Unit
MHz
1/2tSCLK − 13
ns
1/2tSCLK − 13
ns
123.7
5.5
13
ns
ns
5.5
13
ns
37
ns
49
ns
20
ns
20
ns
TBD
ns
40
ns
1/2tSCLK
ns
1/2tSCLK
ns
0.16
μs
13
19
kHz
ADXRS450
Preliminary Technical Data
CS
tSCLK
tSCLKH
tLEAD
tSCLKL
tR
tF
f0
tCS
SCK
tA
tLAG
tV
tDIS
MSB
MISO
LSB
tHIGH
tSU
MOSI
LSB
08952-018
MSB
Figure 25. SPI Timings
preparation for the next sequential command/ response
exchange. This allows for an exceedingly fast sequential transfer
delay of 0.1 μs (see Table 10). As a design precaution, note that
the transmitted data is only as recent as the sequential
transmission delay implemented by the system. Conditions that
result in a sequential transfer delay of several seconds cause the
next sequential device response to contain data that is several
seconds old.
SPI APPLICATIONS
Device Data Latching
To allow for rapid acquisition of data from the ADXRS450,
device data latching has been implemented in the design, as shown
in Figure 26. Upon the assertion of chip select (CS), the data
present in the device is latched into memory. When the full
MOSI command has been received, and CS deasserted, the
appropriate data is shifted into the SPI port registers in
DEVICE DATA IS LATCHED AFTER THE
ASSERTION OF CS. LATCHED DATA IS
TRANSMITTED DURING THE NEXT
SEQUENTIAL COMMAND/RESPONSE
EXCHANGE.
CS
32 CLOCK
CYCLES
32 CLOCK
CYCLES
MOSI
COMMAND N
0x…
COMMAND N + 1
0x…
MISO
RESPONSE N – 1
0x00000001
RESPONSE N
0x…
Figure 26. Device Data Latching
Rev. PrA | Page 14 of 28
32 CLOCK
CYCLES
COMMAND N + 2
0x…
RESPONSE N + 1
0x…
08952-019
SCLK
Preliminary Technical Data
ADXRS450
Command/Response—Bit Definitions
Table 11. Quick Guide—Bit Definitions for SPI Interface
Bit
SQ2 to SQ0
SM2 to SM0
A8 to A0
D15 to D0
SPI
ST1 to ST0
P
P0
P1
RE
DU
ST1 to ST0
Description
Sequence bits (from master)
Sensor module bits (from master)
Register address
Data
SPI command/response
Status bits
Command odd parity
Response, odd parity, Bits[31:16]
Response, odd parity, Bits[31:0]
Request error
Data unavailable
The status bits (ST1 and ST0) are used to signal to the master
device the type of data contained in the response message. The
status bits are decoded as listed in Table 12.
Table 12. Status Bit Code Definitions
ST1:ST0
00
01
10
11
SQ2 to SQ0
This field provides the system with a means of synchronizing
the data samples that are received from multiple sensors. To
facilitate correct synchronization, the ADXRS450 gyroscope
includes the SQ[2:0] field in the response sequence as it was
received in the request.
SM2 to SM0
Sensor module bits from master device. These bits have not
been implemented in the ADXRS450, and are hard coded to be
000 for all occurrences.
A8 to A0
D15 to D0
16-bit device data that can contain any of the following:
•
•
•
Content in Bits[D15:D0]
Error data for sensor data response
Valid sensor data
Sensor self-test data
Read/write response
There are two independent conditions that can result in the ST
bits being set to 0b00 during a sensor data response: self test or
PLL. The self test response is sufficiently different from its
nominal value. Refer to the Specifications section for the
appropriate limits. When the sensor data response is a PLL, the
PLL fault is active.
P
A parity bit (P) is required for all master-to-slave data
transmissions. Communications protocol requires one parity bit
to achieve odd parity for the entire 32-bit command. Bits that
are in don’t care positions are still factored into the parity
calculation.
P0
The A8 to A0 bits represent the memory address from which
device data is being read, or to which information is to be
written. These bits should only be supplied by the master when
the memory registers are being accessed, and are ignored for all
sensor data requests. Refer to the Memory Register Definitions
section for a complete description of the available memory
registers.
•
during a sensor data request results in the device issuing a
read/write error.
Master: data to be written to a memory register as specified
in the A8 to A0 section.
Slave: sensor rate output data.
Slave: device data read from the memory register specified
in the A8 to A0 section, as well as the data from the next
sequential register.
Slave: For a write command, the 16-bit data that is written
to the specified memory register reflects back to the master
device for correlation.
SPI
The SPI bit sets when any either of the following occur: too
many/not enough bits are transmitted, or the message from the
control module contains a parity error. Additionally, any error
P0 is the parity bit that establishes odd parity for Bits[31:16] of
the device response.
P1
P1 is the parity bit that establishes odd parity for the entire
32-bit device response.
RE
RE is the communications error bit transmitted from the
ADXRS450 device to the control module. Request errors can
occur when
•
•
•
An invalid command is sent from the control module.
The read/write command specifies an invalid memory
register.
The write command attempted to a nonwriteable memory
register.
DU
As expressed in Table 10, the sequential transfer delay for
writing data to a memory register (for example, DNC0) results
in a sequential transfer delay of 17 ms. If a successive write
command is issued to the device prior to the completion of the
sequential transfer delay, the command is ignored and the
device issues a DU error response. However, a read command
Rev. PrA | Page 15 of 28
ADXRS450
Preliminary Technical Data
or sensor data request can be issued after a sequential transfer
delay of only 10 μs is observed. Regardless of the commands
that are subsequently issued to the device, once a write procedure
has been initiated, the operation proceeds through to completion
(requiring 17 ms).
Fault Register Bit Definitions
NVM
An NVM error transmits to the control module when the
internal NVM data fails a checksum calculation. This check is
performed once every 50 μs, and does not include the DNC0 or
PID memory registers.
POR
This section describes the bits available for signaling faults to
the user. The individual bits of the fault register are updated
asynchronously depending on their respective detection
criteria; however, it is recommended that the fault register is
read at a rate of at least 250 Hz. When asserted, the individual
status bit does not deassert until it is read by the master device.
If the error persists after a fault register read, the status bit
immediately reasserts, and remains asserted until the next
sequential command/response exchange. The full fault register
is appended to every sensor data request. It can also be accessed
by issuing a read command to Register 0x0A.
Table 13. Quick Guide—Fault Register Bit Definitions
Bit Name
Description
PLL
Q
NVM
POR
UV
Amp
PWR
CST
CHK
OV
Fail
PLL failure
Quadrature error
NVM memory fault
Power-on reset failed to initialize
Regulator under voltage
Amplitude detection failure
Power regulation failed: overvoltage/undervoltage
Continuous self-test failure
Check: generate faults
Regulator overvoltage
Failure which sets the ST[1:0] bits to 0b00
PLL
PLL is the bit indicating that the device has had a failure in the
phase locked-loop functional circuit block. This occurs when
the PLL has failed to achieve sync with the resonator structure.
If the PLL status flag is active, the ST bits of the sensor data
response set to 0b00, indicating that the response contains
potentially invalid rate data.
Q
A Q fault can be asserted based on two independent quadrature
calculations. Located in the quad memory (Register 0x08) is a
value corresponding to the total instantaneous quadrature present
in the device. If this value exceeds 4096 LSB, a Q fault is issued.
Because quadrature build-up can contribute to an offset error,
the ADXRS450 has integrated methods for dynamically cancelling
the effects of quadrature. An internal quadrature accumulator
records the amount of quadrature correction performed by the
ADXRS450. Excessive quadrature is associated with offset errors.
A Q fault is issued once the quadrature error present in the device
has contributed to an equivalent of 4°/sec (typical) of rate offset.
An internal check is performed on device startup to ensure that
the volatile memory of the device is functional. This is accomplished by programming a known value from the device ROM
into a volatile memory register. This value is then continuously
compared to the known value in ROM every 1 μs for the duration
of the device’s operation. If the value stored in the volatile memory
changes, or does not match the value stored in ROM, the POR
error flag is asserted. The value stored in ROM is rewritten to
the volatile memory upon a device power cycle.
PWR
The device performs a continuous check of the internal 3 V
regulated voltage level. If either an overvoltage (OV) or undervoltage (UV) fault is asserted, then the PWR bit is also asserted.
This condition occurs if the regulated voltage is observed to be
either above 3.3 V or below 2.77 V. An internal low-pass filter
removes high frequency glitching effects to prevent the PWR bit
from asserting unnecessarily. To determine if the fault is a result
of an overvoltage or undervoltage condition, the OV and UV
fault bits must be analyzed.
CST
The ADXRS450 is designed with continuous self-test functionality.
Measured self-test amplitudes are compared against the limits
presented in Table 1. Deviations from this value result in
reported self-test errors. There are two thresholds for a self-test
failure.
•
•
Self-test value > ±512 LSB from nominal results in an
assertion of the self-test flag in the fault register
Self-test value > ±1856 LSB from nominal results in both
an assertion of the self-test flag in the fault register as well
as setting the ST[1:0] bits to 0b00, indicating that the rate
data contained in the sensor data response is potentially
invalid.
CHK
The CHK bit is transmitted by the control module to the
ADXRS450 as a method of generating faults. By asserting the
CHK bit, the device creates conditions that result in the
generation of all faults represented through the fault register.
For example, the self-test amplitude is deliberately altered to
exceed the fault detection threshold, resulting in a self test error.
In this way, the device is capable of checking both its ability to
detect a fault condition, as well as its ability to report that fault
to the control module.
Rev. PrA | Page 16 of 28
Preliminary Technical Data
ADXRS450
The fault conditions are initiated nearly simultaneously;
however, the timing for receiving fault codes when the CHK bit
is asserted is dependent upon the time required to generate
each unique fault. It takes no more than 50 ms for all of the
internal faults to be generated, and the fault register updated to
reflect the condition of the device. Until the CHK bit is cleared,
the status bits (ST[1:0]) are set to 0b10, indicating that the data
should be interpreted by the control module as self-test data.
After the CHK bit is deasserted, the fault conditions require an
additional 50 ms to decay, and the device to return to normal
operation. Refer to Figure 21 for the proper methodology for
asserting the check bit.
OV
The OV fault bit asserts if the internally regulated voltage
(nominally 3 V) is observed to exceed 3.3 V. This measurement
is low-pass filtered to prevent artifacts such as noise spikes from
asserting a fault condition. When an OV fault has occurred, the
PWR fault bit is asserted simultaneously. Because the OV fault
bit is not transmitted as part of a sensor data request, it is
recommended that the user read back the FAULT1 and FAULT0
memory registers upon the assertion of a PWR error. This
allows the user to determine the specific error condition.
UV
The UV fault bit asserts if the internally regulated voltage
(nominally 3 V) is observed to be less than 2.77 V. This
measurement is low-pass filtered to prevent artifacts such as
noise spikes from asserting a fault condition. When a UV fault
has occurred, the PWR fault bit is asserted simultaneously. As
the UV fault bit is not transmitted as part of a sensor data
request, it is recommended that the user read back the FAULT1
and FAULT0 memory registers upon the assertion of a PWR
error. This allows the user to determine the specific error
condition.
FAIL
The fail flag is asserted when a condition arises such that the
ST[0:1] bits are set to 0b00. This indicates that the device has
experienced a gross failure, and that the sensor data could
potentially be invalid.
AMP
The amp fault bit is asserted when the measured amplitude of
the silicon resonator has been significantly reduced. This
condition can occur if the voltage supplied to CP5 has fallen
below the requirements of the internal voltage regulator. This
fault bit is OR’ed with the CST fault such that during a sensor
data request, the CST bit position represents either an amp
failure or a CST failure. The full status register can then be read
from memory to validate the specific failure.
K-Bit Assertion: Recommended Start-Up Routine
The following diagram illustrates a recommended start-up
routine that can be implemented by the user. Alternate start-up
sequences can be employed; however, ensure that the response
from the ADXRS450 is handled correctly. If implemented
immediately after power is applied to the device, the total time
to implement the following fault detection routine is approximately 200 ms. As described in the Device Data Latching
section, the data present in the device upon the assertion of the
CS signal is used in the next sequential command/response
exchange. This results in an apparent one transaction delay
before the data resulting from the assertion of the CHK
command is reported by the device. For all other read/write
interactions with the device, no such delay exists, and the MOSI
command is serviced during the next sequential command/
response exchange. Note that when the CHK bit is deasserted, if
the user tries to obtain data from the device before the CST
fault flag has cleared, the device reports the data as error data.
Rev. PrA | Page 17 of 28
ADXRS450
Preliminary Technical Data
MOSI: SENSOR DATA
REQUEST THIS CLEARS
THE CHK BIT
MISO: STANDARD INITIAL
RESPONSE
MISO: SENSOR DATA
RESPONSE
DATA LATCH POINT
CS
X
SCLK
32 CLOCK
CYCLES
MOSI
0x2000003
MISO
0x0000001
t = 100ms
POWER IS
APPLIED TO
THE DEVICE.
WAIT 100ms TO
ALLOW FOR
THE INTERNAL
CIRCUITRY TO
BE INITIALIZED.
ONCE THE 100ms START-UP
TIME HAS OCCURRED, THE
MASTER DEVICE IS FREE TO
ASSERT THE CHK
COMMAND AND START THE
PROCESS OF INTERNAL
ERROR CHECKING. DURING
THE FIRST COMMAND/
RESPONSE EXCHANGE
AFTER POWER ON, THE
ADXRS450 HAS BEEN
DESIGNED TO ISSUE A
PREDEFINED RESPONSE.
MOSI: SENSOR DATA
REQUEST
MISO: CHK RESPONSE
ST[1:0] = 0b10
MISO: CHK RESPONSE
ST[1:0] = 0b10
X
32 CLOCK
CYCLES
t = 150ms
MOSI: SENSOR DATA
REQUEST
X
32 CLOCK
CYCLES
32 CLOCK
CYCLES
0x2000000
0x2000000
0x2000000
0x…
0x…FF OR 0x…FE
(PARITY DEPENDENT)
0x…FF OR 0x…FE
(PARITY DEPENDENT)
t = 200ms
A 50ms DELAY IS REQUIRED
SO THAT THE GENERATION
OF FAULTS WITHIN THE
DEVICE IS ALLOWED TO
COMPLETE. HOWEVER, AS
THE DEVICE DATA IS
LATCHED BEFORE THE CHK
COMMAND IS ASSERTED,
THE DEVICE RESPONSE
DURING THIS
COMMAND/RESPONSE
EXCHANGE DOES NOT
CONTAIN FAULT
INFORMATION. THIS
RESPONSE CAN BE
DISCARDED.
t = 200ms + tTD
ANOTHER 50ms DELAY
NEEDS TO BE OBSERVED TO
ALLOW THE FAULT
CONDITIONS TO CLEAR. IF
THE DEVICE IS FUNCTIONING
PROPERLY, THE MISO
RESPONSE CONTAINS ALL
ACTIVE FAULTS, AS WELL AS
HAVING SET THE MESSAGE
FORMAT TO SELF-TEST
DATA. THIS IS INDICATED
THROUGH THE ST BITS
BEING SET TO 0b10.
Figure 27. Recommended Startup Sequence
Rev. PrA | Page 18 of 28
t = 200ms + 2tTD
THE FAULT BITS OF THE
ADXRS450 REMAIN ACTIVE
UNTIL CLEARED. DUE TO
THE REQUIRED DECAY
PERIOD FOR EACH FAULT
CONDITION, FAULT
CONDITIONS REMAIN
PRESENT UPON THE
IMMEDIATE DEASSERTION
OF THE CHK COMMAND. THIS
RESULTS IN A SECOND
SEQUENTIAL RESPONSE IN
WHICH THE FAULT BITS ARE
ASSERTED. AGAIN, THE
RESPONSE IS FORMATTED
AS SELF-TEST DATA
INDICATING THAT THE FAULT
BITS HAVE BEEN SET
INTENTIONALLY.
ALL FAULT
CONDITIONS ARE
CLEARED, AND ALL
SUBSEQUENT DATA
EXCHANGES NEED
ONLY OBSERVE
THE SEQUENTIAL
TRANSFER DELAY
TIMING
PARAMETER.
08952-020
MOSI: SENSOR DATA REQUEST
CHK COMMAND ASSERTED
Preliminary Technical Data
ADXRS450
SPI RATE DATA FORMAT
The ADXRS450 gyroscope transmits rate data in a 16-bit format,
as part of a 32-bit SPI data frame. See Table 9 for the full 32-bit
format of the sensor data request response. The rate data is transmitted MSB first, from D15 to D0. The data is formatted as a
twos complement number, with a scale factor of 80 LSB/°/sec.
Therefore, the highest obtainable value for positive (clockwise)
rotation is 0x7FFF (decimal +32,767), and for counterclockwise
rotation is 0x8000 (decimal −32,768). Performance of the device
is not guaranteed above ±24,000 LSB (±300°/sec).
Table 14. Rate Data
14-Bit Rate Data
Decimal (LSBs)
+32767
…
+24000
…
+160
+80
…
+40
+20
…
0
…
−20
−40
…
−80
−160
…
−24000
…
−32768
Hex (D15:D0)
0x7FFF
…
0x5DC0
…
0x00A0
0x0050
…
0x0028
0x0014
…
0x 0000
…
0xFFEC
0xFFD8
…
0xFFB0
0xFF60
…
0xA240
…
0x8000
Data Type
Rate data (not guaranteed)
…
Rate data
…
Rate data
Rate data
…
Rate data
Rate data
…
Rate data
…
Rate data
Rate data
…
Rate data
Rate data
…
Rate data
…
Rate data (not guaranteed)
Description
Maximum possible positive data value
…
+300 degrees per second rotation (positive FSR)
…
+2 degrees per second rotation
+1 degree per second rotation
…
+1/2 degree per second rotation
+1/4 degree per second rotation
…
Zero rotation value
…
−1/4 degree per second rotation
−1/2 degree per second rotation
…
−1 degree per second rotation
−2 degree per second rotation
…
−300 degree per second rotation (negative FSR)
…
Maximum possible negative data value
Rev. PrA | Page 19 of 28
ADXRS450
Preliminary Technical Data
MEMORY MAP AND REGISTERS
MEMORY MAP
The following is a list of the memory registers that are available
to be read from or written to by the customer. See the previous
section SPI Communication Protocol for the proper input sequence to read/write a specific memory register. Each memory
register is comprised of 8-bits of data, however, when a read
request is performed, the data always returns as a 16-bit
message. This is accomplished by appending the data from the
next, sequential register to the memory address that was specified.
Data is transmitted MSB first. For proper acquisition of data from
the memory register, make the read request to the even numbered
register address only. Following the memory map (Table 15) is
the explanation of the significance of each memory register.
Table 15. Memory Register Map
Address
Register Name
MSB
D6
D5
D4
D3
D2
D1
LSB
0x00
RATE1
RTE15
RTE14
RTE13
RTE12
RTE11
RTE10
RTE9
RTE8
0x01
RATE0
RTE7
RTE6
RTE5
RTE4
RTE3
RTE2
RTE1
RTE0
0x02
TEM1
TEM9
TEM8
TEM7
TEM6
TEM5
TEM4
TEM3
TEM2
0x03
TEM0
TEM1
TEM0
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
0x04
LO CST1
LCST15
LCST14
LCST13
LCST12
LCST11
LCST10
LCST9
LCST8
0x05
LO CST0
LCST7
LCST6
LCST5
LCST4
LCST3
LCST2
LCST1
LCST0
0x06
HI CST1
HCST15
HCST14
HCST13
HCST12
HCST11
HCST10
HCST9
HCST8
0x07
HI CST0
HCST7
HCST6
HCST5
HCST4
HCST3
HCST2
HCST1
HCST0
0x08
QUAD1
QAD15
QAD14
QAD13
QAD12
QAD11
QAD10
QAD9
QAD8
0x09
QUAD0
QAD7
QAD6
QAD5
QAD4
QAD3
QAD2
QAD1
QAD0
0x0A
FAULT1
(Unused)
(Unused)
(Unused)
(Unused)
FAIL
AMP
OV
UV
0x0B
FAULT0
PLL
Q
NVM
POR
PWR
CST
CHK
0
0x0C
PID1
PIDB15
PIDB14
PIDB13
PIDB12
PIDB11
PIDB10
PIDB9
PIDB8
0x0D
PID0
PIDB7
PIDB6
PIDB5
PIDB4
PIDB3
PIDB2
PIDB1
PIDB0
0x0E
SN3
SNB31
SNB30
SNB29
SNB28
SNB27
SNB26
SNB25
SNB24
0x0F
SN2
SNB23
SNB22
SNB21
SNB20
SNB19
SNB18
SNB17
SNB16
0x10
SN1
SNB15
SNB14
SNB13
SNB12
SNB11
SNB10
SNB9
SNB8
0x11
SN0
SNB7
SNB6
SNB5
SNB4
SNB3
SNB2
SNB1
SNB0
0x12
DNC1
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
(Unused)
DNCB9
DNCB8
0x13
DNC0
DNCB7
DNCB6
DNCB5
DNCB4
DNCB3
DNCB2
DNCB1
DNCB0
Rev. PrA | Page 20 of 28
Preliminary Technical Data
ADXRS450
MEMORY REGISTER DEFINITIONS
The SPI accessible memory registers are described in this section.
As explained in the previous section, when requesting data
from a memory register, only the first sequential memory
address need be addressed. The data returned by the device
contain 16 bits of memory register information. Bits[15:8]
contain the MSB of the requested information, and Bits[7:0]
contain the LSB.
Rate Registers
The LOCST memory registers contain the value of the temperature
compensated and low-pass filtered continuous self-test delta.
This value is a measure of the difference between the positive
and negative self-test deflections and corresponds to the values
presented in Table 1. The device issues a CST error if the value
of self test exceeds the established self-test limits. The self-test
data is filtered to 2 Hz to prevent false triggering of the CST
fault bit. The data is presented as a 16-bit, twos complement
number, with a scale factor of 80 LSB/°/sec.
0x01 (Rate0)
MSB
D15
D7
Register update rate:
500 Hz
High CST (HICST) Memory Registers
Scale factor:
80 LSB/°/sec
Addresses:
Addresses:
0x00 (Rate1)
The rate registers contain the temperature compensated rate
output of the device filtered to 80 Hz. This data can also be
accessed by issuing a sensor data read request to the device. The
data is presented as a 16-bit, twos complement number.
MSB
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
LSB
D8
D0
Temperature (TEMx) Registers
Addresses:
0x02 (TEM1),
0x03 (TEM0)
Register update rate:
500 Hz
Scale factor:
5 LSB/°C
The TEM register contains a value corresponding to the
temperature of the device. The data is presented as a 10-bit,
twos complement number. 0 LSB corresponds to a temperature
of approximately 45°C.
MSB
D9
D1
D8
D0
D7
D6
D5
D4
Value of TEM1:TEM0
0000 0000 00XX XXXX
0011 0010 00XX XXXX
1100 0111 11XX XXXX
Low CST (LOCST) Memory Registers
Addresses:
D13
D5
0x04 (LOCST1)
0x05 (LOCST0)
Register update rate:
1000 Hz
Scale factor:
80 LSB/°/sec
D12
D4
D11
D3
D10
D2
D9
D1
LSB
D8
D0
0x06 (HICST1),
0x07 (HICST0)
Register update rate:
1000 Hz
Scale factor:
80 LSB/°/sec
The HICST register contains the unfiltered self-test information.
The HICST data can be used to supplement fault diagnosis in
safety critical applications as sudden shifts in the self-test
response can be detected. However, the CST bit of the fault
register is not set when the HICST data is observed to exceed
the self-test limits. Only the LOCST memory registers, which
are designed to filter noise and the effects of sudden temporary
self-test spiking due to external disturbances, control the
assertion of the CST fault bit. The data is presented as a 16-bit,
twos complement number.
MSB
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
LSB
D8
D0
Quad Memory Registers
Addresses:
0x08 (QUAD1)
0x09 (QUAD0)
(Unused)
Table 16.
Temperature
45°C
85°C
0°C
D3
LSB
D2
D14
D6
Register update rate:
250 Hz
Scale factor:
80 LSB/°/sec equivalent
The quad memory registers contain a value corresponding to
the amount of quadrature error present in the device at a given
time. Quadrature can be likened to a measurement of the error
of the motion of the resonator structure, and can be caused by
stresses and aging effects. The quadrature data is filtered to
80 Hz and can be read frequently to detect sudden shifts in the
level of quadrature. The data is presented as a 16-bit, twos
complement number.
MSB
D15
D7
Rev. PrA | Page 21 of 28
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
LSB
D8
D0
ADXRS450
Preliminary Technical Data
Fault Registers
Addresses:
Serial Number (SN) Registers
0x0A (FAULT1)
Addresses:
0x0E (SN3)
0x0B (FAULT0)
0x0F (SN2)
Register update rate:
Not applicable
0x10 (SN1)
Scale factor:
Not applicable
0x11 (SN0)
The fault register contains the state of the error flags in the
device. The FAULT0 register is appended to the end of every
device data transmission (see Table 13); however, this register
can also be accessed independently through its memory
location. The individual fault bits are updated asynchronously,
requiring <5 μs to activate, as soon as the fault condition exists
on-chip. When toggled, each fault bit remains active until the
fault register is read or a sensor data command is received. If
the fault is still active after the bit is read, the fault bit
immediately reasserts itself.
MSB
PLL
(Unused)
Q
NVM
POR
FAIL
PWR
AMP
ST
OV
CHK
LSB
UV
0
Register update rate:
Not applicable
Scale factor:
Not applicable
The serial number registers contain a 32-bit identification number
that uniquely identifies the device. To read the entire serial
number, two memory read requests must be initiated. The first
read request to Register 0x0E returns the upper 16 bits of the
serial number, and the following read request to Register 0x10
returns the lower 16 bits of the serial number.
MSB
D31
D23
D15
D7
D30
D22
D14
D6
D29
D21
D13
D5
D28
D20
D12
D4
D27
D19
D11
D3
D26
D18
D10
D2
D25
D17
D9
D1
LSB
D24
D16
D8
D0
Part ID (PID) Registers
Addresses:
Dynamic Null Correction (DNC) Registers
0x0C (PID1)
Addresses:
0x0D (PID0)
Register update rate:
Not applicable
Scale factor:
Not applicable
0x13 (DNC0)
The part identification registers contain a 16-bit number
identifying the version of the ADXRS450. Combined with the
serial number, this information allows for a higher degree of
device individualization and tracking. The initial product ID is
R01 (0x5201), with subsequent versions of silicon incrementing
this value to R02, R03, and so forth.
MSB
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
0x12 (DNC1)
D10
D2
D9
D1
LSB
D8
D0
Register update rate:
Not applicable
Scale factor:
80 LSB/°/sec
The dynamic null correction register is the only register with
write access available to the user. The user can make small
adjustments to the rateout of the device by asserting these bits.
This 10-bit register allows the user to adjust the static rateout of
the device by up to ±6.4°/sec.
MSB
D7
Rev. PrA | Page 22 of 28
D6
(Unused)
D5
D4
D3
D2
D9
D1
LSB
D8
D0
Preliminary Technical Data
ADXRS450
PACKAGE ORIENTATION AND LAYOUT INFORMATION
ADX
RS45
(PAC
KA G
E FR
0
ONT)
14
8
08952-004
1
7
Figure 28. 14-Lead Ceramic LCC_V Vertical Mount
11.232
0.55
0.55
0.55
0.95
1.55
0.95
1.55
1.27
2.55
9.462
0.572
08952-022
2.55
1.5
Figure 29. Sample SOIC_CAV Solder Pad Layout (Land Pattern), Dimensions
Shown In Millimeters, Not To Scale
1
0.8
0.8
1
1.5
Figure 30. LCC_V Solder Pad Layout, Dimensions Shown In Millimeters,
Not To Scale
Rev. PrA | Page 23 of 28
08952-024
1.691
5.55
ADXRS450
Preliminary Technical Data
0.90
1.50
0.50
3.10
7.70
1.00
1.50
0.80
08952-025
2.70
Figure 31. Sample LCC_V Solder Pad Layout for
Horizontal Mounting, Dimensions Shown In Millimeters, Not To Scale
Rev. PrA | Page 24 of 28
Preliminary Technical Data
ADXRS450
SOLDER PROFILE
SUPPLIER TP ≥ TC
USER TP ≤ TC
TC
TC –5°C
SUPPLIER tP
USER tP
TP
TC –5°C
tP
MAXIMUM RAMP-UP RATE = 3°C/sec
MAXIMUM RAMP-DOWN RATE = 6°C/sec
TL
TEMPERATURE
TSMAX
PREHEAT AREA
tL
TSMIN
tS
08952-026
25
TIME 25°C TO PEAK
TIME
Figure 32. Recommended Soldering Profile
Conditions
Profile Feature
Average Ramp Rate (TL to TP)
Preheat
Minimum Temperature (TSMIN)
Maximum Temperature (TSMAX)
Time (TSMIN to TSMAX) (tS)
TSMAX to TL
Ramp-Up Rate
Time Maintained above Liquidous (TL)
Liquidous Temperature (TL)
Time (tL)
Peak Temperature (TP)
Time Within 5°C of Actual Peak Temperature (tP)
Ramp-Down Rate
Time 25°C to Peak Temperature
Sn63/Pb37
100°C
150°C
60 sec to 120 sec
Pb-Free
3°C/sec maximum
150°C
200°C
60 sec to 120 sec
3°C/sec maximum
183°C
60 sec to 150 sec
240°C + 0°C/−5°C
10 sec to 30 sec
6 minutes maximum
Rev. PrA | Page 25 of 28
217°C
60 sec to 150 sec
260°C + 0°C/−5°C
20 sec to 40 sec
6°C/sec maximum
8 minutes maximum
ADXRS450
Preliminary Technical Data
PACKAGE MARKING CODES
XRS450
BRGZ n
#YYWW
LLLLLLLLL
08952-027
XRS450
BEYZ n
#YYWW
LLLLLLLLL
Figure 33. LCC_V and SOIC_CAV Package Marking Codes
Table 17. Package Code Designations
Marking
XRS
450
B
RG
EY
Z
n
#
YYWW
LLLLLLLLL
Significance
Angular rate sensor
Series number
Temperature Grade (−40°C to +105°C)
Package designator (SOIC_CAV package)
Package designator (LCC_V package)
RoHS compliant
Revision number
Pb-Free designation
Assembly date code
Assembly lot code (up to 9 characters)
Rev. PrA | Page 26 of 28
Preliminary Technical Data
ADXRS450
OUTLINE DIMENSIONS
10.30 BSC
16
9
DETAIL A
10.42
BSC
7.80
BSC
1
8
PIN 1
INDICATOR
0.25 GAGE
PLANE
8°
4°
0°
1.27 BSC
9.59 BSC
3.73
3.58
3.43
0.87
0.77
0.67
1.50
1.35
1.20
0.50
0.45
0.40
0.58
0.48
0.38
0.75
0.70
0.65
DETAIL A
072409-B
0.28
0.18
0.08
COPLANARITY
0.10
Figure 34. 16-Lead Small Outline, Plastic Cavity Package [SOIC_CAV]
(RG-16-1)
Dimensions shown in millimeters
FRONT VIEW
9.20
9.00 SQ
8.80
8.08
8.00
7.92
0.275
REF
0.350
0.305
0.260
7.70
7.55
7.40
BACK VIEW
7.18
7.10
7.02
1
1.175
REF
C 0.30
REF
4.40
4.00
3.60
2
3
4
5
6
0.50
TYP
7
SIDE VIEW
1.00
0.675 NOM
0.500 MIN
1.60
(PINS 2, 6)
(PINS 1, 7)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
13
14
DO NOT SOLDER
CENTER PADS.
0.80
(PINS 10,
11, 12)
0.35
REF
0.80 REF
(ALL PINS)
(METALLIZATION BUMP
BUMP HEIGHT 0.03 NOM)
0.80
(PINS 2, 6,
9, 13)
04-08-2010-A
0.40
12
1.00
1.70
REF
1.40
11
(PINS 9-10,
12-13)
0.30
REF
0.35
REF
0.30
REF
(PINS 1,
7, 8, 14)
10
1.50
(PINS 3-5)
1.70
REF
9
(PINS 2, 6)
0.60
(ALL PINS)
8
R 0.20
REF
(PINS 3-5, 10-12)
BOTTOM VIEW (PADS SIDE)
Figure 35. 14-Terminal Ceramic Leadless Chip Carrier [LCC_V]
(EY-14-1)
Dimensions shown in millimeters
Rev. PrA | Page 27 of 28
ADXRS450
Preliminary Technical Data
ORDERING GUIDE
Model1
ADXRS450BRGZ
ADXRS450BRGZ-RL
ADXRS450BEYZ
ADXRS450BEYZ-RL
EVAL-ADXRS450Z
EVAL-ADXRS450Z-M
EVAL-ADXRS450Z-S
1
Temperature
Range
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package Description
16-Lead SOIC_CAV
16-Lead SOIC_CAV
14-Terminal LCC_V
14-Lead LCC
Evaluation Board
Analog Devices Inertial Sensor Evaluation System, Includes ADXRS450
Satellite
ADXRS450 Satellite, Standalone
Z = RoHS Compliant Part.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR08952-0-4/10(PrA)
Rev. PrA | Page 28 of 28
Package
Option
RG-16-1
RG-16-1
EY-14-1
LCC_14