ACT–E128K32 High Speed 4 Megabit EEPROM Multichip Module CIRCUIT TECHNOLOGY Features www.aeroflex.com ■ 4 Low Power 128K x 8 EEPROM Die in One MCM ■ Packaging – Hermetic Ceramic Package ■ Organized as 128K x 32 ● User 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder, Aeroflex code# "P3" ● 66 Pin, 1.08" x 1.08" x .185" PGA Type, With Shoulder, Aeroflex code# "P7" ● 68 Lead, .88" x .88" x .200" Dual-Cavity Small Outline Gull Wing, Aeroflex code# "F2" (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint) ● Configurable to 256K x 16 or 512K x 8 ■ CMOS and TTL Compatible Inputs and Outputs ■ Access Times of 120,140,150, 200, 250& 300ns ■ +5V ±10% Supply ■ MIL-PRF-38534 Compliant MCMs Available ■ Automatic Page Write Operation ■ Hardware and Software Data Protection ■ Page Write Cycle Time: 10ms Max ■ Internal Decoupling Capacitors for Low Noise ■ Data Retention Ten Years Minimum Operation ■ Commercial, Industrial and Military Temperature Ranges ■ SMD# 5962–94585 Released (P7 & F2) ■ Low Power CMOS ■ Data Polling for End of Write Detection ■ Industry Standard Pinouts General Description Block Diagram – PGA Type Package (P3,P7) & CQFP (F2) WE1 CE1 WE2 CE2 WE3 CE3 WE4 CE4 A0 – A16 OE 128Kx8 128Kx8 128Kx8 128Kx8 8 8 8 8 I/O0-7 I/O8-15 I/O16-23 I/O 24-31 Pin Description I/O0-31 Data I/O A0–16 Address Inputs WE1-4 Write Enables OE Output Enable CE1-4 Chip Enables VCC Power Supply GND Ground The ACT–E128K32 is a high speed, 4 megabit, CMOS EEPROM multichip module (MCM) designed for full temperature range military, space, or high reliability applications. The MCM can be organized as a 256K x 16 bits or 512K x 8 bits device and is input and output CMOS and TTL compatible. Writing is executed when the write enable (WE) and chip enable (CE) inputs are low and output enable (OE) is high. Reading is accomplished when WE is high and CE and OE are both low. Access times grades of 120, 140, 150, 200, 250 & 300ns are standard. The ACT–E128K32 is packaged in a choice of hermetically sealed co-fired ceramic packages, a 66 pin, 1.08" sq PGA or a 68 lead, .88" sq gullwing CQFP. The device operates over the temperature range of -55°C to +125°C and military environment. eroflex Circuit Technology - Advanced Multichip Modules © SCD1662 REV B 9/5/01 Absolute Maximum Ratings Parameter Symbol Range Units TC -55 to +125 °C TSTG -65 to +150 °C VG -0.6 to +6.25 V All Output Voltages with respect to Ground - -0.6 to VCC+0.6 V Voltage on OE and A9 with respect to Ground - -0.6 to +13.5 V Operating Temperature Storage Temperature Range All Input Voltages with respect to Ground NOTICE: Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Symbol Minimum Maximum Units Power Supply Voltage +4.5 +5.5 V VIH Input High Voltage +2.0 VCC + 0.3 V VIL Input Low Voltage -0.5 +0.8 V TC Case Operating Temperature (Military) -55 +125 °C VCC Parameter A Capacitance (VIN = 0V, f = 1MHz, TC = 25°C) Symbol CAD COE CWE(1-4) Parameter Maximum Units A0 – A16 Capacitance 50 pF Output Enable Capacitance 50 pF Write Enable Capacitance 20 pF CCE(1-4) Chip Enable Capacitance 20 pF CI/O I/O0 – I/O31 Capacitance 20 pF DC Characteristics (Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C, unless otherwise specified) Parameter Sym ILI Input Leakage Current Conditions Minimum Maximum Units 10 µA VCC = 5.5V, VIN = GND to VCC Output Leakage Current ILOX32 CE = OE = VIH, VOUT = GND to VCC 10 µA Operating Supply Current x 32 Mode ICC X32 CE = VIL, OE = VIH, f = 5Mhz 250 mA 5 mA 0.45 V Operating Supply Current ISB CE = VIH, OE = VIH, f = 5Mhz Output Low Voltage VOL IOL = +2.1mA, VCC = 4.5V Output High Voltage VOH IOH = –400µA, VCC = 4.5V 2.4 V Truth Table CE OE WE Mode Data I/O H X X Standby High Z L L H Read Data Out L H L Write Data In X H X Out Disable High Z X X H Write - X Inhibit - X Aeroflex Circuit Technology L 2 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700 AC Write Characteristics (VCC = 5V, VSS = 0V, TC = -55°C to +125°C) Parameter Symbol Min tWC Write Cycle Time Max Units 10 ms Address Set-up Time tAS 10 ns Write Pulse Width (WE or CE) tWP 150 ns Chip Enable Set-up Time tCE 0 ns Address Hold Time tAH 100 ns Data Hold Time tDH 10 ns Chip Enable Hold Time tCEH 0 ns Data Set-up Time tDS 100 ns Output Enable Set-up Time tOES 10 ns Output Enable Hold Time tOEH 10 ns A AC Read Characteristics (VCC = 5V, VSS = 0V, TC = -55°C to +125°C) Read Cycle Parameter Symbol –120 –140 –150 –200 –250 Min Max Min Max Min Max Min Max Min 120 140 150 200 250 –300 Max Min Max 300 Units ns Read Cycle Time tRC Address Access Time tACC 120 140 150 200 250 300 ns Chip Enable Access Time tACE 120 140 150 200 250 300 ns Output Hold From Address Change, OE or CE tOH 0 Output Enable to Output Valid tOE 0 Chip Enable or OE to High Z Output tDF 0 55 0 0 55 70 70 0 0 55 0 70 0 55 0 70 0 85 0 70 ns 85 ns 70 ns Page Write Characteristics (VCC = 5V, VSS = 0V, TC = -55°C to +125°C) Parameter Symbol Minimum Maximum Units 10 ms Write Cycle Time tWC Address Set-up Time tAS 10 ns Address Hold Time , See Note 1 tAH 100 ns Data Set-up Time tDS 100 ns Data Hold Time tDH 10 ns Write Pulse Width tWP 150 ns Byte Load Cycle Time tBLC Write Pulse Width High tWPH 150 50 µs ns Note 1 – Page Address must remain valid for duration of write cycle. Aeroflex Circuit Technology 3 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700 Device Operation consists of setting the WE line low. The write cycle begins when the last of either CE or WE goes low. The WE line transition from high to low also initiates an internal delay timer to permit page mode operation. Each subsequent WE transition from high to low that occurs before the completion of the tBLC time out will restart the timer from zero. The operation of the timer is the same as a retriggable one-shot. The ACT-E128K32 is a high-performance Electrically Erasable and Programmable Read Only Memory. It is composed of four 1 megabit memory chips and is organized as 131,072 by 32 bits. The device offers access times of 120 to 300ns with power dissipation of 1.375W. When the device is deselected, the CMOS standby current is less than 5 mA. The ACT-E128K32 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Aeroflex’s ACT-E128K32 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. READ The ACT-E128K32 stores data at the memory location determined by the address pins. When CE and OE are low and WE is high, this data is present on the outputs. When CE and OE are high, the outputs are in a high impedance state. This two line control prevents bus contention. DATA POLLING The ACT-E128K32 offers a data polling feature which allows a faster method of writing to the device. Figure 5 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on I/O7 (For each Chip). Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle. WRITE PAGE WRITE OPERATION A write cycle is initiated when OE is high and a low pulse is on WE or CE with CE or WE low. The address is latched on the falling edge of CE or WE whichever occurs last. The data is latched by the rising edge of CE or WE, whichever occurs first. A byte write operation will automatically continue to completion. The ACT-E128K32 has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within tBLC or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. WRITE CYCLE TIMING Figures 2 and 3 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip enable. Chip enable is accomplished by placing the CE line low. Write enable Aeroflex Circuit Technology 4 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700 A byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. Each 128K byte block of the EEPROM has independent write protection. One or more blocks may be enabled and the rest disabled in any combination. The software write protection guards against inadvertent writes during power transitions, or unauthorized modification using a PROM programmer. The usual procedure is to increment the least significant address lines from A0 through A6 at each write cycle. In this manner a page of up to 128 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. After the tBLC time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed. HARDWARE DATA PROTECTION These features protect against inadvertent writes to the ACT-E128K32. These are included to improve reliability during normal operation: A) Vcc Sense While below 3.8V typical write cycles are inhibited. B) Write inhibiting Holding OE low and either CE or WE high inhibits write cycles. C) Noise filter Pulses of <10ns (TYP) on WE or CE will not initiate a write cycle. SOFTWARE DATA PROTECTION A software write protection feature may be enabled or disabled by the user. When shipped by Aeroflex Microelectronics, the ACT-E128K32 has the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. The write protection feature can be disabled by a six Aeroflex Circuit Technology 5 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700 A Data Polling Characteristics (VCC = 5V, VSS = 0V, TC = -55°C to +125°C) Parameter Symbol Min Data Hold Time tDH 10 ns OE Hold Time tOEH 10 ns OE to Output Valid tOE Write Recovery Time tWR Max Units 55 ns 0 ns Guaranteed. But not tested. Figure 1 AC Test Circuit Current Source A IOL Parameter Typical Units Input Pulse Level 0 – 3.0 V Input Rise and Fall VZ ~ 1.5 V (Bipolar Supply) To Device Under Test CL = 50 pF 5 ns Input and Output Timing Reference Level 1.5 V Output Lead Capacitance 50 pF IOH Current Source Notes: 1) VZ is programmable from -2V to +7V. 2) I OL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance. Figure 2 Write Waveforms – WE Controlled tWC OE tOEH tOES ADDRESS tAS tCEH tAH CE tCE WE tWPH t WP tDS t DH DATA IN Aeroflex Circuit Technology 6 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700 Figure 3 Write Waveforms – CE Controlled tWC OE tOEH tOES ADDRESS tAS tCEH tAH WE tCE CE tWPH t WP A tDS tDH DATA IN Figure 4 Read Waveforms tRC ADDRESS Address Valid CE tACE tOE OE tDF tACC OUTPUT High Z tOH Output Valid Notes: 1. OE may be delayed up to tACS – tOE after the falling edge of CE without impact on tOE or by tACC – tOE after an address change without impact on tACC. Aeroflex Circuit Technology 7 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700 Figure 5 Data Polling Waveform WE1-4 CE1-4 tOEH OE tDH tOE I/O7 ADDRESS tWR High Z AN A AN AN AN AN Figure 6 Page Mode Write Waveforms OE CEX tWP WEX tBLC tAS tAH ADDRESS t WPH tDH Valid ADD tWC tDS DATA Valid DATA Byte 0 Byte 1 Byte 2 Byte 3 Byte 127 Notes: 1. A7 through A16 must specify the sector address during each high to low transition of WE (or CE) after the software codes have been entered. 2. OE must be high when WE and CE are both low. Aeroflex Circuit Technology 8 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700 Figure 7 Software Data Protection Enable Algorithm Figure 8 Software Data Protection Disable Algorithm (1) Load Data AA To Address 5555 Load Data AA To Address 5555 Load Data 55 To Address 2AAA Load Data 55 To Address 2AAA Load Data A0 To Address 5555 Writes Enabled (1) Load Data 80 To Address 5555 (2) A Load Data XX To Any Address (4) Load Data AA To Address 5555 (4) Load Last Byte To Last Address Load Data 55 To Address 2AAA Enter Data Protect State Load Data 20 To Address 5555 Exit Data Protect State (3) Load Data XX To Any Address (4) Load Last Byte To Last Address NOTES: 1. Data Format: I/O0 - I/O7 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end ot write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. Aeroflex Circuit Technology 9 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700 Pin Numbers & Functions 66 Pins — PGA Type Package Pin # Function Pin # Function Pin # Function Pin # Function 1 I/O8 18 A12 35 I/O25 52 WE3 2 I/O9 19 Vcc 36 I/O26 53 CE3 3 I/O10 20 CE1 37 A6 54 GND 4 A13 21 NC 38 A7 55 I/O19 5 A14 22 I/O3 39 NC 56 I/O31 6 A15 23 I/O15 40 A8 57 I/O30 7 A16 24 I/O14 41 A9 58 I/O29 8 NC 25 I/O13 42 I/O16 59 I/O28 9 I/O0 26 I/O12 43 I/O17 60 A0 10 I/O1 27 OE 44 I/O18 61 A1 11 I/O2 28 NC 45 VCC 62 A2 12 WE2 29 WE1 46 CE4 63 I/O23 13 CE2 30 I/O7 47 WE4 64 I/O22 14 GND 31 I/O6 48 I/O27 65 I/O21 15 I/O11 32 I/O5 49 A3 66 I/O20 16 A10 33 I/O4 50 A4 17 A11 34 I/O24 51 A5 Note: Pins 8, 21, 28 & 39 can be connected to ground by specifing Option "C". "P3" — 1.08" SQ PGA Type (without shoulder) Package "P7" — 1.08" SQ PGA Type (with shoulder) Package Bottom View (P7 & P3) Side View (P7) Side View (P3) 1.085 SQ MAX 1.000 .185 MAX .600 .025 .035 Pin 56 .050 1.030 1.040 .100 Pin 1 1.030 1.040 .100 .020 .016 1.000 .020 .016 Pin 66 .180 TYP All dimensions in inches Aeroflex Circuit Technology Pin 11 .180 TYP .100 .160 MAX 10 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700 A Pin Numbers & Functions 68 Pins — Dual-Cavity CQFP Pin # Function Pin # Function Pin # Function Pin # Function 1 GND 18 GND 35 OE 52 GND 2 CE3 19 I/O8 36 CE2 53 I/O23 3 A5 20 I/O9 37 NC 54 I/O22 4 A4 21 I/O10 38 WE2 55 I/O21 5 A3 22 I/O11 39 WE3 56 I/O20 6 A2 23 I/O12 40 WE4 57 I/O19 7 A1 24 I/O13 41 NC 58 I/O18 8 A0 25 I/O14 42 NC 59 I/O17 9 NC 26 I/O15 43 NC 60 I/O16 10 I/O0 27 Vcc 44 I/O31 61 VCC 11 I/O1 28 A11 45 I/O30 62 A10 12 I/O2 29 A12 46 I/O29 63 A9 13 I/O3 30 A13 47 I/O28 64 A8 14 I/O4 31 A14 48 I/O27 65 A7 15 I/O5 32 A15 49 I/O26 66 A6 16 I/O6 33 A16 50 I/O25 67 WE1 17 I/O7 34 CE1 51 I/O24 68 CE4 Package Outline — Dual-Cavity CQFP "F2" Top View Pin 9 .990 SQ ±.010 .880 SQ ±.010 Pin 10 Pin 61 *.200 MAX .010 REF Pin 60 .015 ±.010 .946 ±.010 0.010 R 0°- 7° .050 TYP .010 ±.005 .040 Detail “A” Pin 26 Pin 27 Pin 44 .800 REF Pin 43 See Detail “A” *.180 MAX available, call factory for details All dimensions in inches Aeroflex Circuit Technology 11 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700 A CIRCUIT TECHNOLOGY Ordering Information Model Number DESC Drawing Number Speed Package ACT-E128K32N-120P7Q 5962-9458506H4X 120ns PGA Type ACT-E128K32C-120P7Q 5962-9458506H5X 120ns PGA Type ACT-E128K32N-140P7Q 5962-9458505H4X 140ns PGA Type ACT-E128K32C-140P7Q 5962-9458505H5X 140ns PGA Type ACT-E128K32N-150P7Q 5962-9458504H4X 150ns PGA Type ACT-E128K32C-150P7Q 5962-9458504H5X 150ns PGA Type ACT-E128K32N-200P7Q 5962-9458503H4X 200ns PGA Type ACT-E128K32C-200P7Q 5962-9458503H5X 200ns PGA Type ACT-E128K32N-250P7Q 5962-9458502H4X 250ns PGA Type ACT-E128K32C-250P7Q 5962-9458502H5X 250ns PGA Type ACT-E128K32N-300P7Q 5962-9458501H4X 300ns PGA Type ACT-E128K32C-300P7Q 5962-9458501H5X 300ns PGA Type ACT-E128K32N-120F2Q 5962-9458506HMX 120ns CQFP ACT-E128K32N-140F2Q 5962-9458505HMX 140ns CQFP ACT-E128K32N-150F2Q 5962-9458504HMX 150ns CQFP ACT-E128K32N-200F2Q 5962-9458503HMX 200ns CQFP ACT-E128K32N-250F2Q 5962-9458502HMX 250ns CQFP ACT-E128K32N-300F2Q 5962-9458501HMX 300ns CQFP Part Number Breakdown ACT– E 128K 32 N– 200 P7 M Aeroflex Circuit Technology Memory Type Screening E = EEPROM C = Commercial Temp, 0°C to +70°C I = Industrial Temp, -40°C to +85°C T = Military Temp, -55°C to +125°C M = Military Temp, -55°C to +125°C, Screening * Q = MIL-PRF-38534 Compliant / SMD Memory Depth Memory Width, Bits Options Package Type & Size Surface Mount Packages Thru-Hole Packages F2 = .88"SQ 68 Lead Dual-Cavity P3 = 1.085"SQ PGA 66 Pins without shoulder CQFP P7 = 1.085"SQ PGA 66 Pins with shoulder N = None C = Connect to GND – Pins 8,21,28,39 (P3 & P7 Pkg only) Memory Speed, ns * Screened to the individual test methods of MIL-STD-883 Specifications subject to change without notice. Aeroflex Circuit Technology 35 South Service Road Plainview New York 11830 Aeroflex Circuit Technology Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800) 843-1553 12 SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700 A