Anpec APL531712BI-TRG Selectable adjustable/fixed low dropout 300ma linear regulator Datasheet

APL5317
Selectable Adjustable/Fixed Low Dropout 300mA Linear Regulator
Features
General Description
•
•
The APL5317 is a low dropout linear regulator which only
needs a single input voltage supply from 2.8 to 6V, and it
Wide Operating Voltage: 2.8~6V
Low Dropout Voltage:
can deliver current up to 300mA to a set output voltage. It
can work with low ESR ceramic capacitors that make it
230mV(Typical) @ 300mA
•
•
ideal for using in the battery-powered applications, such
as notebook computers and cellular phones. Its typical
Guaranteed 300mA Output Current
Two Modes for Setting Output Voltage
dropout voltage is only 230mV at 300mA loading. The
APL5317 provides two output voltage operation modes,
- Fixed Output Voltage: 1~5V
the fixed output voltage mode and the adjustable output
voltage, controlled by the SET pin for setting the output
- Adjustable Output Voltage: 0.8~5.5V
•
•
•
•
•
•
Current-Limit Protection with Foldback Current
voltage. The fixed output voltage mode sets the output to
a preset voltage (only 1.2V available now) in the chip by
Internal Soft-Start
connecting SET pin to the ground, and the adjustable
output voltage mode needs two resistors as a voltage
Over-Temperature Protection
Stable with Low ESR Ceramic Capacitor
divider connected to SET pin to define the output. The
current-limit with current foldback and thermal shutdown
SOT-23-5 Package
functions protect the device against current over-loads
and over temperature. The APL5317 is available in a SOT-
Lead Free and Green Devices Available
(RoHS Compliant)
23-5 package.
Applications
•
•
•
Pin Configuration
Cellular Phones
VIN 1
Portable and Battery-Powered Equipment
5 VOUT
GND 2
SHDN 3
Notebook and Personal Computers
4 SET
SOT-23-5
Simplified Application Circuit
1. Fixed Output Voltage Mode
2. Adjustable Output Voltage Mode
APL5317
APL5317
VIN
1
CIN
VIN
VOUT
3 SHDN
SET
5
VIN
VOUT
1
4
CIN
COUT
VIN
VOUT
3 SHDN
SET
GND
GND
2
2
5
VOUT
4
COUT
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
1
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APL5317
Ordering and Marking Information
Package Code
B : SOT-23-5
Operating Junction Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Voltage Code (Note 1)
12 : 1.2V
Assembly Material
G: Halogen and Lead Free Device
APL5317
Assembly Material
Handling Code
Temperature Range
Package Code
Voltage Code
APL5317 B:
375X
X - Date code
APL5317-12 B:
375X
X - Date code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Note 1: For other voltage versions, please contact ANPEC for details.
Note 2: Because APL5317 and APL5317-12 are identical, the marking of APL5317 is same as APL5317-12.
Absolute Maximum Ratings
Symbol
(Note 3)
Parameter
Rating
Unit
VIN
VIN Supply Voltage (VIN to GND)
-0.3 ~ 6.5
V
VSHDN
SHDN Input Voltage (SHDN to GND)
-0.3 ~ 6.5
V
PD
Power Dissipation
TJ
Junction Temperature
TSTG
TSDR
Internally Limited
Storage Temperature
Maximum Lead Soldering Temperature, 10 Seconds
W
-40 ~ 150
o
-65 ~ 150
o
260
o
C
C
C
Note 3: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
Parameter
θJA
Thermal Resistance-Junction to Ambient
θJC
Thermal Resistance-Junction to Case
Typical Value
Unit
(Note 4)
SOT-23-5
SOT-23-5
240
o
130
o
C/W
C/W
Note 4 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Symbol
Range
Unit
VIN Supply Voltage
2.8 ~ 6
V
VOUT
Output Voltage
0.8 ~ 5.5
IOUT
VOUT Output Current
VIN
Parameter
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
0 ~ 300
2
V
mA
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APL5317
Recommended Operating Conditions (Cont.)
Symbol
Parameter
Range
Unit
0.22 ~ 100
µF
Output Capacitor
1.5 ~ 33
µF
Junction Temperature
-40 ~ 125
o
CIN
Input Capacitor
COUT
TJ
C
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN = VOUT+1V (min VIN=2.8V), IOUT=0~300mA, CIN = 1µF, COUT = 2.2µF, TA
= -40 to 85oC. Typical values are at TA = 25oC.
Symbol
Parameter
APL5317
Test Conditions
Unit
Min.
Typ.
Max.
VIN
Input Voltage
2.8
-
6
V
VOUT
Output Voltage Range
0.8
-
5.5
V
IQ
VREF
VDROP
PSRR
Quiescent Current
IOUT =10mA ~300mA
-
135
160
µA
Reference Voltage
Measured on SET,
VIN=VOUT+1V(min VIN=2.8V),
IOUT=10mA
-
0.8
-
V
Output Voltage Accuracy
TA=25°
C,
VIN=VOUT+1V(min VIN=2.8V),
IOUT=10mA
-1
-
+1
%
Output Voltage Accuracy
TA=-40°
C ~ 85°
C,
VIN=VOUT+1V(min VIN=2.8V),
IOUT=0~300mA
-2
-
+2
%
VOUT = 2.5V, IOUT = 300mA
-
230
360
VOUT = 3.3V, IOUT = 300mA
-
170
300
f = 10kHz, IOUT = 300mA
-
45
-
dB
f = 80Hz to 100kHz, IOUT = 300mA
-
160
-
µVRMS
450
600
-
mA
mA
Dropout Voltage
Power Supply Ripple Rejection
Ratio
Noise
ILIMIT
Current-Limit
ISHORT
Foldback Current
-
80
-
SHDN Input Voltage High
1.6
-
-
SHDN Input Voltage Low
-
-
0.4
-
0.1
1
µA
-
3
-
MΩ
-
60
-
Ω
Over Temperature Threshold
-
160
-
°
C
Over Temperature Hysteresis
-
40
-
°
C
SET Input Threshold for
Fixed/Adjustable Output Voltage
Mode
-
100
-
mV
-100
-
100
nA
-
60
-
µs
Shutdown VIN Supply Current
VOUT = 0V
SHDN = Low, VIN = 6V
SHDN Pull Low Resistance
VOUT Discharge MOSFET RDS(ON)
SET Input Bias Current
TSS
mV
SHDN = Low
VSET=0.8V
Soft-Start Interval
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
3
V
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APL5317
Typical Operating Characteristics
Quiescent Current vs. Supply Voltage
Quiescent Current vs. Junction Temperature
160
138
IOUT= 0mV
136
Quiescent Current, IQ (µA)
Quiescent Current, IQ (µA)
140
120
100
80
60
40
134
132
130
128
20
126
0
0
1
2
3
4
5
6
-50
7
-25
Supply Voltage, VIN (V)
Quiescent Current vs. Output Current
50
75
100
125
PSRR vs. Frequency
0
-10
140
-20
PSRR (dB)
160
VIN=5.5V
120
100
VIN=3.3V, VOUT=1.2V
CIN=1µF, COUT=2.2µF
IOUT=300mA
-30
-40
VIN=4.5V
-50
80
-60
60
0
50
100
150
200
250
1000
300
10000
100000
1000000
Frequency (Hz)
Output Current, I OUT (mA)
Dropout Voltage vs. Output Current
Dropout Voltage vs. Output Current
300
250
250
TJ=25°
C
TJ=75°
C
TJ=125°
C
200
150
100
TJ=25°
C
VOUT=3.3V
Dropout Voltage, VDROP (mV)
VOUT=2.5V
Dropout Voltage, VDROP (mV)
25
Junction Temperature, T J (°
C)
180
Quiescent Current, IQ (µA)
0
TJ=0°
C
TJ=-50°
C
50
TJ=75°
C
200
TJ=125°
C
150
100
TJ=0°
C
50
TJ=-50°
C
0
0
0
100
200
Output Current, I OUT (mA)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
0
300
4
100
200
Output Current, IOUT (mA)
300
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APL5317
Typical Operating Characteristics (Cont.)
Loop Gain vs. Frequency
Phase vs. Frequency
160
50
VIN=3.3V, VOUT=1.2V, CIN=1µF, COUT=2.2µF
40
30
140
IOUT=100mA
IOUT=300mA
Phase (degree)
120
20
Loop Gain (dB)
VIN=3.3V, VOUT=1.2V, CIN=1µF, C OUT=2.2µF
10
0
100
80
60
-10
40
IOUT=300mA
-20
IOUT=100mA
20
-30
0
-40
1000
10000
100000
1000
1000000
Frequency (Hz)
10000
100000
1000000
Frequency (Hz)
Current Limit vs. Junction Temperature
650
Current Limit, ILIMIT (mA)
VIN=5V
600
550
500
450
-50
-25
0
25
50
75
Junction Temperature, TJ (°
C)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
100
125
5
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APL5317
Operating Waveforms
Load Transient
Line Transient
VIN=3.3V, CIN=1µF, COUT=2.2µF, TR=1µs
CIN=1µF, COUT=2.2µF, TR=10µs, IOUT=10mA
V OUT
V IN
V OUT
IOUT
CH1 : VOUT, 50mV/div, AC
CH2 : IOUT, 100mA/div, DC
Time : 100µs/div
CH1 : VIN, 1V/div, DC
CH2 : VOUT, 20mV/div, AC
Time : 100µs/div
Enable
Shutdown
V OUT
V OUT
V SHDN
V SHDN
I OUT
I OUT
CH1 : VOUT, 500mV/div
CH2 : VSHDN, 5V/div
CH3 : IOUT, 200mA/div
Time : 50µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
CH1 : VOUT, 500mV/Div
CH2 : VSHDN, 5V/Div
CH3 : IOUT, 200mA/Div DC
Time : 10µs/Div
6
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APL5317
Operating Waveforms (Cont.)
Power on
Power off
V IN
V IN
V OUT
V OUT
I OUT
I OUT
CH1 : VIN, 2V/div
CH2 : VOUT, 500mV/div
CH3 : IOUT, 100mA/div
Time : 200µs/Div
CH1 : VIN, 2V/div
CH2 : VOUT,, 500mV/div,
CH3 : IOUT, 100mA/div
Time : 50ms/Div
Pin Description
PIN
FUNCTION
NO.
NAME
1
VIN
Voltage supply input pin
2
GND
Ground pin
3
SHDN
4
SET
5
VOUT
Shutdown control pin, logic high: enable; logic low: shutdown
Connect this pin to the ground for fixed output voltage operation. Connect this pin to an external resistor
divider for adjustable output voltage mode operation.
Regulator output pin
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
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APL5317
Block Diagram
SHDN
VIN
Shutdown
Logic
Foldback
Current
Limit
Thermal
Shutdown
+
VOUT
Low
3MΩ
SET
High
+
0.8V
GND
100mV
Typical Application Circuits
1. Fixed Output Voltage Mode
APL5317
VIN
1
CIN
1µF
3
VIN
VOUT
SHDN
SET
5
VOUT
4
GND
COUT
2.2µF
2
Enable
Shutdown
2.2µF/GRM155R60J225M Murata
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
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APL5317
Typical Application Circuits (Cont.)
2. Adjustable Output Voltage Mode
APL5317
VIN
1
CIN
1µF
3
VOUT
VIN
SET
SHDN
VOUT
5
4
R1
GND
COUT
2.2µF
2
Enable
R2
Shutdown
R1 

VOUT = 0.8 ⋅  1 +

 R2 
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
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APL5317
Function Description
Internal Soft-Start
Under-Voltage Lock Out (UVLO)
An internal soft-start function controls rising rate of the
output voltage to limit the surge current at start-up. The
The APL5317 monitors the input voltage to prevent wrong
logic control. The UVLO function initiates a soft-start pro-
typical soft-start interval is about 80µs.
cess after input voltage exceeds its rising UVLO threshold during power on. The UVLO function also shuts off
Output Voltage Regulation
the output when the input voltage falls below its falling
threshold. Typical UVLO hysteresis voltage is 0.8V.
The APL5317 can work in either fixed or adjustable mode
by connecting the SET to GND or a resistor-divider which
Shutdown Control
receives the feedback voltage of the regulator. The output
voltage set by the resistor-divider is determined by:
The APL5317 has an active-low shutdown function. Force
R1 

VOUT = 0.8 ⋅  1 +

R2 

SHDN high (>1.6V) enables the VOUT; force SHDN low
(<0.4V) disables the VOUT. SHDN is internally pulled low
by a resistor (3MΩ typical). If SHDN is not used, it will
connect to VIN for normal operation.
Where R1 is connected from VOUT to SET with Kelvin
sensing and R2 is connected from SET to GND. The recommended value of R2 is in the range of 100 to 100kΩ.
An error amplifier works with a temperature compensated
0.8V reference and an output PMOS regulates the output
to the presetting voltage. The error amplifier is designed
with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the
reference with the feedback voltage and amplifies the difference to drive the output PMOS which provides load
current from VIN to VOUT.
Thermal Shutdown
A thermal shutdown circuit limits the junction temperature of APL5317. When the junction temperature exceeds
+160οC, a thermal sensor turns off the output PMOS, allowing the device to cool down. The regulator regulates
the output again through initiation of a new soft-start cycle
after the junction temperature is cooled by 40οC.The thermal shutdown is designed with a 40οC hysteresis to lower
the average junction temperature during continuous thermal overload conditions, extending lifetime of the device.
For normal operation, device power dissipation should
be externally limited, so that junction temperature will not
exceed 125οC.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
10
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APL5317
Application Information
Input Capacitor
Operation Region and Power Dissipation
The APL5317 requires proper input capacitors to supply
surge current during stepping load transients to prevent
The APL5317 maximum power dissipation depends on
the thermal resistance and temperature difference be-
the input rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to
tween the die junction and ambient air. The power dissipation PD across the device is:
the VIN limit the slew rate of the surge current, place the
Input capacitors near VIN as close as possible. Input ca-
PD = (TJ - TA) / θJA
where (TJ-TA) is the temperature difference between the
pacitors should be larger than 1µF and a minimum ceramic capacitor of 1µF is necessary.
junction and ambient air. θJA is the thermal resistance
between junction and ambient air. Assuming the TA=25oC
and maximum TJ=160oC (typical thermal limit threshold),
the maximum power dissipation is calculated as:
Output Capacitor
The APL5317 needs a proper output capacitor to maintain circuit stability and improve transient response over
PD(max)=(160-25)/240
= 0.56(W)
temperature and current. In order to insure the circuit
stability, the proper output capacitor value should be larger
For normal operation, do not exceed the maximum junction temperature rating of TJ = 125 oC. The calculated
than 2.2µF. With X5R and X7R dielectrics, 2.2µF is sufficient at all operating temperatures. Large output capaci-
power dissipation should less than:
tor value can reduce noise and improve load-transient
response and PSRR, however, it also affects power on
PD =(125-25)/240
= 0.41(W)
issue. Equation (1) shows the relationship between the
maximum COUT value and VOUT.
COUT(max) = 31 -
6
VOUT
The GND provides an electrical connection to ground and
channels heat away. Connect the GND to the ground by
using a large pad or a ground plane.
...............................(1)
Layout Consideration
Where the unit of COUT is µF and VOUT is V, Figure 1 shows
the curve of maximum output capacitor over the output
Figure 2 illustrates the layout. Below is a checklist for
your layout:
voltage. The output voltage range is from 0.8 to 5.5V and
the output capacitor value should be under the line. Out-
1. Please place the input capacitors close to the VIN.
2. Ceramic capacitors for load must be placed near
put capacitors must be placed at the load and the ground
pin as close as possible and the impedance of the layout
the load as close as possible.
3. To place APL5317 and output capacitors near the
Output Capacitor (µF)
must be minimized.
load is good for performance.
4. Large current paths, the bold lines in figure 2,
31
must have wide tracks.
5. Divider resistor R1 and R2 must be placed near
28
the SET as close as possible.
25
22
0
1
2
3
4
5
6
Output voltage (V)
Figure 1
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Rev. A.4 - Mar., 2009
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APL5317
Application Information (Cont.)
PCB Layout Consideration (Cont.)
CIN
APL5317
VIN
VOUT
SET
VIN
1
VOUT
5
4
R1
COUT
GND
2
LOAD
R2
Figure 2
Recommended Minimum Footprint
SOT-23-5
0.05
0.1
0.076
0.038
0.02
Unit : Inch
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
12
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APL5317
Package Information
SOT-23-5
D
e
E
E1
SEE
VIEW A
b
c
0.25
A
L
0
GAUGE PLANE
SEATING PLANE
A1
A2
e1
VIEW A
S
Y
M
B
O
L
SOT-23-5
MIN.
MIN.
MAX.
A
A1
INCHES
MILLIMETERS
MAX.
1.45
0.00
0.057
0.15
0.000
0.006
0.051
A2
0.90
1.30
0.035
b
0.30
0.50
0.012
0.020
c
0.08
0.22
0.003
0.009
0.122
D
2.70
3.10
0.016
E
2.60
3.00
0.102
0.118
1.80
0.055
0.071
E1
1.40
e
0.95 BSC
e1
0.037 BSC
1.90 BSC
0.075 BSC
L
0.30
0.60
0
0°
8°
0.012
0°
0.024
8°
Note : 1. Follow JEDEC TO-178 AA.
2. Dimension D and E1 do not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil
per side.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
13
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APL5317
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SOT-23-5
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.0 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
(mm)
Devices Per Unit
Package Type
SOT-23-5
Unit
Tape & Reel
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
Quantity
3000
14
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APL5317
Taping Direction Information
SOT-23-5
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
15
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APL5317
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
ESD
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Mar., 2009
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD 78
16
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV, VMM≧200V
10ms, 1tr≧100mA
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APL5317
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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Rev. A.4 - Mar., 2009
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