Burr-Brown ADS1206IDGKT Low-power, synchronous voltage-to-frequency converter Datasheet

 SBAS311 − MARCH 2004
− 1MHz for ADS1206
− 4MHz for ADS1207
Selectable High-Impedance Buffered Input
2% Internal, 2.5V Reference Voltage
High-Current Output Driver
Power Supply 3.3V or 5V
Low Power : 3mW (typ)
DESCRIPTION
D
D
D
D
D
D Alternate Source for AD7740
D −40°C to +85°C Operating Temperature Range
APPLICATIONS
D Galvanic Isolation Measurement
D High Voltage Measurement
D Low-Cost Analog-to-Digital Conversion
D Motor Control
D Industrial Process Control
D Instrumentation
D Smart Transmitters
D Portable Instruments
The ADS1206 and ADS1207 are a low-cost,
high-performance, synchronous voltage-to-frequency
converters (VFC). Both devices can operate from a single
3.0V to 3.6V or 4.5V to 5.5V power supply, consuming only
1mA. The output signal is synchronous with the input
clock, CLKIN. The clock input is TTL- and CMOScompatible and the onboard clock generator can also
accept an external crystal or resonator. The maximum
input clock frequency for the ADS1206 is 1MHz and for the
ADS1207 is 4MHz. The clock divider on the ADS1207
scales the input frequency to 2MHZ, which permits the
core to operate at the higher rate. The high-impedance
input is ideal for direct connection to high-impedance
transducers or high-voltage resistive dividers. Counting
output pulses over a 4ms period results in an effective
12-bit resolution for the ADS1206 using a 1MHz input
clock. For the ADS1207 using a 4MHz input clock, the
same result occurs over a 2ms period. Both devices are
designed for use in medium-resolution measurements.
They are available in an 8-lead VSSOP package.
REFIN/OUT
1kΩ
VIN
x1
Modulator
Reference
Voltage
2.5V
Buffer
FOUT
−2
ADS1207
Only
BUF
CLKOUT
CLKIN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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, * -,+ . )) - - , )*) ) -)
. $/ ' + ) -) ) ,- ) ) .
Copyright  2004, Texas Instruments Incorporated
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PRODUCT PREVIEW
FEATURES
D Syncronous Operation
D Frequency Set By External Clock
D Maximum Input Frequency:
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SBAS311 − MARCH 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT
MAXIMUM
INTEGRAL
LINEARITY
ERROR
(%FS)
MAXIMUM
GAIN
ERROR
(%)
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
ADS1206
±0.012
±0.7
VSSOP-8
DGK
−40°C to +85°C
ADS1207
±0.012
±0.7
VSSOP-8
DGK
−40°C to +85°C
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
TBD
ADS1206IDGKT
Tape and Reel, 250
TBD
ADS1206IDGKR
Tape and Reel, 2000
TBD
ADS1207IDGKT
Tape and Reel, 250
TBD
ADS1207IDGKR
Tape and Reel, 2000
(1) For the most current package and ordering information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
PRODUCT PREVIEW
over operating free-air temperature range unless otherwise noted(1)
ADS1204
UNIT
−0.3 to 7
V
Analog Input Voltage with Respect to GND
GND − 0.3 to VDD + 0.3
V
Reference Input Voltage with Respect to GND
GND − 0.3 to VDD + 0.3
V
Digital Input Voltage with Respect to GND
GND − 0.3 to VDD + 0.3
V
−20 to 20
mA
Supply Voltage, GND to VDD
Input Current to Any Pin Except Supply
Power Dissipation
See Dissipation Rating Table
Operating Virtual Junction Temperature Range, TJ
−40 to +150
°C
Operating Free-Air Temperature Range, TA
−40 to +85
°C
Storage Temperature Range, TSTG
−65 to +150
°C
Lead Temperature (1.6mm or 1/16-inch from case for 10s)
+260
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
3.0
4.5
TBD
0
0.1
TBD
TBD
−40
Low-Voltage Levels
5V Logic Levels
Supply Voltage, GND to VDD
Reference Input Voltage
BUF = 0
BUF = 1
ADS1206
ADS1207
Analog Inputs
External Clock
Operating Junction Temperature Range, TJ
(1) with reduced accuracy, minimum clock can go up to 500kHz.
NOM
5
2.5
MAX
3.6
5.5
VDD
VREF
VDD − 0.2
1
4
105
UNIT
V
V
V
V
V
MHz
MHz
°C
DISSIPATION RATING TABLE
BOARD
Low-K(2)
PACKAGE
TA ≤ 25°C
POWER RATING
DGK
High-K(3)
DGK
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
469.6mW
DERATING FACTOR
ABOVE TA = 25°C(1)
3.756mW/°C
300.5mW
244.2mW
691.4mW
5.531mW/°C
442.5mW
359.5mW
(1) This is the inverse of the traditional junction-to-ambient thermal resistance (Rq JA). Thermal resistances are not production tested and are for
informational purposes only.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3-inch x 3-inch, two-layer board with 2-ounce copper traces on top of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on the top and bottom of the board.
2
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SBAS311 − MARCH 2004
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at −40°C to +85°C, VDD = 5V or VDD = 3V, VREF = internal +2.5V, CLKIN = 1MHz, unless
otherwise noted.
ADS1206I, ADS1207I
MIN
TYP(1)
MAX
UNITS
BUF = 1
±0.012
% FSR
BUF = 0
±0.018
% FSR
TBD
% FSR
mV
PARAMETER
DC Accuracy
INL
Integral linearity error(2)
DNL
Differential nonlinearity(3)
VOS
Offset error
TCVOS
GERR
Offset error drift
Gain error(4)
TCGERR
Gain error drift
TEST CONDITIONS
BUF = 0, VIN = 0V
±7
±35
BUF = 1, VIN = 0.1V
±7
±35
mV
5
20
µV/°C
±0.1
±0.7
% FSR
Referenced to VREF
Noise
PSRR
Power-supply rejection ratio
20
ppm/°C
TBD
µVrms
4.5V < VDD < 5.5V
55
dB
3.0V < VDD < 3.6V
65
dB
FSR
Full-scale range
Input capacitance
Input current
BUF = 0
0
BUF = 1
0.1
BUF = 0
3
BUF = 1
3
BUF = 0
8
10
5
100
BUF = 1
Differential input resistance
Bandwidth
V
V
pF
pF
100
Differential input capacitance
BW
VREF
VDD − 0.2
PRODUCT PREVIEW
Analog Input
µA
nA
kΩ
1
pF
FS sinewave, −3dB, BUF = 0
TBD
MHz
FS sinewave, −3dB, BUF = 1
TBD
MHz
Output Signal
FOUT
Output frequency span
ADS1206I
0.1
0.9
CLKIN
ADS1207I
0.05
0.45
CLKIN
Voltage Reference Output
VOUT
Reference voltage output
2.3
2.5
Initial accuracy
dVOUT/dT
PSRR
Power-supply rejection ratio
%
±50
ppm/°C
100
f =10Hz to 10kHz, CL = 10µF
TBD
µVPP
µVrms
−70
dB
VDD = 4.5V to 5.5V
VDD = 3.0V to 3.6V
Reference output resistance
Turn-on settling time
V
±8
f = 0.1Hz to 10Hz, CL = 10µF
Output voltage temperature drift
Output voltage noise
2.7
to 0.1% at CL = 0
−60
dB
1
kΩ
30
µs
Voltage Reference Input
VREF
Reference voltage input
Reference input capacitance
Reference input current
TBD
2.5
VDD
V
5
pF
±200
µA
(1) All typical values are at TA = +25°C.
(2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the transfer curve for VIN = 0V to VREF or 0.1V
to VDD − 0.2V, expressed either as the number of LSBs or as a percent of measured input range.
(3) Ensured by design.
(4) Maximum values, including temperature drift, are ensured over the full specified temperature range.
(5) Applicable for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V.
(6) Applicable for 3.0V nominal supply: VDD (min) = 3.0V and VDD (max) = 3.6V.
3
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SBAS311 − MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating free-air temperature range at −40°C to +85°C, VDD = 5V or VDD = 3V, VREF = internal +2.5V, CLKIN = 1MHz, unless
otherwise noted.
PARAMETER
Digital Inputs(5)
TEST CONDITIONS
ADS1206I, ADS1207I
MIN
TYP(1)
MAX
Logic family
VIH
VIL
High-level input voltage
IIN
CI
Input current
UNITS
CMOS
0.7×VDD
−0.3
Low-level input voltage
VDD+0.3
0.3×VDD
±1
VI = VDD or GND
Input capacitance
5
V
V
µA
pF
Digital Outputs(5)
PRODUCT PREVIEW
Logic family
VOH
High-level output voltage
VOL
IO
Low-level output voltage
CO
CL
Output capacitance
Output sink current
CMOS
VDD = 4.5V, IOH = −100µA
VDD = 4.5V, IOH = −2mA
4.44
V
2.5
VDD = 4.5V, IOH = 2mA
1.5V < VOL < VDD
V
0.5
10
5
pF
Load capacitance
Digital Inputs(6)
Logic family
V
mA
30
pF
VDD+0.3
0.8
V
±1
nA
LVCMOS and LVTTL
VIH
VIL
High-level input Voltage
Low-level input voltage
VDD = 3.6V
VDD = 3.0V
IIN
CI
Input current
VI = VDD or GND
2
−0.3
Input capacitance
5
V
pF
Digital Outputs(6)
Logic family
LVCMOS and LVTTL
High-level output voltage
VDD = 3V, IOH = −100µA
VDD = 3V, IOH = −2mA
VOL
Low-level output voltage
VDD = 3V, IOH = 100µA
VDD = 3V, IOH = 2mA
IO
CO
Output sink current
10
Output capacitance
5
VOH
VDD−0.2
2.4
V
V
0.2
0.4
CL
Load capacitance
Power Supply
VDD
IDD
Power-supply voltage
Supply current
Power dissipation
V
V
mA
pF
30
pF
V
Low-voltage levels
3.0
3.6
5V logic levels
4.5
5.5
V
1.25
mA
BUF = GND
0.9
BUF = VDD
1.1
1.5
mA
VDD = 3.3V
VDD = 5V
3.63
4.95
mW
5.5
7.5
mW
(1) All typical values are at TA = +25°C.
(2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the transfer curve for VIN = 0V to VREF or 0.1V
to VDD − 0.2V, expressed either as the number of LSBs or as a percent of measured input range.
(3) Ensured by design.
(4) Maximum values, including temperature drift, are ensured over the full specified temperature range.
(5) Applicable for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V.
(6) Applicable for 3.0V nominal supply: VDD (min) = 3.0V and VDD (max) = 3.6V.
4
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SBAS311 − MARCH 2004
PIN ASSIGNMENTS
Terminal Functions
TERMINAL
VSSOP PACKAGE
(TOP VIEW)
CLKOUT
1
NAME
BUF
8
NO.
DESCRIPTION
CLKOUT
1
Clock output
CLKIN
2
Master clock input
GND
3
Ground
Reference voltage input or output
CLKIN
2
7
FOUT
REFIN/OUT
4
GND
3
6
VDD
VIN
5
Analog input
VIN
VDD
FOUT
6
Power supply, +3.3V or +5V nominal
7
Modulator output
BUF
8
Buffered mode select
REFIN/OUT
4
5
PARAMETER MEASUREMENT INFORMATION
tC1
tD1
PRODUCT PREVIEW
CLKIN
tW1
FOUT
tW2
tR1
tF1
Figure 1. Timing Diagram
TIMING REQUIREMENTS: 5.0V
over recommended operating free-air temperature range at −40°C to +85°C,, and VDD = 5V, unless otherwise noted.
PARAMETER
tC1
Input clock period
tW1
tD1
Input clock high time
tW2
tR1
FOUT high time
MIN
MAX
UNITS
ADS1206
1000
TBD
ns
ADS1207
250
TBD
ns
(tC1/2) − 100
TBD
(tC1/2) + 100
TBD
ns
tC1 − 20
TBD
tC1 + 20
TBD
ns
FOUT rising edge delay after input clock rising edge
FOUT rise time
ns
ns
tF1
FOUT fall time
TBD
TBD
ns
NOTE: Applicable for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V. All input signals are specified with tR = tF = 5ns (10% to 90%
of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram.
TIMING REQUIREMENTS: 3.3V
over recommended operating free-air temperature range at −40°C to +85°C,, and VDD = 3.3V, unless otherwise noted.
PARAMETER
tC1
Input clock period
tW1
tD1
Input clock high time
tW2
tR1
FOUT high time
MIN
MAX
UNITS
ADS1206
1000
TBD
ns
ADS1207
250
TBD
ns
(tC1/2) − 100
TBD
(tC1/2) + 100
TBD
ns
tC1 − 8
TBD
tC1 + 8
TBD
ns
FOUT rising edge delay after input clock rising edge
FOUT rise time
ns
ns
tF1
FOUT fall time
TBD
TBD
ns
NOTE: Applicable for 3.3V nominal supply: VDD (min) = 3.0V and VDD (max) = 3.6V. All input signals are specified with tR = tF = 5ns (10% to 90%
of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram.
5
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS1206IDGKR
PREVIEW
MSOP
DGK
8
2500
None
Call TI
Call TI
ADS1206IDGKT
PREVIEW
MSOP
DGK
8
250
None
Call TI
Call TI
ADS1207IDGKR
PREVIEW
MSOP
DGK
8
None
Call TI
Call TI
ADS1207IDGKT
PREVIEW
MSOP
DGK
8
None
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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