CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200 and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • 3.3V power supply • 3.3V/2.5V I/O power supply • Fast clock-to-output times — 2.6 ns (for 250-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • CY7C1460AV33, CY7C1462AV33 available in JEDEC-standard lead-free 100-pin TQFP, lead-free and non-lead-free 165-ball FBGA package. CY7C1464AV33 available in lead-free and non-lead-free 209-ball FBGA package • IEEE 1149.1 JTAG-Compatible Boundary Scan • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects for CY7C1464AV33, BWa–BWd for (BWa–BWh CY7C1460AV33 and BWa–BWb for CY7C1462AV33) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Logic Block Diagram-CY7C1460AV33 (1M x 36) A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 S E N S E ADV/LD BWa BWb BWc BWd WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC MEMORY ARRAY WRITE DRIVERS A M P S WE O U T P U T R E G I S T E R S E INPUT REGISTER 1 OE CE1 CE2 CE3 ZZ Cypress Semiconductor Corporation Document #: 38-05353 Rev. *D E O U T P U T D A T A S T E E R I N G INPUT REGISTER 0 B U F F E R S DQs DQPa DQPb DQPc DQPd E E READ LOGIC SLEEP CONTROL • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 22, 2006 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Logic Block Diagram-CY7C1462AV33 (2M x 18) ADDRESS REGISTER 0 A0, A1, A A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWa MEMORY ARRAY WRITE DRIVERS BWb O U T P U T S E N S E R E G I S T E R S A M P S WE O U T P U T D A T A B U F F E R S S T E E R I N G E INPUT REGISTER 1 E OE CE1 CE2 CE3 DQs DQPa DQPb E INPUT REGISTER 0 E READ LOGIC Sleep Control ZZ Logic Block Diagram-CY7C1464AV33 (512K x 72) A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD BWa BWb BWc BWd BWe BWf BWg BWh WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S O U T P U T D A T A B U F F E R S S T E E R I N G E E DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh WE INPUT REGISTER 1 E OE CE1 CE2 CE3 ZZ INPUT REGISTER 0 E READ LOGIC Sleep Control Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Document #: 38-05353 Rev. *D 250 MHz 200 MHz 167 MHz Unit 2.6 475 120 3.2 425 120 3.4 375 120 ns mA mA Page 2 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1462AV33 (2M × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A A A A A A A A NC/72M VSS VDD NC/144M A A A A A A A A NC/72M VSS VDD NC/144M NC/288M MODE A A A A A1 A0 Document #: 38-05353 Rev. *D NC DQPb NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb DQb NC DQb DQb DQb DQb VSS VSS VDDQ VDDQ DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQb DQa DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb DQa NC VSS VSS VDDQ VDDQ NC DQa DQa NC DQPa NC NC/288M CY7C1460AV33 (1M × 36) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS DQc DQc DQc DQc VSS VDDQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 DQPc DQc DQc VDDQ A A A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A 100-pin TQFP Pinout Page 3 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1460AV33 (1M × 36) 1 2 A B C D E F G H J K L M N P NC/576M R MODE 3 4 5 6 7 8 BWc BWb CE3 CLK CEN WE A CE1 NC/1G A CE2 DQPc DQc NC DQc VDDQ DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd 9 10 11 ADV/LD A A NC OE A A NC VSS VSS VSS VDD VDDQ DQPb DQb BWa VSS VDDQ BWd VSS VDD VSS VSS VSS VDDQ NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc VDDQ VDD VSS VSS VSS VDD DQb VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQb DQc NC DQd DQb NC DQa DQb ZZ DQa DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd NC VDDQ VDDQ VDD VSS VSS NC VSS NC VSS NC VDD VSS VDDQ VDDQ DQa NC DQa DQPa A A TDI A1 TDO A A A NC/288M A A TMS A0 TCK A A A A 11 NC/144M NC/72M A CY7C1462AV33 (2M × 18) A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 NC/576M A CE1 BWb NC NC CE3 CEN ADV/LD A A A NC NC/1G A CE2 NC NC NC DQb VDDQ NC DQb NC NC NC DQb DQb DQb DQb DQb DQPb BWa CLK VDDQ VDDQ VSS VSS VSS OE VSS VDD A VSS WE VSS VSS A VSS VDD VDDQ NC NC DQPa DQa VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa VDDQ VDDQ NC VDDQ VDD VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ NC VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD NC NC DQa DQa DQa ZZ NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC NC NC VDDQ VDDQ VDD VSS VSS NC VSS NC VSS NC VDD VSS VDDQ VDDQ DQa NC NC NC A A TDI A1 TDO A A A A A TMS A0 TCK A A A DQb NC NC NC/144M NC/72M MODE A Document #: 38-05353 Rev. *D NC/288M A Page 4 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1464AV33 (512K x 72) 1 2 A DQg DQg B DQg DQg C DQg D 3 4 5 6 7 8 9 10 11 ADV/LD A CE3 A DQb DQb WE A BWSb BWSf DQb DQb CE1 NC BWSe BWSa DQb DQb NC NC VSS DQb DQb DQPf DQPb CE2 A BWSc BWSg NC DQg BWSh BWSd NC/576M DQg DQg VSS NC NC/1G OE E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf G DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf H DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf J DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf K NC NC CLK NC VSS CEN VSS NC NC NC NC L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa R DQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ T DQd DQd VSS NC NC MODE NC NC DQe DQe U DQd DQd NC/144M A A A A NC/288M DQe DQe V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TCK DQe DQe A NC/72M TDO VSS DQPa DQf DQPe Pin Definitions Pin Name I/O Type Pin Description A0 A1 A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. BWa BWb BWc BWd BWe BWf BWg BWh InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh. WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Document #: 38-05353 Rev. *D Page 5 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Pin Definitions (continued) Pin Name I/O Type Pin Description CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputAsynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQa DQb DQc DQd DQe DQf DQg DQh I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by AX during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPa,DQPb, DQPc,DQPd DQPe,DQPf DQPg,DQPh I/OSynchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh. Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. MODE TDO JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Synchronous TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. Synchronous TMS Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of Synchronous TCK. TCK JTAG-Clock VDD Power Supply VDDQ Clock input to the JTAG circuitry. Power supply inputs to the core of the device. I/O Power Supply Power supply for the I/O circuitry. VSS NC NC/72M Ground N/A N/A NC/144M N/A Not connected to the die. Can be tied to any voltage level. NC/288M N/A Not connected to the die. Can be tied to any voltage level. NC/576M N/A Not connected to the die. Can be tied to any voltage level. NC/1G N/A Not connected to the die. Can be tied to any voltage level. ZZ InputAsynchronous Document #: 38-05353 Rev. *D Ground for the device. Should be connected to ground of the system. No connects. This pin is not connected to the die. Not connected to the die. Can be tied to any voltage level. ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to VSS or left floating. ZZ pin has an internal pull-down. Page 6 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Functional Overview The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[x] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tri-state following the next clock rise. Burst Read Accesses The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment Document #: 38-05353 Rev. *D the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1464AV33, DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ and DQP for CY7C1464AV33, (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 & DQa,b/DQPa,b for CY7C1462AV33) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BW (BWa,b,c,d,e,f,g,h for CY7C1464AV33, BWa,b,c,d for CY7C1460AV33 and BWa,b for CY7C1462AV33) signals. The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1464AV33, DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33) inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1464AV33, DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33) are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst Page 7 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for CY7C1464AV33, BWa,b,c,d for CY7C1460AV33 and BWa,b for CY7C1462AV33) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Interleaved Burst Address Table (MODE = Floating or VDD) Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. First Address Second Address Third Address Fourth Address A1,A0 A1,A0 A1,A0 A1,A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address Second Address Third Address Fourth Address A1,A0 A1,A0 A1,A0 A1,A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit IDDZZ Sleep mode standby current ZZ > VDD − 0.2V 100 mA tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ active to sleep current This parameter is sampled tRZZI ZZ Inactive to exit sleep current This parameter is sampled 2tCYC ns 2tCYC 0 ns ns Truth Table[1, 2, 3, 4, 5, 6, 7] Operation Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Address Used None None CE H X ZZ L L ADV/LD L H WE X X BWx X X OE X X CEN L L CLK L-H L-H DQ Tri-State Tri-State External L L L H X L L L-H Data Out (Q) Next X L H X X L L L-H Data Out (Q) External L L L H X H L L-H Tri-State Next X L H X X H L L-H Tri-State Notes: 1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWX. See Write Cycle Description table for details. 3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes. 4. The DQ and DQP pins are controlled by the current cycle and the OE signal. 5. CEN = H inserts wait states. 6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tri-state when OE is inactive or when the device is deselected, and DQs=data when OE is active. Document #: 38-05353 Rev. *D Page 8 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Truth Table[1, 2, 3, 4, 5, 6, 7] (continued) Operation Write Cycle (Begin Burst) Write Cycle (Continue Burst) NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SLEEP MODE Address Used External CE L ZZ L ADV/LD L WE L BWx L OE X CEN L CLK L-H DQ Data In (D) Next X L H X L X L L-H Data In (D) None L L L L H X L L-H Tri-State Next X L H X H X L L-H Tri-State Current X L X X X X H L-H - None X H X X X X X X Tri-State Partial Write Cycle Description[1, 2, 3, 8] Function (CY7C1460AV33) WE BWd BWc BWb BWa Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQa and DQPa) L H H H L Write Byte b – (DQb and DQPb) L H H L H Write Bytes b, a L H H L L Write Byte c – (DQc and DQPc) L H L H H Write Bytes c, a L H L H L Write Bytes c, b L H LL L H Write Bytes c, b, a L H L L L Write Byte d – (DQd and DQPd) L L H H H Write Bytes d, a L L H H L Write Bytes d, b L L H L H Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L L Function (CY7C1462AV33)[2,8] WE BWb BWa Read H x x Write – No Bytes Written L H H Write Byte a – (DQa and DQPa) L H L Write Byte b – (DQb and DQPb) L L H Write Both Bytes L L L Function (CY7C1464AV33)[2,8] WE BWx Read H x Write – No Bytes Written L H Write Byte X − (DQx and DQPx) L L Write All Bytes L All BW = L Note: 8. Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05353 Rev. *D Page 9 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 IEEE 1149.1 Serial Boundary Scan (JTAG) Test Data-In (TDI) The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Disabling the JTAG Feature Test Data-Out (TDO) It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic level. TAP Controller Block Diagram 0 TAP Controller State Diagram 1 Bypass Register TEST-LOGIC RESET 2 1 0 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 0 Selection Circuitry TDO Identification Register CAPTURE-IR x . . . . . 2 1 0 Boundary Scan Register SHIFT-IR 1 Instruction Register 31 30 29 . . . 2 1 0 0 SHIFT-DR 0 1 EXIT1-DR 1 EXIT1-IR 0 1 0 PAUSE-IR 1 TCK TMS 0 PAUSE-DR TAP CONTROLLER 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 TDI 0 1 CAPTURE-DR 0 0 1 Selection Circuitry 0 UPDATE-IR 1 0 Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Document #: 38-05353 Rev. *D TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. Page 10 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The length of the Boundary Scan Register for the SRAM in different packages is listed in the Scan Register Sizes table. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. Document #: 38-05353 Rev. *D SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #89 (for 165-FBGA package) or bit #138 (for 209-FBGA package). Page 11 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. Reserved This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 2 Test Clock (TCK) 3 t TH t TMSS t TMSH t TDIS t TDIH t TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[9, 10] Parameter Description Min. Max. Unit Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns 50 ns 20 MHz Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 10 ns 0 ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise 5 ns tTDIS TDI Set-up to TCK Clock Rise 5 ns tCS Capture Set-up to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Hold Times Notes: 9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document #: 38-05353 Rev. *D Page 12 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input rise and fall times ................................................... 1 ns Input pulse levels ................................................ VSS to 2.5V Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.5V Input timing reference levels......................................... 1.25V Output reference levels...................................................1.5V Output reference levels ................................................ 1.25V Test load termination supply voltage...............................1.5V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Output Load Equivalent 1.5V 1.25V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11] Parameter Description Test Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH = –4.0 mA, VDDQ = 3.3V 2.4 V IOH = –1.0 mA, VDDQ = 2.5V 2.0 V VOH2 Output HIGH Voltage IOH = –100 µA VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 VOL1 Output LOW Voltage IOL = 8.0 mA VDDQ = 3.3V 0.4 V IOL = 1.0 mA VDDQ = 2.5V 0.4 V VOL2 Output LOW Voltage IOL = 100 µA VDDQ = 3.3V 0.2 V VIH Input HIGH Voltage VDDQ = 3.3V VIL Input LOW Voltage VDDQ = 2.5V IX Input Load Current VDDQ = 2.5V V 0.2 V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.3 0.8 V –0.3 0.7 V –5 5 µA GND < VIN < VDDQ Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24)[12] CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 (1M ×36) (2M ×18) (512K ×72) 000 000 000 Description Describes the version number. 01011 01011 01011 Architecture/Memory Type(23:18) 001000 001000 001000 Defines memory type and architecture Bus Width/Density(17:12) 100111 010111 110111 Defines width and density 00000110100 00000110100 00000110100 1 1 1 Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) Reserved for Internal Use Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Notes: 11. All voltages referenced to VSS (GND). 12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device. Document #: 38-05353 Rev. *D Page 13 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Scan Register Sizes Register Name Instruction Bit Size (×36) Bit Size (×18) Bit Size (×72) 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order (165-ball FBGA package) 89 89 - Boundary Scan Order (209-ball FBGA package) - - 138 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05353 Rev. *D Page 14 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 165-ball FBGA Boundary Scan Order [13] CY7C1460AV33 (1M x 36), CY7C1462AV33 (2M x 18) Bit# ball ID Bit# ball ID Bit# ball ID Bit# ball ID 1 N6 26 E11 51 A3 76 N1 2 N7 27 D11 52 A2 77 N2 3 10N 28 G10 53 B2 78 P1 4 P11 29 F10 54 C2 79 R1 5 P8 30 E10 55 B1 80 R2 6 R8 31 D10 56 A1 81 P3 7 R9 32 C11 57 C1 82 R3 8 P9 33 A11 58 D1 83 P2 9 P10 34 B11 59 E1 84 R4 10 R10 35 A10 60 F1 85 P4 11 R11 36 B10 61 G1 86 N5 12 H11 37 A9 62 D2 87 P6 13 N11 38 B9 63 E2 88 R6 14 M11 39 C10 64 F2 89 Internal 15 L11 40 A8 65 G2 16 K11 41 B8 66 H1 17 J11 42 A7 67 H3 18 M10 43 B7 68 J1 19 L10 44 B6 69 K1 20 K10 45 A6 70 L1 21 J10 46 B5 71 M1 22 H9 47 A5 72 J2 23 H10 48 A4 73 K2 24 G11 49 B4 74 L2 25 F11 50 B3 75 M2 Note: 13. Bit# 89 is preset HIGH. Document #: 38-05353 Rev. *D Page 15 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 209-ball BGA Boundary Scan Order [13, 14] CY7C14604V33 (512K x 72) Bit# Ball ID Bit# 1 W6 36 6F 71 6H 106 3K 8K 72 6C 107 4K 3 V6 U6 37 38 9K 73 6B 108 6K 4 W7 39 10K 74 6A 109 2K 2 ball ID Bit# ball ID Bit# ball ID 5 V7 40 11J 75 5A 110 2L 6 U7 41 10J 76 5B 111 1L 7 T7 42 11H 77 5C 112 2 Mbit 8 V8 43 10H 78 5D 113 1 Mbit 9 U8 44 11G 79 4D 114 2N 10 T8 45 10G 80 4C 115 1N 11 V9 46 11F 81 4A 116 2P 12 U9 47 10F 82 4B 117 1P 13 P6 48 10E 83 3C 118 2R 14 W11 49 11E 84 3B 119 1R 15 W10 50 11D 85 3A 120 2T 16 V11 51 10D 86 2A 121 1T 17 V10 52 11C 87 1A 122 2U 18 U11 53 10C 88 2B 123 1U 19 U10 54 11B 89 1B 124 2V 20 T11 55 10B 90 2C 125 1V 21 T10 56 11A 91 1C 126 2W 22 R11 57 10A 92 2D 127 1W 23 R10 58 9C 93 1D 128 6T 24 P11 59 9B 94 1E 129 3U 25 P10 60 9A 95 2E 130 3V 26 N11 61 8D 96 2F 131 4T 27 N10 62 8C 97 1F 132 5T 28 M11 63 8B 98 1G 133 4U 29 M10 64 8A 99 2G 134 4V 30 L11 65 7D 100 2H 135 5W 31 L10 66 7C 101 1H 136 5V 32 K11 67 7B 102 2J 137 5U 33 M6 68 7A 103 1J 138 Internal 34 L6 69 6D 104 1K 35 J6 70 6G 105 6N Note: 14. Bit# 138 is preset HIGH. Document #: 38-05353 Rev. *D Page 16 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V Range Ambient Temperature Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD Commercial 0°C to +70°C DC to Outputs in Tri-State ................... –0.5V to VDDQ + 0.5V Industrial –40°C to +85°C VDD VDDQ 3.3V –5%/+10% 2.5V –5% to VDD DC Input Voltage....................................–0.5V to VDD + 0.5V Electrical Characteristics Over the Operating Range[15, 16] DC Electrical Characteristics Over the Operating Range Parameter Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH VOL VIH VIL IX Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Voltage[15] Voltage[15] Input Leakage Current except ZZ and MODE Test Conditions Min. Max. Unit 3.135 3.6 V for 3.3V I/O 3.135 VDD V for 2.5V I/O 2.375 2.625 V for 3.3V I/O, IOH = −4.0 mA 2.4 V for 2.5V I/O, IOH = −1.0 mA 2.0 V for 3.3V I/O, IOL = 8.0 mA 0.4 V for 2.5V I/O, IOL = 1.0 mA 0.4 V for 3.3V I/O 2.0 VDD + 0.3V V for 2.5V I/O 1.7 VDD + 0.3V V for 3.3V I/O –0.3 0.8 V for 2.5V I/O –0.3 0.7 V –5 5 µA GND ≤ VI ≤ VDDQ Input Current of MODE Input = VSS Input Current of ZZ 5 Input = VSS 30 IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply µA µA –5 Input = VDD VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC µA –30 Input = VDD µA 5 µA 4-ns cycle, 250 MHz 475 mA 5-ns cycle, 200 MHz 425 mA 6-ns cycle, 167 MHz 375 mA –5 ISB1 Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, All speed grades VIN ≥ VIH or VIN ≤ VIL, f = fMAX = 1/tCYC 225 mA ISB2 Automatic CE Max. VDD, Device Deselected, All speed grades Power-down VIN ≤ 0.3V or VIN > VDDQ − 0.3V, Current—CMOS Inputs f = 0 120 mA ISB3 Automatic CE Max. VDD, Device Deselected, All speed grades Power-down VIN ≤ 0.3V or VIN > VDDQ − 0.3V, Current—CMOS Inputs f = fMAX = 1/tCYC 200 mA ISB4 Automatic CE Power-down Current—TTL Inputs 135 mA Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 All speed grades Notes: 15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2). 16. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05353 Rev. *D Page 17 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Capacitance[17] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TA = 25°C, f = 1 MHz, VDD = 2.5V VDDQ = 2.5V 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit 6.5 7 5 pF 3 7 5 pF 5.5 6 7 pF 100 TQFP Package 165 FBGA Package 209 FBGA Package Unit 25.21 20.8 25.31 °C/W 2.28 3.2 4.48 °C/W Thermal Resistance[17] Parameters Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω 10% GND 5 pF VT = 1.5V (a) INCLUDING JIG AND SCOPE 2.5V I/O Test Load 2.5V OUTPUT R = 351Ω VT = 1.25V (a) 5 pF INCLUDING JIG AND SCOPE ≤ 1 ns ≤ 1 ns (b) (c) R = 1667Ω ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω 90% 10% 90% 10% 90% 10% 90% GND R =1538Ω (b) ≤ 1 ns ≤ 1 ns (c) Note: 17. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05353 Rev. *D Page 18 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Switching Characteristics Over the Operating Range [22, 23] –250 –200 Parameter Description Min. [18] VCC (typical) to the first access read or write 1 1 1 ms 4.0 5.0 6.0 ns tPower Max. Min. –167 Max. Min. Max. Unit Clock tCYC Clock Cycle Time FMAX Maximum Operating Frequency tCH Clock HIGH 1.5 2.0 2.4 ns tCL Clock LOW 1.5 2.0 2.4 ns 250 200 167 MHz Output Times tCO Data Output Valid After CLK Rise tEOV OE LOW to Output Valid tDOH Data Output Hold After CLK Rise tCHZ Clock to High-Z[19, 20, 21] Clock to Low-Z[19, 20, 21] tCLZ tEOHZ tEOLZ OE HIGH to Output High-Z[19, 20, 21] OE LOW to Output Low-Z[19, 20, 21] 2.6 3.2 2.6 1.0 3.0 1.5 2.6 1.0 ns 3.4 ns 1.5 3.0 1.3 2.6 3.4 ns 3.4 1.5 3.0 ns ns 3.4 ns 0 0 0 ns Set-up Times tAS Address Set-up Before CLK Rise 1.2 1.4 1.5 ns tDS Data Input Set-up Before CLK Rise 1.2 1.4 1.5 ns tCENS CEN Set-up Before CLK Rise 1.2 1.4 1.5 ns tWES WE, BWx Set-up Before CLK Rise 1.2 1.4 1.5 ns tALS ADV/LD Set-up Before CLK Rise 1.2 1.4 1.5 ns tCES Chip Select Set-up 1.2 1.4 1.5 ns tAH Address Hold After CLK Rise 0.3 0.4 0.5 ns tDH Data Input Hold After CLK Rise 0.3 0.4 0.5 ns Hold Times tCENH CEN Hold After CLK Rise 0.3 0.4 0.5 ns tWEH WE, BWx Hold After CLK Rise 0.3 0.4 0.5 ns tALH ADV/LD Hold after CLK Rise 0.3 0.4 0.5 ns tCEH Chip Select Hold After CLK Rise 0.3 0.4 0.5 ns Notes: 18. This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can be initiated. 19. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 21. This parameter is sampled and not 100% tested. 22. Timing reference is 1.5V when VDDQ=3.3V and is 1.25V when VDDQ=2.5V. 23. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05353 Rev. *D Page 19 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Switching Waveforms Read/Write/Timing[24, 25, 26] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BWx A1 ADDRESS A2 tCO tAS tDS tAH Data tDH D(A1) tCLZ D(A2) D(A2+1) tDOH Q(A3) tOEV Q(A4) tCHZ Q(A4+1) D(A5) Q(A6) In-Out (DQ) tOEHZ tDOH tOELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT UNDEFINED Notes: 24. For this waveform ZZ is tied low. 25. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional. Document #: 38-05353 Rev. *D Page 20 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Switching Waveforms (continued) NOP,STALL and DESELECT Cycles[24, 25, 27] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BWx ADDRESS A5 tCHZ D(A1) Data Q(A2) D(A4) Q(A3) Q(A5) In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL DON’T CARE NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED ZZ Mode Timing[28, 29] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. 28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 29. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05353 Rev. *D Page 21 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1460AV33-167AXC Package Diagram Operating Range Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1462AV33-167AXC CY7C1460AV33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1462AV33-167BZC CY7C1460AV33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1462AV33-167BZXC CY7C1464AV33-167BGC CY7C1464AV33-167BGXC CY7C1460AV33-167AXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial CY7C1462AV33-167AXI CY7C1460AV33-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1462AV33-167BZI CY7C1460AV33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1462AV33-167BZXI CY7C1464AV33-167BGI CY7C1464AV33-167BGXI 200 CY7C1460AV33-200AXC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1462AV33-200AXC CY7C1460AV33-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1462AV33-200BZC CY7C1460AV33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1462AV33-200BZXC CY7C1464AV33-200BGC CY7C1464AV33-200BGXC CY7C1460AV33-200AXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial CY7C1462AV33-200AXI CY7C1460AV33-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1462AV33-200BZI CY7C1460AV33-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1462AV33-200BZXI CY7C1464AV33-200BGI CY7C1464AV33-200BGXI Document #: 38-05353 Rev. *D 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free Page 22 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 250 Ordering Code CY7C1460AV33-250AXC Package Diagram Operating Range Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1462AV33-250AXC CY7C1460AV33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1462AV33-250BZC CY7C1460AV33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1462AV33-250BZXC CY7C1464AV33-250BGC CY7C1464AV33-250BGXC CY7C1460AV33-250AXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial CY7C1462AV33-250AXI CY7C1460AV33-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1462AV33-250BZI CY7C1460AV33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1462AV33-250BZXI CY7C1464AV33-250BGI CY7C1464AV33-250BGXI Document #: 38-05353 Rev. *D 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free Page 23 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Package Diagrams 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 81 100 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0.60±0.15 0.20 MIN. 51-85050-*B 1.00 REF. DETAIL Document #: 38-05353 Rev. *D A Page 24 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Package Diagrams (continued) 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165) PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 0.35 0.15 C +0.05 -0.10 0.53±0.05 0.25 C 10.00 B 15.00±0.10 0.15(4X) SEATING PLANE 1.40 MAX. 0.36 C 51-85165-*A Document #: 38-05353 Rev. *D Page 25 of 27 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Package Diagrams (continued) 209-ball FBGA (14 x 22 x 1.76 mm) (51-85167) 51-85167-** ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus Latency and NoBL are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-05353 Rev. *D Page 26 of 27 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Document History Page Document Title: CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05353 REV. ECN No. Issue Date Orig. of Change ** 254911 See ECN SYT New Data sheet Part number changed from previous revision. New and old part number differ by the letter “A” *A 303533 See ECN SYT Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA on Page # 5 Changed the test condition from VDD = Min to VDD = Max for VOL in the Electrical Characteristics table Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All Packages on the Thermal Resistance Table Changed IDD from 450, 400 & 350 mA to 475, 425 & 375 mA for 250, 200 and 167 MHz respectively Changed ISB1 from 190, 180 and 170 mA to 225 mA for 250, 200 and 167 MHz respectively Changed ISB2 from 80 mA to 100 mA for all frequencies Changed ISB3 from 180, 170 & 160 mA to 200 mA for 250, 200 and 167 MHz respectively Changed ISB4 from 100 mA to 110 mA for all frequencies Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP Package Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 MHz Speed Bin Added lead-free information for 100-pin TQFP and 165 FBGA and 209 BGA packages *B 331778 See ECN SYT Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA Package Added Industrial Temperature Grade Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively Updated the Ordering Information by Shading and Unshading MPNs as per availability *C 417509 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed IX current value in MODE from –5 & 30 µA to –30 & 5 µA respectively and also Changed IX current value in ZZ from –30 & 5 µA to –5 & 30 µA respectively on page# 18 Modified test condition from VIH < VDD to VIH < VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from *A to *B *D 473229 See ECN NXR Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table. Document #: 38-05353 Rev. *D Description of Change Page 27 of 27 [+] Feedback