CAT5271, CAT5273 Dual 256‐position I2C Compatible Digital Potentiometers (POTs) The CAT5271 and CAT5273 are dual 256-position digital programmable linear taper potentiometers ideally suited for replacing mechanical potentiometers and variable resistors. The wiper settings are controlled through an I2C-compatible digital interface. Upon power-up, the wiper assumes a midscale position and may be repositioned anytime after the power is stable. The devices can be programmed to go to a shutdown state during operation. The CAT5271 and CAT5273 operate from 2.7 V to 5.5 V, while consuming less than 2 mA. This low operating current, combined with a small package footprint, makes them ideal for battery-powered portable applications. The CAT5271 and CAT5273, designed as pin for pin replacements for the AD5243 and AD5248, are offered in the 10-lead MSOP package and operate over the −40C to +85C industrial temperature range. http://onsemi.com MSOP−10 Z SUFFIX CASE 846AE MARKING DIAGRAMS ANCC YMR Features Dual 256-position End-to-End Resistance: 50 kW, 100 kW I2C Compatible Interface* Power-on Preset to Midscale Single Supply 2.7 V to 5.5 V Low Temperature Coefficient 100 ppm/C Low Power, IDD 2 mA max Wide Operating Temperature −40C to +85C MSOP−10 Package (3 mm 4.9 mm) These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications ANCC = CAT5721 − 50 kW ANCE = CAT5721 − 100 kW PA = CAT5273 − 50 kW* Y = Production Year (Last Digit) M = Production Month (1−9, O, N, D) R = Revision L = Assembly Location XX = Last Two Digits of Assembly Lot Number *Contact factory for availability of CAT5273 − 100 kW PIN CONNECTIONS B1 Potentiometer Replacement Transducer Adjustment of Pressure, Temperature, Position, Chemical, and Optical Sensors 1 1 1 PAYM LXX ANCE YMR 1 A1 W2 GND CAT5271 SCL VDD RF Amplifier Biasing Gain Control and Offset Adjustment B1 AD0 W2 GND *Two address decode pins (CAT5273 only) allowing multiple devices on the same bus W1 B2 A2 SDA 1 CAT5273 W1 B2 AD1 SDA SCL VDD (Top Views) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. Semiconductor Components Industries, LLC, 2013 July, 2013 − Rev. 3 1 Publication Order Number: CAT5271/D CAT5271, CAT5273 SDA I2C Interface SCL A1 Wiper Control Register 1 VCC Wiper Control Register 1 W1 SCL B1 SDA A2 Wiper Control Register 2 I2C Interface VCC W2 B2 GND AD0 Figure 1. CAT5271 Functional Block Diagram B1 Wiper Control Register 2 Control Logic GND W1 W2 B2 AD1 Figure 2. CAT5273 Functional Block Diagram Table 1. PIN FUNCTION DESCRIPTION CAT5271 CAT5273 Pin No. Pin Name Description Pin Name Description 1 B1 B1 Terminal B1 2 A1 A1 Terminal AD0 Device Address Bit 0 3 W2 W2 Terminal W2 W2 Terminal 4 GND Digital Ground GND Digital Ground 5 VDD Positive Power Supply VDD Positive Power Supply 6 SCL Serial Clock Input SCL Serial Clock Input 7 SDA Serial Data Input / Output SDA Serial Data Input / Output 8 A2 A2 Terminal AD1 Device Address Bit 1 9 B2 B2 Terminal B2 B2 Terminal 10 W1 W1 Terminal W1 W1 Terminal B1 Terminal Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1) Rating VDD to GND Value Unit −0.3 to 6.5 V A1, B1, W1, A2, B2, W2 Voltage to GND VDD IMAX 20 mA 0 to 6.5 V −40 to +85 C 150 C −65 to +150 C 300 C Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. http://onsemi.com 2 CAT5271, CAT5273 Table 3. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions VDD = 2.7 V to 5.5 V; VA = VDD; VB = 0 V; –40C < TA < +85C; unless otherwise noted. (Note 2) Test Conditions Symbol Min Typ (Note 3) Max Unit Resistor Differential Nonlinearity (Note 4) RWB, VA = no connection (CAT5271) R−DNL −1 0.1 +1 LSB Resistor Integral Nonlinearity (Note 4) 0.4 +2 LSB Parameter DC CHARACTERISTICS − RHEOSTAT MODE RWB, VA = no connection (CAT5271) R−INL −2 Nominal Resistor Tolerance (Note 5) TA = 25C nRAB −20 Resistance Temperature Coefficient VAB = VDD, Wiper = no connection nRAB/nT VDD = 5 V, IW = 3 mA RW Wiper Resistance +20 100 VDD = 3 V, IW = 3 mA % ppm/C 50 120 100 250 W DC CHARACTERISTICS − POTENTIOMETER DIVIDER MODE N Resolution 8 Bits LSB Differential Nonlinearity (Note 6) DNL −1 0.1 +1 Integral Nonlinearity (Note 6) INL −1 0.4 +1 100 LSB Voltage Divider Temperature Coefficient Code = 0x80 nVW/nT ppm/C Full-scale Error Code = 0xFF VWFSE −3 −1 0 LSB Zero-scale Error Code = 0x00 VWZSE 0 1 3 LSB VA,B,W GND VDD V RESISTOR TERMINALS Voltage Range (Note 7) Capacitance (Note 8) A, B f = 1 MHz, measured to GND, Code = 0 x 80 CA,B 45 pF Capacitance (Note 8) W f = 1 MHz, measured to GND, Code = 0 x 80 CW 60 pF VA = VB = VDD/2 ICM 1 nA Input Logic High VDD = 5 V VIH Input Logic Low VDD = 5 V VIL Input Logic High VDD = 3 V VIH VDD = 3 V VIL 0.3VDD V VIN = 0 V or 5 V IIL 1 mA 5.5 V Common-mode Leakage (Note 8) DIGITAL INPUTS Input Logic Low Input Current 0.7 x VDD V 0.3VDD 0.7 x VDD V V POWER SUPPLIES VDD RANGE Power Supply Range Supply Current Power Dissipation (Note 8) Power Supply Sensitivity 2.7 VIH = 5 V or VIL = 0 V IDD 2 mA VIH = 5 V or VIL = 0 V, VDD = 5 V PDISS 0.3 0.2 mW nVDD = +5 V 10%, Code = Midscale PSS 0.05 %/% DYNAMIC CHARACTERISTICS (Notes 8 and 10) Bandwidth –3 dB Total Harmonic Distortion VW Settling Time (50 kW/100 kW) RAB = 50 kW / 100 kW, Code = 0x80 BW 100/40 kHz VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kW THDW 0.05 % VA = 5 V, VB = 0 V, 1 LSB error band tS 2 ms 2. VA applies to both A1 and A2, VB applies to both B1 and B2. 3. Typical specifications represent average readings at +25C and VDD = 5 V. 4. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 5. CAT5271: VAB = VDD, Wiper (VW) = no connect. CAT5273: VWB = VDD. 6. INL and DNL are measured at VW with the digital potentiometer configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 7. Resistor terminals A, B, W have no limitations on polarity with respect to each other. 8. Guaranteed by design and not subject to production test. 9. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 10. All dynamic characteristics use VDD = 5 V. http://onsemi.com 3 CAT5271, CAT5273 Table 4. CAPACITANCE TA = 25C, f = 1.0 MHz, VDD = 5 V Symbol CI/O (Note 11) Test Input/Output Capacitance (SDA, SCL) Conditions Max Units VI/O = 0 V 8 pF Max Units Table 5. POWER UP TIMING (Notes 11 and 12) Symbol Parameter tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms 11. This parameter is tested initially and after a design or process change that affects the parameter. 12. tPUR and t PUW are delays required from the time VCC is stable until the specified operation can be initiated. Table 6. DIGITAL POTENTIOMETER TIMING Symbol tWRPO tWR Max Units Wiper Response Time After Power Supply Stable Parameter Min 50 ms Wiper Response Time: SCL falling edge after last bit of wiper position data byte to wiper change 20 ms Max Units 400 kHz Table 7. A.C. CHARACTERISTICS VDD = +2.7 V to +5.5 V, −40C to +85C unless otherwise specified. Parameter Symbol Min Typ fSCL Clock Frequency tHIGH Clock High Period 600 ns tLOW Clock Low Period 1300 ns tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 600 ns tHD:STA Start Condition Hold Time 600 ns tSU:DAT Data in Setup Time 100 ns tHD:DAT Data in Hold Time 0 ns tSU:STO Stop Condition Setup Time 600 ns Time the bus must be free before a new transmission can start 1300 ns tBUF tR SDA and SCL Rise Time 300 ns tF SDA and SCL Fall Time 300 ns tDH Data Out Hold Time 100 ns TI Noise Suppression Time Constant at SCL, SDA Inputs 50 ns tAA SCL Low to SDA Data Out and ACK Out 1 ms http://onsemi.com 4 CAT5271, CAT5273 TYPICAL CHARACTERISTICS 0.03 0.1 0.02 0 DNL ERROR (LSB) ERROR (LSB) 0.01 0 −0.01 −0.02 −0.1 INL −0.2 −0.3 −0.03 −0.4 −0.04 −0.05 0 32 64 96 128 160 192 224 −0.5 256 64 96 128 160 192 224 256 TAP Figure 3. Potentiometer Divider Differential Non-linearity, VDD = 5.6 V Figure 4. Potentiometer Divider Integral Non-linearity, VDD = 5.6 V 0.16 0.14 0.08 0.12 0.06 ERROR (LSB) ERROR (LSB) 32 TAP 0.10 0.04 0.02 0 0.10 0.08 0.06 0.04 0.02 0 −0.02 −0.04 0 0 32 64 96 128 160 192 224 −0.02 −0.04 256 0 32 64 96 128 160 192 224 256 TAP TAP Figure 5. Rheostat Differential Non-linearity, VDD = 5.6 V Figure 6. Rheostat Integral Non-linearity, VDD = 5.6 V 120 6 100 5 5.6 V VDD = 2.6 V 60 3.3 V 40 4.0 V 3 3.3 V 2 20 0 5.0 V 4 Vw (V) Rw (W) 80 5.6 V 4.0 V 0 50 100 VDD = 2.6 V 1 150 200 0 250 0 52 104 156 TAP TAP Figure 7. Wiper Resistance at Room Temperature Figure 8. Wiper Voltage http://onsemi.com 5 208 260 CAT5271, CAT5273 TYPICAL CHARACTERISTICS 400 350 T = 90C ISB (nA) 300 T = −45C 250 T = 25C 200 150 100 2 3 4 5 6 VDD (V) Figure 9. Standby Current 102.15 0.4 102.10 102.05 0.2 D (%) R (kW) 102.00 101.95 101.90 0 101.85 101.80 −0.2 −50 −20 10 40 70 101.75 −50 100 −20 10 40 70 TEMPERATURE (C) TEMPERATURE (C) Figure 10. Change in End-to-End Resistance Figure 11. End-to-End Resistance vs. Temperature 0 100 30 −6 25 VDD = 5 V PSRR (dB) A (dB) −12 VDD = 3 V −18 −24 −30 −36 20 VDD = 5 V 15 VDD = 3 V 10 5 1 10 100 1000 0 1 10 100 f (KHz) f (KHz) Figure 12. Gain vs. Bandwidth (Tap 0x80) Figure 13. PSRR http://onsemi.com 6 1000 CAT5271, CAT5273 BASIC OPERATION The CAT5271 and CAT5273 are dual 256-position digitally controlled potentiometers. When power is first applied, the wipers assume a mid-scale position. Once the power supply is stable, the wipers may be repositioned via the I2C compatible interface. PROGRAMMING: VARIABLE RESISTOR Rheostat Mode The equation for determining the digitally programmed output resistance between W and B is (The following section refers to CAT5271. The behavior of CAT5273 is identical, but for this device terminal A of the resistor is not accessible.) The resistance between terminals A and B, RAB, has a nominal value of 50 kW or 100 kW and has 256 contact points accessed by the wiper terminal, plus the B terminal contact. Data in the 8-bit Wiper register is decoded to select one of these 256 possible settings. The wiper’s first connection is at the B terminal, corresponding to control position 0x00. Ideally this would present a 0 W between the Wiper and B, but just as with a mechanical rheostat there is a small amount of contact resistance to be considered, there is a wiper resistance comprised of the RON of the FET switch connecting the wiper output with its respective contact point. In CAT5271/ CAT5273 this ‘contact’ resistance is typically 50 W. Thus a connection setting of 0x00 yields a minimum resistance of 50 W between terminals W and B. For a 100 kW device, the second connection, or the first tap point, corresponds to 441 W (RWB = RAB/256 + RW = 390.6 + 50 W) for data 0x01. The third connection is the next tap point, is 831 W (2 x 390.6 + 50 W) for data 0x02, and so on. Figure 14 shows a simplified equivalent circuit where the last resistor string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. R WB + D R AB ) R W 256 where D is the decimal equivalent of the binary code loaded in the 8-bit Wiper register, RAB is the end-to-end resistance, and RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 100 kW and the A terminal is open circuited, the following output resistance RWB will be set for the indicated Wiper register codes: Table 8. CODES AND CORRESPONDING RWB RESISTANCE FOR RAB = 100 kW, VDD = 5 V D (Dec.) RWB (W) Output State 255 99,559 Full Scale (RAB – 1 LSB + RW) 128 50,050 Midscale 1 441 1 LSB 0 50 Zero Scale (Wiper Contact Resistance) Be aware that in the zero-scale position, the wiper resistance of 50 W is still present. Current flow between W and B in this condition should be limited to a maximum pulsed current of no more than 20 mA. Failure to heed this restriction can cause degradation or possible destruction of the internal switch contact. Similar to the mechanical potentiometer, the resistance of the digital POT between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is A RS RS Wiper Register and Decoder RS R WA(D) + 256 * D R AB ) R W 256 W RS (eq. 1) (eq. 2) For RAB = 100 kW and the B terminal open circuited, the following output resistance RWA will be set for the indicated Wiper register codes. B Figure 14. CAT5271 Equivalent Digital POT Circuit http://onsemi.com 7 CAT5271, CAT5273 VDD Table 9. CODES AND CORRESPONDING RWA RESISTANCE FOR RAB = 100 kW, VDD = 5 V D (Dec.) RWA (W) Output State 255 441 Full Scale 128 50,050 Midscale 1 99,659 1 LSB 0 100,050 Zero Scale W, A, B CAT5271 LOGIC Typical device to device resistance matching is lot dependent and may vary by up to 20%. GND Figure 16. ESD Protection Power-up Sequence Digital Input Because ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 15), it is recommended that VDD/GND be powered before applying any voltage to terminals A, B, and W. The ideal power-up sequence is: GND, VDD, digital inputs, and then VA/B/W. The order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND. LOGIC GND Power Supply Bypassing Good design practice employs compact, minimum lead length layout design. Leads should be as direct as possible. It is also recommended to bypass the power supplies with quality low ESR Ceramic chip capacitors of 0.01 mF to 0.1 mF. Low ESR 1 mF to 10 mF tantalum or electrolytic capacitors can also be applied at the supplies to suppress transient disturbances and low frequency ripple. As a further precaution digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce. W, A, B Potentiometer GND Figure 15. ESD Protection Networks VDD Terminal Voltage Operating Range VDD C3 10 mF The CAT5271/CAT5273 VDD and GND power supply define the limits for proper 3-terminal digital potentiometer operation. Signals or potentials applied to terminals A, B or the wiper must remain inside the span of VDD and GND. Signals which attempt to go outside these boundaries will be clamped by the internal forward biased diodes. + C1 0.1 mF CAT5271 GND Figure 17. Power Supply Bypassing http://onsemi.com 8 CAT5271, CAT5273 I2C BUS PROTOCOL START Condition The following defines the features of the I2C bus protocol: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. The START condition precedes all commands to the device, and is defined as a high to low transition of SDA when SCL is high. The CAT5271/CAT5273 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A low to high transition of SDA when SCL is high determines the STOP condition. All operations must end with a STOP condition. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, CAT5271/CAT5273 will be considered a slave device in all applications. DEVICE ADDRESSING Acknowledge The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The seven most significant bits of the 8-bit slave address are fixed as 0101111 for the CAT5271. For CAT5273 the first five bits are fixed as 01011, and the next two bits are pin-programmable device address bits (AD1 and AD0). The next bit (R/W) selects between the type of the instruction Read or Write. If the bit is logic high, then a Read instruction is performed. If the bit is logic low, then the Write command is executed. After the Master sends a START condition and the slave address byte, the CAT5271/CAT5273 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT5271/CAT5273 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT5271/CAT5273 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5271/CAT5273 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. WRITE OPERATION acknowledge from the Slave, the Master device transmits the data to be written into the wiper register. The CAT5271/ CAT5273 acknowledges once more and the Master generates the STOP condition. In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte. After receiving another http://onsemi.com 9 CAT5271, CAT5273 tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 18. Bus Timing Diagram SDA SCL START CONDITION STOP CONDITION Figure 19. Start/Stop Condition SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 20. Acknowledge Condition http://onsemi.com 10 CAT5271, CAT5273 INSTRUCTION AND REGISTER DESCRIPTION Slave Address Byte The remainder of the bits in the instruction byte are don’t care bits. The first byte sent to the CAT5271 from the master/processor is called the Slave Address Byte. The most significant seven bits of the slave address are a device type identifier. For the CAT5271, these bits are fixed at 0101111. For CAT5273, the first five bits are fixed as 01011, and the next two bits of the device identifier are determined by the logic levels on the AD1 and AD0 pins. The following bit (R/W) selects between a Read or a Write operation. If the bit is logic high, then a Read instruction is performed. If the bit is low, then the Write command is executed. Read Operation In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences. There is no potentiometer channel selection bit in the Read command. The addressed channel is the one that is previously selected in the write mode. If it desired to read the potentiometer wiper register values of both channels, the first potentiometer must be addressed in write mode and then change to read mode to read the first channel value. After that, the user must return the device to write mode with the second potentiometer selected and read the second potentiometer wiper register value in read mode. It is not necessary for users to issue the third data byte in write mode for subsequent read operation. Instruction Byte Write and Read instructions are respectively three and two bytes in length. The basic sequence of the two instructions is illustrated in Table 10 and 11. Write Operation In the write instruction, the second byte first bit (A0) selects between the potentiometer 1 and 2: a logic low is for the potentiometer 1, and a logic high is for potentiometer 2. The following bit (SD) is the shutdown bit. A logic high causes an open circuit at terminal A while shorting the wiper terminal W to terminal B. The “shutdown” operation does not change the contents of the wiper register. When the shutdown bit, SD, goes back to a logic low, the previous wiper position is restored. Also during shutdown, new settings can be programmed. As soon as the device is returned from shutdown, the wiper position is set according to the wiper register value. Wiper Control The CAT5271/CAT5273 contains two 8-bit Wiper Control Register (WCR). The Wiper Control Register output is decoded to select one of 256 switches along its resistor array. The contents of the WCR may be written by the host via Write instruction. The Wiper Control Registers are a volatile register that loses its contents when the CAT5271/CAT5273 is powered-down. Upon power-up, the wiper is set to midscale and may be repositioned anytime after the power has become stable. Table 10. CAT5271 Write S 0 1 0 1 1 1 1 W A A0 SD Slave Address Byte X X X X X X A D7 D6 D5 Instruction Byte D4 D3 D2 D1 D0 D2 D1 D0 A P Data Byte SDA 0 S T A R T 1 0 1 1 1 1 SD A0 R/W X X X X D7 X X A C K D6 D5 D4 D3 A S C T K O P A C K Instruction Byte Slave Address Byte Data Byte Table 11. CAT5271 READ S 0 1 0 1 1 1 1 R A D7 D6 D5 D4 Slave Address Byte SDA S T A R T 0 1 0 1 1 D3 D2 D1 D0 D2 D1 D0 A P N A C K S T O P Data Byte 1 1 R/W D7 D6 D5 D4 D3 A C K Data Byte Slave Address Byte Legend S= P= A= D= R= W= Start Stop Acknowledge Data bit Read (bit is 1 for Read instruction) Write (bit is 0 for Write instruction) A0 = SD = X= http://onsemi.com 11 Potentiometer Channel (1 or 2) Select Bit Shut Down: 0: normal operation 1: wiper is parked at B terminal and terminal A is open circuit. Don’t Care CAT5271, CAT5273 Table 12. CAT5273 Write S 0 1 0 1 1 AD1 AD0 W A A0 Slave Address Byte SD X X X X X X A D7 D6 D5 Instruction Byte D4 D3 D2 D1 D0 D2 D1 D0 A P Data Byte SDA 0 1 0 S T A R T 1 1 AD1 AD0 R/W A0 SD X X X X D7 X X A C K D6 D5 D4 D3 A S C T K O P A C K Instruction Byte Slave Address Byte Data Byte Table 13. CAT5273 READ S 0 1 0 1 1 AD1 AD0 R A D7 D6 D5 Slave Address Byte SDA 0 S T A R T 1 0 D4 D3 D2 D1 D0 D2 D1 D0 A P N A C K S T O P Data Byte 1 1 AD1 AD0 R/W D7 D6 D5 D4 D3 A C K Data Byte Slave Address Byte Legend S= P= A= D= R= W= A0 = Start Stop Acknowledge Data bit Read (bit is 1 for Read instruction) Write (bit is 0 for Write instruction) Potentiometer Channel (1 or 2) Select Bit SD = X= AD1, AD0 = Shut Down: 0: normal operation 1: wiper is parked at B terminal and terminal A is open circuit. Don’t Care Bits that must match the logic levels on pins AD1 and AD0 Table 14. ORDERING PART NUMBER Part Number Resistance CAT5271ZI−50−GT3 50 kW CAT5271ZI−00−GT3 100 kW CAT5273ZI−50−GT3 50 kW Package Lead Finish MSOP−10 NiPdAu MSOP−10 NiPdAu Shipping† 3000 / Tape & Reel 3000 / Tape & Reel 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 13. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com. 14. All packages are RoHS-compliant (Lead-free, Halogen-free). http://onsemi.com 12 CAT5271, CAT5273 PACKAGE DIMENSIONS MSOP 10, 3x3 CASE 846AE ISSUE O SYMBOL MIN NOM A E E1 MAX 1.10 A1 0.00 0.05 0.15 A2 0.75 0.85 0.95 b 0.17 0.27 c 0.13 D 2.90 3.00 3.10 E 4.75 4.90 5.05 E1 2.90 3.00 3.10 0.50 BSC e L 0.40 L1 0.60 0.80 0.95 REF L2 θ 0.23 0.25 BSC 0º 8º DETAIL A TOP VIEW D A A2 A1 c e END VIEW b q SIDE VIEW L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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