Product Folder Order Now Support & Community Tools & Software Technical Documents Reference Design CSD87503Q3E SLPS661 – SEPTEMBER 2017 CSD87503Q3E 30-V N-Channel NexFET™ Power MOSFETs 1 Features • • • • • • • • 1 Dual N-Ch Common Source MOSFETs Optimized for 5-V Gate Drive Low-Thermal Resistance Low Qg and Qgd Lead-Free Terminal Plating RoHS Compliant Halogen Free SON 3.3-mm × 3.3-mm Plastic Package 2 Applications • • • USB Type-C/PD VBus Protection Battery Protection Load Switch Product Summary TA = 25°C VALUE VDS Drain-to-Source Voltage Qg Gate Charge Total (4.5 V) Qgd Gate Charge Gate-to-Drain RDD(on) Drain-to-Drain On-Resistance VGS(th) Threshold Voltage UNIT 30 V 13.4 nC 5.8 nC VGS = 4.5 V 17.3 VGS = 10 V 13.5 mΩ 1.7 V Device Information(1) DEVICE QTY MEDIA PACKAGE SHIP CSD87503Q3E 2500 13-Inch Reel CSD87503Q3ET 250 7-Inch Reel SON 3.30-mm × 3.30-mm Plastic Package Tape and Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. 3 Description Absolute Maximum Ratings The CSD87503Q3E is a 30-V, 13.5-mΩ, common source, dual N-channel device designed for USB Type-C/PD and battery protection. This SON 3.3 × 3.3 mm device has low drain-to-drain on-resistance that minimizes losses and offers low component count for space constrained applications. Top View TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 30 V VGS Gate-to-Source Voltage ±20 V ID1, Continuous Drain-to-Drain Current (Package Limited) 10 A Continuous Drain-to-Source Current (Package Limited) 1.5 A D2 IDS Pulsed Drain-to-Drain Current,(1) 89 A PD Power Dissipation(2) 2.6 W PD Power Dissipation, TC = 25°C 15.6 W TJ , Tstg Operating Junction, Storage Temperature –55 to 150 °C ID1, D2M (1) Max RθJC = 8°C/W, pulse duration ≤ 100 μs, duty cycle ≤ 1%. (2) Typical RθJA = 50°C/W when mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 0.06-in (1.52-mm) thick FR4 PCB. RDD(on) vs VGS Circuit Image Gate 1 PIN 1 Gate 2 PIN 3 Drain 1 Pins 7, 8 Drain 2 Pins 5, 6 Common Common Source Source Pin 2 Pin 4 RDD(on) - On-State Resistance (m:) 40 TC = 25°C, I D1D2 = 6 A TC = 125°C, I D1D2 = 6 A 35 30 25 20 15 10 5 0 0 2 4 6 8 10 12 14 VG1, VG2 - Gate Voltage (V) 16 18 20 D007 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD87503Q3E SLPS661 – SEPTEMBER 2017 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 1 1 1 2 3 7 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Receiving Notification of Documentation Updates.... Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 Q3 Package Dimensions .......................................... 8 7.2 Recommended PCB Pattern..................................... 9 7.3 Recommended Stencil Opening ............................... 9 Device and Documentation Support.................... 7 4 Revision History 2 DATE REVISION NOTES September 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD87503Q3E CSD87503Q3E www.ti.com 5 SLPS661 – SEPTEMBER 2017 Specifications 5.1 Electrical Characteristics TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage (1) VGS = 0 V, ID = 250 μA IDSS Drain-to-source leakage current (1) VGS = 0 V, VDS = 24 V 1 μA IGSS Gate-to-source leakage current (1) VDS = 0 V, VGS = 20 V 100 nA V VGS(th) Gate-to-source threshold voltage RDD(on) Drain-to-drain on-resistance gfs Transconductance (1) VDS = VGS, ID = 250 μA 30 1.3 V 1.7 2.1 VGS = 4.5 V, ID1D2 = 6 A 17.3 21.9 VGS = 10 V, ID1D2 = 6 A 13.5 16.9 VDS = 3 V, ID1D2 = 6 A mΩ 24 S DYNAMIC CHARACTERISTICS CISS Input capacitance COSS Output capacitance CRSS Rg Qg 782 1020 pF 157 204 pF Reverse transfer capacitance 149 194 pF Series gate resistance (1) 1.5 3.0 Ω Gate charge total (4.5 V) 13.4 17.4 Gate charge total (10 V) 32.9 42.8 VGS = 0 V, VD1D2 = 15 V, ƒ = 1 MHz Qgd Gate charge gate-to-drain Qgs Gate charge gate-to-source VD1D2 = 15 V, ID1D2 = 6 A Qg(th) Gate charge at Vth QOSS Output charge td(on) nC 5.8 nC 4.8 nC 1.0 nC 4.3 nC Turnon delay time 10 ns tr Rise time 40 ns td(off) Turnoff delay time 25 ns tf Fall time 8 ns VD1D2 = 15 V, VGS = 0 V VD1D2 = 15 V, VGS = 10 V, ID1D2 = 6 A, RG = 0 Ω DIODE CHARACTERISTICS VSD Diode forward voltage (1) Qrr Reverse recovery charge (1) trr Reverse recovery time (1) (1) ID = 0.5 A, VGS = 0 V 0.75 VDS = 15 V, IF = 6 A, di/dt = 300 A/μs 0.95 V 9.2 nC 14 ns Parameter measured on both MOSFETs individually. Table values are for a single FET. 5.2 Thermal Information TA = 25°C (unless otherwise stated) THERMAL METRIC RθJC RθJA (1) (2) MIN Junction-to-case thermal resistance (1) Junction-to-ambient thermal resistance (1) (2) 2 TYP MAX UNIT 8 °C/W 60 °C/W 2 RθJC is determined with the device mounted on a 1-in (6.45-cm ), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD87503Q3E 3 CSD87503Q3E SLPS661 – SEPTEMBER 2017 www.ti.com Max RθJA = 60°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu. Max RθJA = 185°C/W when mounted on a minimum pad area of 2-oz (0.071-mm) thick Cu. 5.3 Typical MOSFET Characteristics TA = 25°C (unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD87503Q3E CSD87503Q3E www.ti.com SLPS661 – SEPTEMBER 2017 Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise stated) 20 VG1, VG2 = 4.5 V VG1, VG2 = 6 V VG1, VG2 = 10 V 70 ID1D2 - Drain-to-Drain Current (A) ID1D2 - Drain-to-Drain Current (A) 80 60 50 40 30 20 10 TC = 125°C TC = 25°C TC = -55°C 18 16 14 12 10 8 6 4 2 0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VD1D2 - Drain-to-Drain Voltage (V) 1.8 0 2 0.5 1 D002 1.5 2 2.5 3 VG1, VG2 - Gate Voltage (V) 3.5 4 D003 VD1D2 = 5 V Note: Measurement taken with both gates tied together Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 10000 Ciss = CG1D1+CG1S1+CG2S2+CG2D2 Coss = CG1D1+1/(1/CD1S1+1/(CG1S1+CG2S2+CD2S2)) Crss = CG1D1+1/(1/CD1S1+1/(CG1S1+CG2S2)) 9 8 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 1000 100 2 1 0 10 0 5 10 15 20 25 Qg - Gate Charge (nC) ID1D2 = 6 A 30 35 0 3 6 D004 30 D005 Figure 5. Capacitance 40 RDD(on) - On-State Resistance (m:) 2.1 VGS(th) - Threshold Voltage (V) 27 VD1D2 = 15 V Figure 4. Gate Charge 1.9 1.7 1.5 1.3 1.1 0.9 -75 9 12 15 18 21 24 VD1D2 - Drain-to-Drain Voltage (V) TC = 25°C, I D1D2 = 6 A TC = 125°C, I D1D2 = 6 A 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 175 0 2 D006 4 6 8 10 12 14 VG1, VG2 - Gate Voltage (V) 16 18 20 D007 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD87503Q3E 5 CSD87503Q3E SLPS661 – SEPTEMBER 2017 www.ti.com Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise stated) 10 1.8 VG1, VG2 = 4.5 V VG1, VG2 = 10 V 1.6 1.4 1.2 1 0.8 0.6 0.4 -75 TC = 25qC TC = 125qC ID1D2 - Drain-To-Drain Current (A) Normalized On-State Resistance 2 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (qC) 125 150 0 175 0.1 D008 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VD1D2 - Drain-To-Drain Voltage (V) 0.9 1 D009 ID1D2 = 6 A VD1D2 = 15 V Note: Measurement taken with both gates tied together Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage 100 DC 10 ms 1 ms 100 µs 10 µs IAV - Peak Avalanche Current (A) ID1D2 - Drain-To-Drain Current (A) 1000 100 10 1 0.1 0.1 1 10 VD1D2 - Drain-To-Drain Voltage (V) 100 TC = 25q C TC = 125q C 10 1 0.01 0.1 TAV - Time in Avalanche (ms) D010 1 D011 Single pulse, max RθJC = 8°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDD - Drain-to-Drain Current (A) 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (°C) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD87503Q3E CSD87503Q3E www.ti.com SLPS661 – SEPTEMBER 2017 6 Device and Documentation Support 6.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 6.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 6.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD87503Q3E 7 CSD87503Q3E SLPS661 – SEPTEMBER 2017 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q3 Package Dimensions 3.4 3.2 B A PIN 1 INDEX AREA 3.4 3.2 C 1 MAX SEATING PLANE 0.08 C 2X 2.09 0.1 0.53 4X 0.33 (0.2) TYP 0.05 0.00 PKG 2X EXPOSED THERMAL PAD 4 5 10 2X 1.95 2X 1.175 0.1 SYMM 8X 9 0.1 0.05 8 1 0.35 0.25 C A B C 6X 0.65 4X PIN 1 ID (OPTIONAL) 0.53 0.33 4223409/A 12/2016 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance. Table 1. Pin Configuration POSITION 8 DESIGNATION Pin 1 Gate 1 Pin 2 Common Source Pin 3 Gate 2 Pin 4 Common Source Pins 5, 6 Drain 2 Pins 7, 8 Drain 1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD87503Q3E CSD87503Q3E www.ti.com SLPS661 – SEPTEMBER 2017 7.2 Recommended PCB Pattern (0.325) TYP (0.675) TYP SOLDER MASK OPENING TYP 4X (0.63) (0.175) PADS 9 & 10 4X (0.63) 1 8X (0.3) 8 9 (0.763) TYP SYMM 6X (0.65) 10 2X (1.18) 5 4 (R0.05) TYP PKG ( 0.2) VIA TYP 0.05 MIN TYP 2X (2.09) METAL UNDER SOLDER MASK TYP (3.07) 1. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB Attachment (SLUA271). 2. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged, or tented. 3. This drawing is subject to change without notice. 7.3 Recommended Stencil Opening SOLDER MASK OPENING TYP METAL UNDER SOLDER MASK TYP PKG (0.175) 4X (0.545) 4X (0.63) 1 9 8X (0.3) 8 2X (0.763) SYMM 6X (0.65) 2X (1.06) 10 5 4 (R0.05) TYP 2X (1.86) (1.535) EXPOSED METAL TYP (1.578) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PADS 9 & 10 80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X 1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 2. This drawing is subject to change without notice. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD87503Q3E 9 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD87503Q3E ACTIVE VSON DTD 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 150 87503E CSD87503Q3ET ACTIVE VSON DTD 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 150 87503E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. 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