ALSC AS4C256K16F0-50TI 5v 256k x 16 cmos dram (fast page mode) Datasheet

AS4C256K16FO
®
5V 256K X 16 CMOS DRAM (Fast Page Mode)
Features
• Organization: 262,144 words × 16 bits
• High speed
- 25/30/35/50 ns RAS access time
- 12/16/18/25 ns column address access time
- 7/10/10/10 ns CAS access time
• Low power consumption
- Active: 770 mW max (ASAS4C256K16FO-50)
- Standby: 5.5 mW max, CMOS I/O
• Fast page mode
• AS4C256K16FO-50 timings are also valid for
• Refresh
- 512 refresh cycles, 8 ms refresh interval
- RAS-only or CAS-before-RAS refresh or self-refresh
- Self-refresh option is available for new generation
device only. Contact Alliance for more information.
• Read-modify-write
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil, 40-pin SOJ
- 400 mil, 40/44-pin TSOP II
• Single 5V power supply/built-in Vbb generator
• Latch-up current > 200 mA
AS4C256K16FO-60.
Pin arrangement
Pin designation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
TSOP II
44
1
43
2
42
3
41
4
40
5
39
6
38
7
37
8
36
9
35
10
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
13
14
15
16
17
18
19
20
21
22
ASC256K16FO
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
ASC256K16FO
SOJ
Pin(s)
Description
A0 to A8
Address inputs
RAS
Row address strobe
I/O0 to I/O15
Input/output
OE
Output enable
UCAS
Column address strobe, upper byte
LCAS
Column address strobe, lower byte
WE
Read/write control
VCC
Power (+5V ± 10%)
GND
Ground
Selection guide
Symbol
–25
–30
–35
–50
Unit
Maximum RAS access time
tRAC
25
30
35
50
ns
Maximum column address
access time
tCAA
12
16
18
25
ns
Maximum CAS access time
tCAC
7
10
10
10
ns
Maximum output enable (OE)
access time
tOEA
7
10
10
10
ns
Minimum read or write cycle
time
tRC
40
65
70
85
ns
Minimum EDO page mode
cycle time
tPC
12
12
14
25
ns
Maximum operating current
ICC1
200
180
160
140
mA
Maximum CMOS standby
current
ICC2
2.0
2.0
2.0
2.0
mA
4/11/01; V.0.9.1
Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.
AS4C256K16FO
®
Functional description
The AS4C256K16FO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) device organized as
262,144 words × 16 bits. The AS4C256K16FO is fabricated with advanced CMOS technology and designed with innovative
design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.
The AS4C256K16FO features a high-speed page mode operation in which high speed read, write and read-write are performed
on any of the 512 × 16 bits defined by the column address. The asynchronous column address uses an extremely short row
address capture time to ease the system-level timing constraints associated with multiplexed addressing. Output is tri-stated by a
column address strobe (CAS) which acts as an output enable independent of RAS. Very fast CAS to output access time eases
system design.
Refresh on the 512 address combinations of A0–A8 during an 8 ms period is accomplished by performing any of the following:
•
•
•
•
•
RAS-only refresh cycles
Hidden refresh cycles
CAS-before-RAS refresh cycles
Normal read or write cycles
Self-refresh cycles.*
The AS4C256K16FO is available in standard 40-pin plastic SOJ and 44-pin TSOP II packages compatible with widely available
automated testing and insertion equipment. System level features include single power supply of 5V ± 10% tolerance and direct
interface with TTL logic families.
Refresh
controller
Logic block diagram
RAS
UCAS
LCAS
WE
RAS clock
generator
CAS clock
generator
A0
A1
A2
A3
A4
A5
A6
A7
A8
Sense amp
I/O0 to I/O15
OE
Row decoder
GND
Data
I/O
buffer
Column decoder
Addreess buffers
VCC
512×512×16
array
(4,194,304)
Substrate
bias generator
WE clock
generator
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Symbol
Min
Typ
Max
Unit
VCC
4.5
5.0
5.5
V
GND
0.0
0.0
0.0
V
VIH
2.4
–
VCC + 1
V
VIL
–1.0
–
0.8
V
* Self-refresh option is available for new generation device only. Contact Alliance for more information.
4/11/01; V.0.9.1
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P. 2 of 25
AS4C256K16FO
®
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
VIN
–1.0
+7.0
V
Output voltage
VOUT
–1.0
+7.0
V
Power supply voltage
VCC
–1.0
+7.0
V
Operating temperature
TOPR
0
+70
°C
Storage temperature (plastic)
TSTG
–55
+150
°C
Soldering temperature × time
TSOLDER
–
260 × 10
°C × sec
PD
–
1
W
IOUT
–
50
mA
200
–
mA
Input voltage
Power dissipation
Short circuit output current
Latch-up current
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
DC electrical characteristics
Parameter
Symbol
Input leakage
IIL
current
Output leakage
IOL
current
Operating
power supply
ICC1
current
TTL standby
power supply
ICC2
current
Average power
supply current,
ICC3
RAS refresh
mode
Fast page mode
average power
ICC4
supply current
CMOS standby
power supply
ICC5
current
CAS-before-RAS
refresh power
ICC6
supply current
VOH
Output voltage
VOL
Self refresh
current
4/11/01; V.0.9.1
ICC7
(VCC = 5 ± 10%, GND = 0V, Ta = 0° C to +70° C)
–25
Min Max
–30
Min Max
–35
Min Max
–50
Min Max Unit Note
–10
10
–10
10
–10
10
–10
10
µA
–10
10
–10
10
–10
10
–10
10
µA
RAS, UCAS, LCAS, address
cycling; tRC = min
–
200
–
180
–
160
–
140
mA
RAS = UCAS = LCAS = VIH
–
2.0
–
2.0
–
2.0
–
2.0
mA
RAS cycling,
UCAS = LCAS = VIH,
tRC = min
–
120
–
200
–
190
–
140
mA
1
RAS = UCAS = LCAS = VIL,
address cycling: tSC = min
–
130
–
190
–
180
–
70
mA
1,2
RAS = UCAS = LCAS =
VCC – 0.2V
–
0.60
–
1.0
–
1.0
–
1.0
mA
RAS, UCAS, LCAS, cycling;
tRC = min
–
120
–
200
–
190
–
140
mA
–
0.4
2.4
–
–
0.4
2.4
–
–
0.4
2.4
–
–
0.4
V
V
2.0
–
2.0
–
2.0
–
2.0
mA
Test conditions
0V ≤ VIN ≤ + 5.5V
pins not under test = 0V
DOUT disabled,
0V ≤ VOUT ≤ + 5.5V
IOUT = – 5.0 mA
2.4
IOUT = 4.2 mA
–
RAS = UCAS = LCAS = VIL, WE
= OE = A0 – A8 = VCC –0.2V,
–
DQ0 – DQ15 = VCC – 0.2V, 0.2V
are open
Alliance Semiconductor
1,2
1
P. 3 of 25
AS4C256K16FO
®
AC parameters common to all waveforms
(VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C)
–25
Standard
Symbol
Parameter
–30
–35
–50
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
tRC
Random read or write cycle time
45
–
65
–
70
–
85
–
ns
tRP
RAS precharge time
15
–
25
–
25
–
25
–
ns
tRAS
RAS pulse width
25
75K
30
75K
35
75K
50
75K
ns
tCAS
CAS pulse width
4
–
5
–
6
–
10
–
ns
tRCD
RAS to CAS delay time
10
17
15
20
16
24
15
35
ns
6
tRAD
RAS to column address delay time
8
13
10
14
11
17
15
25
ns
7
tRSH(R)
CAS to RAS hold time (read cycle)
7
–
10
–
10
–
10
–
ns
tCSH
RAS to CAS hold time
20
–
30
–
35
–
50
–
ns
tCRP
CAS to RAS precharge time
5
–
5
–
5
–
5
–
ns
tASR
Row address setup time
0
–
0
–
0
–
0
–
ns
tRAH
Row address hold time
5
–
5
–
6
–
9
–
ns
1.5
50
1.5
50
1.5
50
3
50
ns
4,5
tT
Transition time (rise and fall)
tREF
Refresh period
–
8
–
8
–
8
–
8
ms
3
tCLZ
CAS to output in low Z
0
–
0
–
0
–
3
–
ns
8
Read cycle
(VCC = 5V±10%, GND = 0V, Ta = 0° C to + 70° C)
–25
Standard
Symbol
Parameter
–30
–35
–50
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
tRAC
Access time from RAS
–
25
–
30
–
35
–
50
ns
6
tCAC
Access time from CAS
–
7
–
10
–
10
–
10
ns
6,13
tAA
Access time from address
–
12
–
16
–
18
–
25
ns
7,13
tAR(R)
Column add hold from RAS
19
–
26
–
28
–
30
–
ns
tRCS
Read command setup time
0
–
0
–
0
–
0
–
ns
tRCH
Read command hold time to CAS
0
–
0
–
0
–
0
–
ns
9
tRRH
Read command hold time to RAS
0
–
0
–
0
–
0
–
ns
9
tRAL
Column address to RAS Lead time
12
–
16
–
18
–
25
–
ns
tCPN
CAS precharge time
4
–
3
–
4
–
5
–
ns
tOFF
Output buffer turn-off time
0
6
0
8
0
8
0
8
ns
4/11/01; V.0.9.1
Alliance Semiconductor
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AS4C256K16FO
®
Write cycle
(VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C)
–25
Standard
Symbol
Parameter
–30
–35
–50
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
tASC
Column address setup time
0
–
0
–
0
–
0
–
ns
tCAH
Column address hold time
5
–
5
–
5
–
9
–
ns
tAWR
Column address hold time to RAS
19
–
26
–
28
–
30
–
ns
tWCS
Write command setup time
0
–
0
–
0
–
0
–
ns
11
tWCH
Write command hold time
5
–
5
–
5
–
9
–
ns
11
tWCR
Write command hold time to RAS
19
–
26
–
28
–
30
–
ns
tWP
Write command pulse width
5
–
5
–
5
–
9
–
ns
tRWL
Write command to RAS lead time
7
–
10
–
11
–
12
–
ns
tCWL
Write command to CAS lead time
5
–
10
–
11
–
12
–
ns
tDS
Data-in setup time
0
–
0
–
0
–
0
–
ns
12
tDH
Data-in hold time
5
–
5
–
5
–
9
–
ns
12
tDHR
Data-in hold time to RAS
19
–
26
–
28
–
30
–
ns
(VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C)
Read-modify-write cycle
–25
Standard
Symbol
Parameter
–30
–35
–50
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
tRWC
Read-write cycle time
100
–
100
–
105
–
120
–
ns
tRWD
RAS to WE delay time
34
–
50
–
54
–
60
–
ns
11
tCWD
CAS to WE delay time
17
–
26
–
28
–
30
–
ns
11
tAWD
Column address to WE delay time
21
–
32
–
35
–
40
–
ns
11
tRSH(W) CAS to RAS hold time (write)
7
–
10
–
10
–
12
–
ns
tCAS(W) CAS pulse width (write)
15
–
15
–
15
–
15
–
ns
Fast page mode cycle
(VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C)
–25
Standard
Symbol
Parameter
–30
–35
–50
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
tPC
Read or write cycle time
8
–
12
–
14
–
25
–
ns
14
tCAP
Access time from CAS precharge
–
14
–
19
–
21
–
23
ns
13
tCP
CAS precharge time
3
–
3
–
4
–
5
–
ns
tPCM
Fast page mode RMW cycle
56
–
56
–
58
–
60
–
ns
tCRW
Page mode CAS pulse width (RMW)
44
–
44
–
46
–
50
–
ns
tRASP
RAS pulse width
25
75K
30
75K
35
75K
50
75K
ns
4/11/01; V.0.9.1
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P. 5 of 25
AS4C256K16FO
®
Refresh cycle
(VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C)
–25
Min
Max
10
–
7
–
0
–
Standard
Symbol
Parameter
tCSR
CAS setup time (CAS-before-RAS)
tCHR
CAS hold time (CAS-before-RAS)
tRPC
RAS precharge to CAS hold time
CAS precharge time
tCPT
(CAS-before-RAS counter test)
8
Output enable
Standard
Symbol
tROH
tOEA
tOED
tOEZ
tOEH
8
–
–35
Min Max
10
–
8
–
0
–
8
–
–50
Min Max
10
–
10
–
0
–
8
–
Unit
ns
ns
ns
Notes
3
3
ns
(VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C)
Parameter
RAS hold time referenced to OE
OE access time
OE to data delay
Output buffer turnoff delay from OE
OE command hold time
Self refresh cycle
–
–30
Min Max
10
–
7
–
0
–
–25
Min Max
5
–
–
8
5
–
–
6
5
–
–30
Min Max
5
–
–
10
5
–
–
8
8
–
–35
Min Max
5
–
–
10
5
–
–
8
8
–
–50
Min Max
5
–
–
10
8
–
–
8
8
–
Unit
ns
ns
ns
ns
ns
Notes
8
(VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C)
–25
Standard
Symbol
Parameter
Min
Max
tRASS RAS pulse width (CBR self refresh)
100K
–
tRPS
RAS precharge time (CBR self refresh) 85
–
tCHS CAS hold time (CBR self refresh)
30
–
–30
–35
Min Max Min Max
100K
–
100K
–
85
–
85
–
30
–
30
–
–50
Min Max
100K –
85
–
30
–
Unit
ns
ns
ns
Notes
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ICC1, ICC3, ICC4, and ICC6 depend on cycle rate.
ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended
periods of bias without clocks (greater than 8 ms).
AC characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) ≥ GND and VIH (max) ≤
VCC.
VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA.
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either tRCH or tRRH must be satisfied for a read cycle.
tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥
tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD
≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If
neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
Access time is determined by the longest of tCAA or tCAC or tCAP.
tASC ≥ tCP to achieve tPC (min) and tCAP (max) values.
These parameters are sampled, but not 100% tested.
4/11/01; V.0.9.1
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AS4C256K16FO
®
Key to switching waveforms
Rising input
Undefined/don’t care
Falling input
Read cycle waveform
tRC
tRAS
tRCD
tRSH
tRP
RAS
tCSH
tCRP
tASC
tCAS
tRCS
tCAH
UCAS, LCAS
tAR
tRAD
tRAL
tRAH
tASR
Address
Row Address
Col Address
tRRH
tRCH
WE
tROH
OE
tOEZ
tRAC
tAA
tCLZ
I/O
4/11/01; V.0.9.1
tOEA
tCAC
tOFF
Data Out
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AS4C256K16FO
®
Upper byte read waveform
tRC
tRAS
tRP
RAS
tRCD
tRSH
tCSH
tCRP
tCRP
tCAS
UCAS
tCRP
LCAS
tRAH
tRAD
tRAL
tASC
tASR
tCAH
Row
Address
Column
tRCH
tRRH
tRCS
WE
tROH
OE
tOEA
tRAC
tOEZ
tAA
tCAC
tCLZ
tOFF
Upper I/O
Data Out
Lower I/O
Lower byte read waveform
tRC
tRAS
tRP
RAS
tRCD
tRSH
tCSH
tCRP
tCRP
tCAS
LCAS
tCRP
UCAS
tASC
tRAH
tRAD
tRAL
tASR
Address
tCAH
Row
Column
tRCH
tRRH
tRCS
WE
tROH
OE
Upper I/O
tOEA
tRAC
tAA
tCLZ
tOEZ
tCAC
4/11/01; V.0.9.1
tOFF
Data Out
Lower I/O
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AS4C256K16FO
®
Early write waveform
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS
tRCD
UCAS, LCAS
tAWR
tRAD
tASR
Address
tRAL
tASC
tCAH
Col Address
tRAH
Row Address
tWCR
tCWL
tRWL
tWP
tWCS
tWCH
WE
OE
tDHR
tDS
I/O
4/11/01; V.0.9.1
tDH
Data In
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AS4C256K16FO
®
Upper byte early write waveform
tRC
tRAS
tRP
RAS
tASR
Address
tRAD
tAWR
tRAL
Column Address
tRAH
Row Address
tCAH
tRSH
tASC
tRCD
tCSH
tCAS
tCRP
tCRP
UCAS
tCRP
tRPC
LCAS
tCWL
tWCS
tWCH
tRWL
tWCR
tWP
WE
OE
tDHR
Upper I/O
tDS
tDH
Data In
Lower I/O
4/11/01; V.0.9.1
Alliance Semiconductor
P. 10 of 25
AS4C256K16FO
®
Lower byte early write waveform
tRC
tRAS
tRP
RAS
tAWR
tRAD
tASR
tRAL
tRAH
Address
Row Address
tCRP
Column Address
tRPC
UCAS
tASC
tRCD
tCAH
tCAS
tCSH
tRSH
tCRP
LCAS
tWCR
tCRP
tRWL
tCWL
tWCS
tWCH
tWP
WE
OE
Upper I/O
tDHR
tDS
tDH
Data In
Lower I/O
Write waveform
tRAS
tRC
tRP
RAS
tCSH
tCRP
tRSH
tCAS
tRCD
UCAS,
LCAS
tRAL
tAWR
tRAD
tASR
Address
tASC
tCAH
Col Address
tRAH
Row Address
tWCR
tRWL
tCWL
tWP
WE
tOEH
OE
tDHR
tOED
I/O
4/11/01; V.0.9.1
tDS
tDH
Data In
Alliance Semiconductor
P. 11 of 25
AS4C256K16FO
®
Upper byte write waveform
tRC
tRAS
tRP
RAS
tRAD
tRAL
tAWR
tASR
Address
tRAH
Row Address
Column Address
tCSH
tRCD
tCRP
tRSH
tCAH
tCAS
tASC
tCRP
UCAS
tCRP
tRPC
LCAS
tCWL
tRWL
tWP
WE
tOEH
OE
tDS
Upper I/O
tDH
Data In
tOED
Lower I/O
4/11/01; V.0.9.1
Alliance Semiconductor
P. 12 of 25
AS4C256K16FO
®
Lower byte write waveform
tRC
tRAS
tRP
RAS
tRAD
tAWR
tASR
tRAL
tRAH
Address
Row Address
Column Address
tCAH
tRCD
tCAS
tCSH
tCRP
tRSH
tACS
tCRP
LCAS
tCRP
tRPC
UCAS
tCWL
tRWL
tWP
WE
tOEH
OE
Upper I/O
tDH
tDS
Lower I/O
Data In
Read-modify-write waveform
tRWC
tRAS
RAS
tCRP
tRP
tCAS
tRSH
tRCD
tCSH
UCAS,
LCAS
tAR
tRAL
tRAD
tRAH
tASR
Address
tASC
Row Address
tCAH
Col Address
tRWD
tRWL
tCWL
tWP
tAWD
tRCS
WE
tCWD
tOEA
tOEZ
tOED
OE
tRAC
I/O
4/11/01; V.0.9.1
tAA
tCAC
tCLZ
Data Out
Alliance Semiconductor
tDS
tDH
Data In
P. 13 of 25
AS4C256K16FO
®
Upper byte read-modify-write waveform
tRWC
tRAS
tRP
RAS
tCSH
tRCD
tCAS
tRSH
tCRP
UCAS
tCRP
tCRP
tRPC
LCAS
tASR
tRAD
tACS
tRAH
Address
tRAL
tCAH
Column Address
tRWD
tAWD
Row
tCWL
tRWL
tCWD
tRCS
WE
tWP
tOEA
OE
tDS
tOED
Upper Input
tCLZ
tCAC
tAA
tRAC
Data In
tOEZ
Upper Output
Data Out
tOED
Lower Input
Lower Output
Data Out
4/11/01; V.0.9.1
Alliance Semiconductor
P. 14 of 25
AS4C256K16FO
®
Lower byte read-modify write waveform
tRWC
tRAS
tRP
RAS
tCRP
tRPC
UCAS
tCSH
tCAS
tRSH
tRCD
tCRP
tCRP
LCAS
tRAD
tASR
tRAL
tCAH
tACS
tRAH
Column Address
Address
tRWD
Row
tCWL
tRWL
tWP
tAWD
tRCS
tCWD
WE
tOEA
OE
Upper Input
Upper Output
Data Out
tOED
tDS
Lower Input
tRAC
tAA
tCAC
tCLZ
Data In
tOEZ
Lower Output
Data Out
4/11/01; V.0.9.1
Alliance Semiconductor
P. 15 of 25
AS4C256K16FO
®
Fast page mode read waveform
tRASP
tRP
RAS
tCSH
tCRP
tRCD
tCAS
tRSH
tPC
tCP
UCAS,
LCAS
tAR
tRAL
tRAD
tASC
tRAH
tASR
Row
Address
Col Address
tRCS
tCAH
Col Address
Col Address
tRCS
tRCH
tRRH
tRCH
WE
tOEA
tOEA
OE
tRAC
tOEZ
tCLZ
tCAC
tAA
Data Out
I/O
tOFF
tCAP
Data Out
Data Out
Fast page mode byte read waveform
tRASP
tRP
RAS
tCSH
UCAS
tRCD
tCRP
tRSH
tCAS
tCAS
tPC
tCP
tPC
tCRP
tCAS
Address
tCAH
tRAH
tRAD
Row
tRCS
tRAL
tASC
tASC
Column 1
tCAH
Column 2
tASC
Column n
tRCS
tRCH
tRCS
tRCH
tRPC
tCP
LCAS
tASR
tCRP
tCAS
tCAH
WE
tOEA
tOEA
tOEA
OE
tAA
tCAP
Upper I/O
tRAC
tCAC
tCLZ
tAA
tCAC
tCLZ
tOFF
tOEZ
Data Out 2
tAA
tCAP
tCAC
tCLZ
tOFF
tOEZ
tOFF
tOEZ
Lower I/O
Data Out 1
4/11/01; V.0.9.1
Alliance Semiconductor
Data Out n
P. 16 of 25
AS4C256K16FO
®
Fast page mode early write waveform
tRASP
tRAH
tRWL
RAS
tCRP
tRCD
tPC
tCSH
tASC
tWCS
tCAS
UCAS,
LCAS
tRAL
tAR
tASR
tRAD
Row address
Address
tCAH
tRSH
tCP
Col address
Col Address
Col Address
tCWL
tWP
tOEH
tWCH
WE
OE
tHDR
tOED
tDH
tDS
Data In
I/O
Data In
Data In
Fast page mode byte early write waveform
tRASP
RAS
tRP
tCSH
tCRP
tRCD
tRSH
tCAS
tCAS
tCRP
UCAS
tCP
tPC
tCRP
tCP
tPC
tCAS
tRPC
LCAS
tRAD
tRAH
tASR
Address
tCAH
tASC
Column 1
Row
tASC
Column 2
tRAL
tCAH
tCAH
tASC
Column n
tRWL
tWCH
tWCS
tWCH
tWP
tCWL
tWCH
tWCS
tWP
tWCS
tWP
tCWL
tCWL
WE
OE
tDS
Upper I/O
tDH
Data In 2
tDS
tDH
tDS
tDH
Lower I/O
Data In 1
4/11/01; V.0.9.1
Alliance Semiconductor
Data In n
P. 17 of 25
AS4C256K16FO
®
Fast page mode read-modify-write waveform
tRASP
tRP
tCP
tCRP
RAS
tPCM
tCSH
tRCD
UCAS,
LCAS
tCAS
tRAD
tASR
Address
tRAH
Row Ad
tCAH
Col Ad
Col Ad
tCWL
tCWD
tRWD
tCWD
tAWD
tRCS
tRAL
tCAH
Col Address
tCAH
tCWD
tAWD
tRWL
tCWL
tWP
WE
tOEA
tOEZ
tOED
tOEA
OE
tAA
tDH
tRAC
tCLZ
tCAC
Data In
Data Out
I/O
tCAP
tCLZ
tCAC
tDS
tCLZ
tCAC
tDS
Data In
Data Out
Data In
Data Out
CAS-before-RAS refresh waveform
(WE = VIH)
tRC
tRP
tRAS
RAS
tRPC
tCHR
tCPN
tCSR
UCAS,
LCAS
tOFF
I/O
RAS-only refresh waveform
(WE = OE = VIH or VIL)
tRC
tRAS
tRP
RAS
tCRP
UCAS,
LCAS
Address
4/11/01; V.0.9.1
tARS
tRPC
tRAH
Row Address
Alliance Semiconductor
P. 18 of 25
AS4C256K16FO
®
Fast page mode byte read-modify-write waveform
tRASP
tRP
RAS
tCSH
tRCD
tCRP
tRSH
tCAS
tCAS
tCRP
UCAS
tPCM
tCP
tCP
tCAS
LCAS
tRAD
tRAH
tASR
Address
tRCS
tAWD
tASC
tASC
C1
R
tRAL
tCAH
tCAH
tCWD
tRWD
tAWD
tASC
Cn
C2
tAWD
tCAH
tCWD
tCWL
tWP
tWP
tRWL
tCWD
tCWL
tWP
tCWL
WE
tOEA
tOEA
tOEA
OE
tDH
tOED
tDS
tDH
tOED
tDS
Upper Input
tRAC
Data In 1
tAA
tCAC
Data In n
tCAP
tAA
tOEZ
tOEZ
tCAC
tCLZ
tCLZ
Upper Output
Data Out 1
tDH
tOED
Data Out n
tDS
Lower Input
Data In 2
tCAP
tAA
tCAC
tOEZ
tCLZ
Lower Output
Data Out 2
4/11/01; V.0.9.1
Alliance Semiconductor
P. 19 of 25
AS4C256K16FO
®
Hidden refresh waveform (read)
tRC
tRC
tRAS
tPR
tRAS
tPR
RAS
tCRP
tRCD
tCHR
tRSH
tCRP
CAS
tAR
tRAD
tRAH
tASR
tASC
Col Address
Row
Address
tRCS
tRRH
WE
tOEA
OE
tRAC
tAA
tCAC
tCLZ
tOFF
tOEZ
Data Out
I/O
Hidden refresh waveform (write)
tRC
tRAS
tRP
RAS
tCRP
tRCD
UCAS,
LCAS
tRSH
tAR
tRAD
tASR
tRAH
Address
tRAL
tASC
tCAH
Row Address
Col Address
tRWL
tWCR
tWCS
tWP
tWCH
WE
tDS
I/O
tDH
tDHR
Data In
OE
4/11/01; V.0.9.1
Alliance Semiconductor
P. 20 of 25
AS4C256K16FO
®
CAS before RAS refresh counter test waveform
tRAS
tRSH
tRP
RAS
tCSR
tCHR
tCPT
tCAS
UCAS, LCAS
tRAL
tCAH
Address
Col Address
tAA
tCAC
tCLZ
Read Cycle
I/O
tOFF
Data Out
tRRH
tRCH
tRCS
WE
tOEA
tROH
OE
tRWL
tCWL
tWP
tWCH
Write Cycle
tWCS
WE
tDH
tDS
Data In
I/O
OE
tRCS
tWP
tCWD
tCWL
tAWD
Read-Write Cycle
WE
tOEA
tOED
OE
tAA
tCLZ
tCAC
I/O
4/11/01; V.0.9.1
tDH
tOEZ
Data Out
Alliance Semiconductor
tDS
Data In
P. 21 of 25
AS4C256K16FO
®
CAS-before-RAS self refresh cycle
tRP
tRASS
tRPS
RAS
tRPC
tCP
tRPC
tCHS
tCSR
UCAS,
LCAS
tCEZ
DQ
Typical AC and DC characteristics
1.5
1.2
1.1
1.0
0.9
0.8
4.0
70
4.5
5.0
5.5
Supply voltage (V)
1.2
1.1
1.0
0.8
–55
6.0
Typical supply current ICC
vs. supply voltage VCC
70
50
40
30
20
10
4/11/01; V.0.9.1
6.0
–60
60
–50
50
50
125
Typical supply current ICC
vs. ambient temperature Ta
100
150
200
Load capacitance (pF)
250
Typical power-on current IPO
vs. cycle rate 1/tRC
35
30
50
40
30
20
0.0
–55
–70
70
30
–10
35
80
Ambient temperature (°C)
10
4.5
5.0
5.5
Supply voltage (V)
80
40
60
Supply current (mA)
Supply current (mA)
1.3
0.9
60
0.0
4.0
90
Typical access time
1.3
Ta = 25°C
Typical access time tRAC
vs. load capacitance CL
100
1.4
Normalized access time
Normalized access time
1.4
Normalized access time tRAC
vs. ambient temperature Ta
Power-on current (mA)
1.5
Normalized access time tRAC
vs. supply voltage VCC
25
20
15
10
5
0.0
–10
35
80
125
Ambient temperature (°C)
Alliance Semiconductor
2
4
6
8
Cycle rate (MHz)
10
P. 22 of 25
AS4C256K16FO
®
Typical refresh current ICC3
vs. supply voltage VCC
35
35
20
15
10
25
20
15
10
5
4.5
5.0
5.5
Supply voltage (V)
Typical TTL stand-by current ICC2
vs. ambient temperature Ta
3.5
2.5
2.0
1.5
1.0
0.5
0.0
0
Typical fast page mode current ICC4
vs. ambient temperature Ta
Fast page mode current (mA)
30
25
20
15
10
5
0.0
0
20
40
60
Ambient temperature (°C)
4/11/01; V.0.9.1
80
1.0
4.0
70
50
40
30
20
10
35
1.5
0
60
0.0
0.0
20
40
60
80
Ambient temperature (°C)
2.0
20
40
60
80
Ambient temperature (°C)
Typical output sink current IOL
vs. output voltage VOL
70
Output sink current (mA)
3.0
Stand-by current (mA)
0
0.0
6.0
2.5
0.5
Output source current (mA)
0
4.0
Typical TTL stand-by current ICC2
vs. supply voltage VCC
3.0
Stand-by current (mA)
Refresh current (mA)
Refresh current (mA)
25
5
Fast page mode current (mA)
3.5
30
30
35
Typical refresh current ICC3
vs. Ambient temperature Ta
4.5
5.0
5.5
Supply voltage (V)
6.0
Typical output source current IOH
vs. output voltage VOH
60
50
40
30
20
10
0.0
0.5
1.0
1.5
Output voltage (V)
2.0
0.0
1.0
2.0
3.0
Output voltage (V)
4.0
Typical fast page mode current ICC4
vs. supply voltage VCC
30
25
20
15
10
5
0.0
4.0
4.5
5.0
5.5
Supply voltage (V)
Alliance Semiconductor
6.0
P. 23 of 25
AS4C256K16FO
®
Package dimensions
E He
40/44-pin TSOP II
1 2 3 4 5 6 7 8 910111213141516171819202122
D
l
A2
A
0–5°
A1
e
b
e
E1 E2
B
c
A
A1
b
A
A1
A2
B
b
c
D
E
E1
E2
40-pin SOJ
400 mil
Min
Max
0.128
0.148
0.026
1.105
1.115
0.026
0.032
0.020
0.007
0.013
1.020
1.035
0.370 (typical)
0.395
0.405
0.435
0.445
e
0.050 (typical)
D
40-pin SOJ
Pin 1
A
A1
A2
b
c
D
E
He
e
l
44-pin TSOP II
Min
Max
(mm) (mm)
1.2
0.05
0.95
1.05
0.30
0.45
0.127 (typical)
18.28
18.54
10.03
10.29
11.56
11.96
0.80 (typical)
0.40
0.60
c
44434241403938373635343332313029282726252423
A2
E2
Seating
Plane
Capacitance
(f = 1 MHz, Ta = Room Temperature, VCC = 5V ±10%)
Parameter
Input capacitance
I/O capacitance
4/11/01; V.0.9.1
Symbol
Signals
Test conditions
Max
Unit
CIN1
A0 to A8
VIN = 0V
5
pF
CIN2
RAS, UCAS, LCAS, WE,
OE
VIN = 0V
7
pF
CI/O
I/O0 to I/O15
VIN = VOUT = 0V
7
pF
Alliance Semiconductor
P. 24 of 25
AS4C256K16FO
®
Ordering codes
–25 ns
–30 ns
–35 ns
–50 ns
AS4C256K16F0-25JC
AS4C256K16F0-30JC
AS4C256K16F0-35JC
AS4C256K16FO-50JC
AS4C256K16F0-25JI
AS4C256K16F0-30JI
AS4C256K16F0-35JI
AS4C256K16FO-50JI
AS4C256K16F0-25TC
AS4C256K16F0-30TC
AS4C256K16F0-35TC
AS4C256K16FO-50TC
AS4C256K16F0-25TI
AS4C256K16F0-30TI
AS4C256K16F0-35TI
AS4C256K16FO-50TI
Part numbering system
AS4C
256K16F0
–XX
X
C/I
DRAM prefix
Device number
RAS access time
Package:
J = Plastic SOJ, 400 mil, 40-pin
T = TSOP II, 400 mil, 40/44-pin
Temperature Range:
C= Commercial (0 °C to 70 °C)
I= Industrial (-40°C to 85°C)
4/11/01; V.0.9.1
Alliance Semiconductor
P. 25 of 25
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