DAC DAC 764 764 2 DAC7642 DAC7643 3 SBAS233 – DECEMBER 2001 16-Bit, Dual Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● ● ● ● The DAC7642 and DAC7643 are dual channel, 16-bit, voltage output Digital-to-Analog Converters (DACs) which provide 15-bit monotonic performance over the specified temperature range. They accept 16-bit parallel input data, have double-buffered DAC input logic (allowing simultaneous update of all DACs), and provide a readback mode of the internal input registers. Programmable asynchronous reset clears all registers to a mid-scale code of 8000H (DAC7642) or to a zero-scale code of 0000H (DAC7643). These DACs can operate from a single +5V supply or from +5V and –5V supplies, providing an output range of 0 to +2.5V or –2.5V to +2.5V, respectively. LOW POWER: 4mW UNIPOLAR OR BIPOLAR OPERATION SETTLING TIME: 10µs to 0.003% FSR 15-BIT LINEARITY AND MONOTONICITY: –40°C to +85°C ● RESET TO MID-SCALE (DAC7642) OR ZERO-SCALE (DAC7643) ● DATA READBACK ● DOUBLE-BUFFERED DATA INPUTS APPLICATIONS ● ● ● ● ● Low power and small size per DAC make the DAC7642 and DAC7643 ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closed-loop servo-control. The DAC7642 and DAC7643 are available in a LQFP-32 package and specified over a –40°C to +85°C temperature range. PROCESS CONTROL CLOSED-LOOP SERVO-CONTROL MOTOR CONTROL DATA ACQUISITION SYSTEMS DAC-PER-PIN PROGRAMMERS VCC VREFL Sense VSS VREFL VREFH VREFH Sense DAC7642 DAC7643 16 DATA I/O I/O Buffer Input Register A DAC Register A DAC A VOUTA VOUTA Sense Input Register B DACSEL CS R/W DAC Register B DAC B VOUTB VOUTB Sense Control Logic GND RST LOADDACS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) VCC to VSS ............................................................................. –0.3V to 11V VCC to GND .......................................................................... –0.3V to 5.5V VREFL to VSS ............................................................. –0.3V to (VCC – VSS) VCC to VREFH ............................................................ –0.3V to (VCC – VSS) VREFH to VREFL ......................................................... –0.3V to (VCC – VSS) Digital Input Voltage to GND ................................... –0.3V to VCC + 0.3V Digital Output Voltage to GND ................................. –0.3V to VCC + 0.3V Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +125°C Lead Temperature (soldering, 10s) ............................................... +300°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DAC7642VFT DAC7642VFR Tape and Reel, 250 Tape and Reel, 1000 DAC7642VFB T DAC7642VFB R Tape and Reel, 250 Tape and Reel, 1000 DAC7643VFT DAC7643VFR Tape and Reel, 250 Tape and Reel, 1000 DAC7643VFB T DAC7643VFB R Tape and Reel, 250 Tape and Reel, 1000 MONOTONICITY PACKAGE-LEAD PACKAGE DESIGNATOR(1) DAC7642VF 14 Bits LQFP-32 VF –40°C to +85°C DAC7642 " " " " " " DAC7642VFB 15 Bits LQFP-32 VF –40°C to +85°C DAC7642B " " " " " " DAC7643VF 14 Bits LQFP-32 VF –40°C to +85°C DAC7643 " " " " " " DAC7643VFB 15 Bits LQFP-32 VF –40°C to +85°C DAC7643B " " " " " " PRODUCT NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. 2 DAC7642, DAC7643 www.ti.com SBAS233 ELECTRICAL CHARACTERISTICS (Dual Supply) At TA = TMIN to TMAX, VCC = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, unless otherwise noted. DAC7642VF DAC7643VF PARAMETER ACCURACY Linearity Error Linearity Match Differential Linearity Error Monotonicity, TMIN to TMAX Bipolar Zero Error Bipolar Zero Error Drift Full-Scale Error Full-Scale Error Drift Bipolar Zero Matching Full-Scale Matching Power-Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration CONDITIONS MIN MAX ±3 ±4 ±2 ±4 R L = 10kΩ VREFL –1.25 No Oscillation MIN ±3 ±3 10 ±3 10 ±3 ±3 100 VREFH +1.25 VREFL + 1.25 –2.5 +2.5 VREFH – 1.25 8 0.5 2 60 40 f = 10kHz 7FFFH to 8000H or 8000H to 7FFFH UNITS ±2 ±2 ±1 ±3 ✻ ✻ ✻ ✻ ±1 ±1 ✻ ✻ ✻ ✻ ✻ ±3 ±3 ✻ LSB LSB LSB Bits mV ppm/°C mV ppm/°C mV mV ppm/V ✻ ✻ ✻ ✻ ✻ ✻ ✻ 10 POWER SUPPLY VCC VSS ICC ISS Power TEMPERATURE RANGE Specified Performance +4.75 –5.25 –1.2 –40 V mA pF mA ✻ ✻ V V µA µA ✻ µs LSB nV-s nV/√Hz nV-s ✻ 0.3 • VCC ±10 ±10 3.6 ✻ ✻ ✻ ✻ 0.7 • VCC IOH = –0.8mA IOL = 1.2mA ±2 ✻ ✻ ✻ 500 –500 To ±0.003%, 5V Output Step See Figure 5 MAX ✻ ✻ 500 –10, +30 Indefinite GND, VCC or VSS TYP 15 ±1 5 ±1 5 ±1 ±1 10 Channel-to-Channel Matching Channel-to-Channel Matching At Full-Scale DIGITAL INPUT VIH VIL IIH IIL DIGITAL OUTPUT VOH VOL TYP 14 REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time Channel-to-Channel Crosstalk Digital Feedthrough Output Noise Voltage DAC Glitch DAC7642VFB DAC7643VFB 4.5 0.3 +5.0 –5.0 0.7 –0.8 7.5 ✻ 0.4 +5.25 –4.75 1.1 ✻ ✻ ✻ 11.5 +85 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V µA µA ✻ V V ✻ ✻ ✻ ✻ V V mA mA mW ✻ °C ✻ Specifications same as DAC7642VF and DAC7643VF. DAC7642, DAC7643 SBAS233 www.ti.com 3 ELECTRICAL CHARACTERISTICS (Single Supply) At TA = TMIN to TMAX, VCC = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, unless otherwise noted. DAC7642VF DAC7643VF PARAMETER ACCURACY Linearity Error(1) Linearity Match Differential Linearity Error Monotonicity, TMIN to TMAX Zero-Scale Error Zero-Scale Error Drift Full-Scale Error Full-Scale Error Drift Zero-Scale Matching Full-Scale Matching Power-Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration CONDITIONS MIN MAX ±3 ±4 ±2 ±4 RL = 10kΩ 0 –1.25 No Oscillation MIN ±3 ±3 10 ±3 10 ±3 ±3 100 VREFH +1.25 VREFL + 1.25 0 +2.5 VREFH – 1.25 8 0.5 2 60 40 7FFFH to 8000H or 8000H to 7FFFH UNITS ±2 ±2 ±1 ±3 ✻ ✻ ✻ ✻ ±1 ±1 ✻ ✻ ✻ ✻ ✻ ±3 ±3 ✻ LSB LSB LSB Bits mV ppm/°C mV ppm/°C mV mV ppm/V ✻ ✻ ✻ ✻ ✻ ✻ ✻ 10 POWER SUPPLY VCC VSS ICC Power TEMPERATURE RANGE Specified Performance +4.75 0 –40 V mA pF mA ✻ ✻ V V µA µA ✻ µs LSB nV-s nV/√Hz nV-s ✻ ✻ ✻ ✻ V V µA µA ✻ ✻ ✻ V V ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V mA mW ✻ °C 0.3 • VCC ±10 ±10 3.6 ✻ ✻ ✻ ✻ 0.7 • VCC IOH = –0.8mA IOL = 1.2mA ±2 ✻ ✻ ✻ 250 –250 To ±0.003%, 2.5V Output Step See Figure 6 MAX ✻ ✻ 500 –10, +30 Indefinite GND or VCC TYP 15 ±1 5 ±1 5 ±1 ±1 10 Channel-to-Channel Matching Channel-to-Channel Matching At Full-Scale DIGITAL INPUT VIH VIL IIH IIL DIGITAL OUTPUT VOH VOL TYP 14 REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time Channel-to-Channel Crosstalk Digital Feedthrough Output Noise Voltage, f = 10kHz DAC Glitch DAC7642VFB DAC7643VFB ✻ 4.5 0.3 0.4 +5.0 0 0.5 2.5 +5.25 0 0.9 4.5 ✻ ✻ +85 ✻ ✻ Specifications same as DAC7642VF and DAC7643VF. NOTE: (1) If VSS = 0V, specification applies at Code 0040H and above due to possible negative zero-scale error. 4 DAC7642, DAC7643 www.ti.com SBAS233 PIN CONFIGURATION 25 VOUTB 26 VOUTB Sense 27 VREFH Sense 28 VREFH 29 VREFL 30 VREFL Sense 31 VOUTA Sense LQFP 32 VOUTA Top View VCC 1 24 VSS GND 2 23 DACSEL DB15 3 22 RST DB14 4 21 LOADDACS DB13 5 20 R/W DB12 6 19 CS DB11 7 18 DB0 DB10 8 17 DB1 16 DB2 13 DB5 15 12 DB6 DB3 11 DB7 14 10 DB8 DB4 9 DB9 DAC7642 DAC7643 PIN DESCRIPTIONS PIN NAME DESCRIPTION PIN NAME 1 VCC Positive Power Supply 20 R/W 2 GND Ground Enabled by CS, Controls Data Read from and Write to the Input Registers. DESCRIPTION 3 DB15 Data Bit 15, MSB 21 LOADDACS 4 DB14 Data Bit 14 DAC Output Registers Load Control. Rising edge triggered. Transfers Data from the Input Registers to the DAC Registers, Updating the DAC Output. 5 DB13 Data Bit 13 22 RST 6 DB12 Data Bit 12 7 DB11 Data Bit 11 Reset, Rising Edge Triggered. DAC7642 resets to mid-scale, DAC7643 resets to zero. (Resets Both Input Registers and DAC Registers) 8 DB10 Data Bit 10 23 DACSEL Enabled by CS. Selects the individual DAC Input Registers. (LOW Selects Register A, HIGH Selects Register B) VSS Negative Power Supply DAC B Voltage Output 9 DB9 Data Bit 9 10 DB8 Data Bit 8 24 11 DB7 Data Bit 7 25 VOUTB 12 DB6 Data Bit 6 26 VOUTB Sense 13 DB5 Data Bit 5 14 DB4 Data Bit 4 27 VREFH Sense 28 VREFH DAC A and B Reference High Input 29 VOUTL DAC A and B Reference Low Input 15 DB3 Data Bit 3 16 DB2 Data Bit 2 17 DB1 Data Bit 1 18 DB0 Data Bit 0, LSB 19 CS Chip Select, Active LOW DAC A and B Reference High Sense Input 30 VREFL Sense DAC A and B Reference Low Sense Input 31 VOUTA Sense DAC A Output Amplifier Inverting Input. Used to close the feedback loop at the load. 32 VOUTA DAC7642, DAC7643 SBAS233 DAC B Output Amplifier Inverting Input. Used to close the feedback loop at the load. www.ti.com DAC A Output Voltage 5 TYPICAL CHARACTERISTICS: VSS = 0V At TA = +25°C, VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH LE (LSB) Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +85°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, –40°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 6 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 Digital Input Code LE (LSB) LE (LSB) DLE (LSB) DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –40°C LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 +85°C DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) DLE (LSB) DLE (LSB) LE (LSB) +25°C 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DAC7642, DAC7643 www.ti.com SBAS233 TYPICAL CHARACTERISTICS: VSS = 0V (Cont.) At TA = +25°C, VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. POSITIVE FULL-SCALE ERROR vs TEMPERATURE NEGATIVE FULL-SCALE ERROR vs TEMPERATURE 3 Code (0040H) 2 Positive Full-Scale Error (mV) Negative Full-Scale Error (mV) 3 DAC A 1 0 DAC B –1 –2 DAC A 1 0 DAC B –1 –2 –3 –3 –40 –15 10 35 60 –40 85 –15 35 Temperature (°C) VREFH CURRENT vs CODE (all DACs sent to indicated code) VREFL CURRENT vs CODE (all DACs sent to indicated code) 0.30 0.00 0.25 –0.05 0.20 0.15 0.10 60 85 –0.10 –0.15 –0.20 0.05 –0.25 0.00 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –0.30 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs DIGITAL INPUT CODE 1 1.0 Data = FFFFH (all DACs) No Load No Load 0.8 0.8 0.6 0.6 ICC (mA) ICC (mA) 10 Temperature (°C) VREF Current (mA) VREF Current (mA) Code (FFFFH) 2 0.4 0.2 All DACs 0.4 0.2 0 –40 –15 10 35 60 0.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 85 Temperature (°C) Digital Input Code DAC7642, DAC7643 SBAS233 www.ti.com 7 TYPICAL CHARACTERISTICS: VSS = 0V (Cont.) At TA = +25°C, VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs SETTLING TIME (0V to +2.5V) Large-Signal Settling Time: 1V/div OUTPUT VOLTAGE vs SETTLING TIME (+2.5V to 2mV) +5V LDAC 0 Output Voltage Output Voltage Small-Signal Settling Time: 500µV/div Small-Signal Settling Time: 500µV/div Large-Signal Settling Time: 1V/div +5V LDAC 0 Time (2µs/div) Time (2µs/div) OUTPUT VOLTAGE vs MIDSCALE GLITCH PERFORMANCE OUTPUT VOLTAGE vs MIDSCALE GLITCH PERFORMANCE +5V LDAC 0 Output Voltage (20mV/div) Output Voltage (20mV/div) +5V LDAC 0 7FFFH to 8000H 8000H to 7FFFH Time (1µs/div) Time (1µs/div) BROADBAND NOISE OUTPUT NOISE VOLTAGE vs FREQUENCY Noise (nV/√Hz) Noise Voltage (50µV/div) 1000 100 10 10 Time (10µs/div) 100 1000 10000 100000 1000000 Frequency (Hz) 8 DAC7642, DAC7643 www.ti.com SBAS233 TYPICAL CHARACTERISTICS: VSS = 0V (Cont.) At TA = +25°C, VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. LOGIC SUPPLY CURRENT vs LOGIC INPUT LEVEL FOR DIGITAL INPUTS VOUT vs RLOAD 5 Typical of One Digital Input 0.40 4 0.30 3 VOUT (V) Logic Supply Current (mA) 0.50 0.20 Source 2 0.10 1 0.00 0 0.01 1 0 2 3 4 5 Sink 0.1 1 10 100 RLOAD (kΩ) Logic Input Level for Digital Inputs (V) VSS = –5V At TA = +25°C, VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. LE (LSB) DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +85°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85°C) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 LE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25°C) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 +85°C DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) +25°C Digital Input Code 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DAC7642, DAC7643 SBAS233 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 www.ti.com 9 TYPICAL CHARACTERISTICS: VSS = –5V (Cont.) At TA = +25°C, VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, –40°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) LE (LSB) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code VREFH CURRENT vs CODE (all DACs sent to indicated code) VREFL CURRENT vs CODE (all DACs sent to indicated code) 0.6 0.0 0.5 –0.1 VREF Current (mA) VREF Current (mA) DLE (LSB) LE (LSB) –40°C 0.4 0.3 0.2 –0.2 –0.3 –0.4 0.1 –0.5 0.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –0.6 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code POSITIVE FULL-SCALE ERROR vs TEMPERATURE BIPOLAR ZERO ERROR vs TEMPERATURE 3 3 Bipolar Zero Error (mV) Positive Full-Scale Error (mV) Code (8000H) 2 DAC A 1 0 –1 DAC B –2 DAC A 1 0 –1 DAC B –2 –3 –3 –40 –15 10 35 60 –40 85 –15 10 35 60 85 Temperature (°C) Temperature (°C) 10 Code (FFFFH) 2 DAC7642, DAC7643 www.ti.com SBAS233 TYPICAL CHARACTERISTICS: VSS = –5V (Cont.) At TA = +25°C, VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. NEGATIVE FULL-SCALE ERROR vs TEMPERATURE SUPPLY CURRENT vs DIGITAL INPUT CODE 1.00 Code (0000H) No Load ICC 0.75 2 DAC A Supply Current (mA) Negative Full-Scale Error (mV) 3 1 0 DAC B –1 –2 0.50 0.25 0.00 –0.25 –0.50 –0.75 ISS –1.00 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –3 –40 –15 10 35 60 85 Temperature (°C) Digital Input Code VOUT vs RLOAD SUPPLY CURRENT vs TEMPERATURE 5 1 ICC 4 Source 0.5 Supply Current (mA) 3 VOUT (V) 2 1 0 –1 Sink –2 –3 0 –0.5 ISS –1 Data = FFFFH (all DACs) No Load –4 –5 0.01 –1.5 0.1 1 10 100 –40 –15 10 35 60 RLOAD (kΩ) Temperature (°C) OUTPUT VOLTAGE vs SETTLING TIME (–2.5V to +2.5V) OUTPUT VOLTAGE vs SETTLING TIME (+2.5V to –2.5V) 85 +5V LDAC 0 Output Voltage Output Voltage Large-Signal Settling Time: 2V/div Small-Signal Settling Time: 500µV/div Small-Signal Settling Time: 500µV/div Large-Signal Settling Time: 2V/div +5V LDAC 0 Time (2µs/div) Time (2µs/div) DAC7642, DAC7643 SBAS233 www.ti.com 11 TYPICAL CHARACTERISTICS: VSS = –5V (Cont.) At TA = +25°C, VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs MIDSCALE GLITCH PERFORMANCE Output Voltage (50mV/div) Output Voltage (50mV/div) OUTPUT VOLTAGE vs MIDSCALE GLITCH PERFORMANCE 7FFFH to 8000H 8000H to 7FFFH +5V LDAC 0 +5V LDAC 0 Time (1µs/div) Time (1µs/div) THEORY OF OPERATION by the external voltage references VREFL and VREFH, respectively. The digital input is a 16-bit parallel word and the DAC input registers offer a readback capability. The converters can be powered from either a single +5V supply or a dual ±5V supply. Each device offers a reset function which immediately sets all DAC output voltages, DAC registers and Input registers to mid-scale, code 8000H (DAC7642), or to zeroscale, code 0000H (DAC7643). See Figures 2 and 3 for the basic configurations of the DAC7642 and DAC7643. The DAC7642 and DAC7643 are dual channel, voltage output, 16-bit DACs. The architecture is an R-2R ladder configuration with the three MSB’s segmented followed by an operational amplifier that serves as a buffer. Each DAC has its own R-2R ladder network, segmented MSBs, and output op amp, as shown in Figure 1. The minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set RF VOUT Sense VOUT R 2R 2R 2R 2R 2R 2R 2R 2R 2R VREFH VREFH Sense VREFL VREFL Sense FIGURE 1. DAC7642 and DAC7643 Architecture. 12 DAC7642, DAC7643 www.ti.com SBAS233 0V to +2.5V 32 +2.5V 31 VOUTA 1 +5V 1µF 0.1µF 2 3 4 5 DATA BUS 6 7 8 30 29 28 0V to +2.5V 27 VREFH VREFL Sense VOUTA Sense 26 25 VOUTB Sense VREFH Sense VREFL VOUTB VSS VCC GND DACSEL DB15 RST DAC7642 DAC7643 DB14 LDAC DB13 R/W DB12 CS DB11 DB0 DB10 DB1 24 23 SELECT DAC CHANNEL 22 RESET DAC REGISTERS 21 LOAD DAC REGISTERS 20 READ/WRITE 19 CHIP SELECT 18 17 DATA BUS DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 9 10 11 12 13 14 15 16 FIGURE 2. Basic Single-Supply Operation of the DAC7642 and DAC7643. –2.5V to +2.5V 32 31 +5V 1µF 0.1µF 2 3 4 5 DATA BUS 6 7 8 30 29 VREFL Sense VOUTA 1 +2.5V –2.5V VOUTA Sense 28 27 26 25 VOUTB Sense VREFH VREFL –2.5V to +2.5V VREFH Sense VOUTB 1µF VSS VCC GND DACSEL DB15 DB14 RST DAC7642 DAC7643 DB13 LDAC R/W DB12 CS DB11 DB0 DB10 DB1 0.1µF 24 –5V 23 SELECT DAC CHANNEL 22 RESET DAC REGISTERS 21 LOAD DAC REGISTERS 20 READ/WRITE 19 CHIP SELECT 18 17 DATA BUS DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 9 10 11 12 13 14 15 16 FIGURE 3. Basic Dual-Supply Operation of the DAC7642 and DAC7643. DAC7642, DAC7643 SBAS233 www.ti.com 13 ANALOG OUTPUTS When VSS = –5V (dual-supply operation), the output amplifier can swing to within 2.25V of the supply rails over the –40°C to +85°C temperature range. When VSS = 0V (single-supply operation), and with RLOAD also connected to ground, the output can swing to ground. Care must also be taken when measuring the zero-scale error when VSS = 0V. Since the DAC output cannot swing below ground, the output voltage may not change for the first few digital input codes (0000H, 0001H, 0002H, etc.) if the output amplifier has a negative offset. At the negative limit of –2mV, the first specified output starts at code 0040H. Due to the high accuracy of these DACs, system design problems such as grounding and contact resistance become very important. A 16-bit converter with a 2.5V full-scale range has a 1LSB value of 38µV. With a load current of 1mA, a series wiring and connector resistance of only 40mΩ (RW2) will cause a voltage drop of 40µV, as shown in Figure 4. To understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copper-clad printed circuit board is 1/2 mΩ per square. For a 1mA load, a 10 milli-inch wide printed circuit conductor 600 milli-inches long will result in a voltage drop of 30µV. The DAC7642 and DAC7643 offer a force and sense output configuration for the high open-loop gain output amplifiers. This feature allows the loop around the output amplifier to be closed at the load (shown in Figure 4), thus ensuring an accurate output voltage. REFERENCE INPUTS The reference inputs, VREFL and VREFH, can be any voltage between VSS + 2.5V and VCC – 2.5V provided that VREFH is at least 1.25V greater than VREFL. The minimum output of each DAC is equal to VREFL plus a small offset voltage (essentially, the offset of the output op amp). The maximum output is equal to VREFH plus a similar offset voltage. Note RW2 DAC7642 DAC7643 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 VREFH Sense 27 VOUTB Sense 26 VOUTB 25 RW1 VOUT +V +2.5V RW1 VOUT RW2 FIGURE 4. Analog Output Closed-Loop Configuration. RW represents wiring resistances. that VSS (the negative power supply) must either be connected to ground or must be in the range of –4.75V to –5.25V. The voltage on VSS sets several bias points within the converter. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device may be affected. The current into the VREFH input and out of VREFL depends on the DAC output voltages and can vary from a few microamps to approximately 0.5mA. The reference input appears as a varying load to the reference. If the references applied can sink or source the required current, a reference buffer is not required. The DAC7642 and DAC7643 feature reference drive and sense connections such that the internal errors caused by the changing reference current and the circuit impedances can be minimized. Figures 5 through 13 show different reference configurations and the effect on the linearity and differential linearity. +V DAC7642 DAC7643 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 OPA2234 VOUT 100Ω 1000pF –V +V 1000pF VREFH Sense 27 VOUTB Sense 26 VOUTB 25 –2.5V 2200pF 100Ω +2.5V 2200pF VOUT –V FIGURE 5. Dual Supply Configuration-Buffered References, Used for Dual-Supply Characteristic Curves. 14 DAC7642, DAC7643 www.ti.com SBAS233 +V DAC7642 DAC7643 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 OPA2350 VOUT 100Ω 27 VOUTB Sense 26 VOUTB 25 2kΩ 1000pF +0.050V 98kΩ +V 100Ω 1000pF VREFH Sense 2200pF +2.5V 2200pF VOUT FIGURE 6. Single-Supply Buffered Reference with VREFL of 50mV. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code FIGURE 7. Integral Linearity and Differential Linearity Error Curves for Figure 6. FIGURE 8. Integral Linearity and Differential Linearity Error Curves for Figure 9. +V +V DAC7642 DAC7643 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 VREFH Sense 27 VOUTB Sense 26 VOUTB 25 OPA2350 VOUT 100Ω +1.25V 2200pF 1000pF +V 1000pF 100Ω 2200pF +2.5V VOUT FIGURE 9. Single-Supply Buffered Reference with VREFL = +1.25V and VREFH = +2.5V. DAC7642, DAC7643 SBAS233 www.ti.com 15 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 VREFH Sense 27 VOUTB Sense 26 VOUTB 25 DAC7642 DAC7643 VOUT +V OPA2350 +V 100Ω 1000pF +2.5V 2200pF VOUT FIGURE 10. Single-Supply Buffered VREFH. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code FIGURE 11. Linearity and Differential Linearity Error Curves for Figure 10. FIGURE 13. Linearity and Differential Linearity Error Curves for Figure 12. DIGITAL INTERFACE DAC7642 DAC7643 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 VREFH Sense 27 VOUTB Sense 26 VOUTB 25 VOUT +V +2.5V VOUT See Table I for the basic control logic of the DAC7642 and DAC7643. Note that each internal register is edge triggered and not level triggered. When the LOADDACS signal is transitioned from LOW to HIGH, the digital word existing in the input register is latched into the DAC register. The first set of registers (the input registers) are triggered via the DACSEL, R/W, and CS inputs. Only one of these registers can be transparent at any given time. The double-buffered architecture is designed mainly so each DAC input register can be written to at any time without affecting the DAC outputs. All DAC voltages are updated simultaneously by the rising edge of LOADDACS. It also allows multiple devices to be updated simultaneously by sharing the LOADDACS control from the host with each device. FIGURE 12. Low-Cost Single-Supply Configuration. 16 DAC7642, DAC7643 www.ti.com SBAS233 DACSEL R/W CS RST LOADDACS INPUT REGISTER DAC REGISTER MODE DAC L H L H X X X L L H H X X X L L L L H H X L, H L, H L, H L, H L, H L, H ↑ X X X X ↑ L, H L, H Write Write Read Read Hold Hold Reset Hold Hold Hold Hold Write Hold Reset Write Input Write Input Read Input Read Input Update Hold Reset A B A B All All All TABLE I. DAC7642 and DAC7643 Logic Truth Table. DIGITAL TIMING VOUT = VREFL + Figure 14 and Table II provide detailed timing for the digital interface of the DAC7642 and DAC7643. (VREFH – VREFL) • N 65, 536 (1) where N is the digital input code. This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. DIGITAL INPUT CODING The DAC7642 and DAC7643 input data is in Straight Binary format. The output voltage is given by Equation 1: tWCS CS tRCS CS tRDH tRDS tWS tWH tAS tAH R/W DACSEL R/W tLS ±0.003% of FSR Error Band LOADDACS DACSEL tDH tDS tDZ Data In tS Data Valid Data Out tLH tLWD tAH tAS tLX tCSD VOUT Data Read Timing Data Write Timing ±0.003% of FSR Error Band tRSH tRSS RST tS +FS (DAC7643) VOUT Zero-Scale –FS +FS (DAC7642) VOUT Midscale –FS FIGURE 14. Digital Input and Output Timing. DAC7642, DAC7643 SBAS233 www.ti.com 17 SYMBOL DESCRIPTION MIN tRCS tRDS tRDH tDZ tCSD tWCS tWS tWH tAS tAH tLS tLH tLX tDS tDH tLWD tRSS tRSH tS CS LOW for Read R/W HIGH to CS LOW R/W HIGH after CS HIGH CS HIGH to Data Bus in High Impedance CS LOW to Data Bus Valid CS LOW for Write R/W LOW to CS LOW R/W LOW after CS HIGH DACSEL Valid to CS LOW DACSEL Valid after CS HIGH CS LOW to LOADDACS HIGH CS LOW after LOADDACS HIGH LOADDACS HIGH Data Valid to CS LOW Data Valid after CS HIGH LOADDACS LOW RESET LOW RESET HIGH Settling Time 150 10 10 10 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs 100 150 100 40 0 10 0 10 30 100 100 0 10 100 10 10 10 TABLE II. Timing Specifications (TA = –40°C to +85°C). DIGITALLY-PROGRAMMABLE CURRENT SOURCE The DAC7642 and DAC7643 offer a unique set of features that allows a wide range of flexibility in designing applications circuits, such as programmable current sources. The DAC7642 and DAC7643 offer both a differential reference input, as well as an open-loop configuration around the output amplifier. The open-loop configuration around the output amplifier allows a transistor to be placed within the loop to implement a digitally-programmable, unidirectional current source. The availability of a differential reference also allows programmability for both the full-scale and zero-scale currents. The output current is calculated as: V H – VREFL N Value IOUT = REF • 65, 536 R SENSE + (VREFL / R SENSE ) Figure 15 shows a DAC7642 and DAC7643 in a 4-20mA current output configuration. The output current can be determined by Equation 3: (3) IOUT 2.5V – 0.5V N Value 0.5V = + • 65, 536 125Ω 125Ω At full-scale, the output current is 16mA plus the 4mA for the zero current. At zero scale the output current is the offset current of 4mA (0.5V/125Ω). (2) IOUT VPROGRAMMED 125Ω DAC7642 DAC7643 VOUTA 32 VOUTA Sense 31 VREFL Sense 30 VREFL 29 VREFH 28 OPA2350 100Ω VREFH Sense 27 26 VOUTB 25 2200pF 20kΩ 1000pF 80kΩ 100Ω 1000pF VOUTB Sense +V 2200pF +V +2.5V IOUT VPROGRAMMED 125Ω FIGURE 15. 4-20mA Digitally Controlled Current Source. 18 DAC7642, DAC7643 www.ti.com SBAS233 PACKAGE DRAWING MTQF002B – JANUARY 1995 – REVISED MAY 2000 VF (S-PQFP-G32) PLASTIC QUAD FLATPACK 0,45 0,25 0,80 24 0,20 M 17 25 16 32 9 0,13 NOM 1 8 5,60 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,05 MIN 0,25 0°– 7° 1,45 1,35 Seating Plane 0,75 0,45 0,10 1,60 MAX 4040172/D 04/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. DAC7642, DAC7643 SBAS233 www.ti.com 19 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Applications amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated