CY62128EV30 MoBL® 1-Mbit (128 K × 8) Static RAM 1-Mbit (128 K × 8) Static RAM Features Functional Description ■ Very high speed: 45 ns The CY62128EV30 is a high performance CMOS static RAM module organized as 128K words by 8-bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). ■ Temperature ranges: ❐ Industrial: –40 °C to +85 °C ■ Wide voltage range: 2.2 V to 3.6 V ■ Pin compatible with CY62128DV30 ■ Ultra low standby power ❐ Typical standby current: 1 µA ❐ Maximum standby current: 4 µA ■ Ultra low active power ❐ Typical active current: 1.3 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2, and OE features ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Offered in Pb-free 32-pin SOIC, 32-pin thin small outline package (TSOP) Type I, and 32-pin shrunk thin small outline package (STSOP) packages To write to the device, take chip enable (CE1 LOW and CE2 HIGH) and write enable (WE) inputs LOW. Data on the eight I/O pins is then written into the location specified on the address pin (A0 through A16). To read from the device, take chip enable (CE1 LOW and CE2 HIGH) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. Logic Block Diagram SENSE AMPS ROW DECODER 128K x 8 ARRAY I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 • POWER DOWN I/O 7 A16 A14 A12 OE A15 COLUMN DECODER WE Cypress Semiconductor Corporation Document #: 38-05579 Rev. *J I/O 1 A13 CE1 CE2 I/O 0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 25, 2011 [+] Feedback CY62128EV30 MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Document #: 38-05579 Rev. *J Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18 Page 2 of 18 [+] Feedback CY62128EV30 MoBL® Pin Configuration Figure 1. 32-pin STSOP [1] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 25 26 27 26 28 29 30 31 32 1 2 3 4 5 6 7 8 Top View (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Figure 2. 32-pin TSOP I [1] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Top View (not to scale) OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Figure 3. 32-pin SOIC [1] Top View NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Product Portfolio Power Dissipation Product Range Speed (ns) VCC Range (V) Operating ICC (mA) f = 1 MHz CY62128EV30LL Industrial Min Typ [2] Max 2.2 3.0 3.6 45 f = fmax Standby ISB2 (µA) Typ [2] Max Typ [2] Max Typ [2] Max 1.3 2.0 11 16 1 4 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document #: 38-05579 Rev. *J Page 3 of 18 [+] Feedback CY62128EV30 MoBL® DC input voltage [3, 4] ...................–0.3 V to VCC(max) + 0.3 V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied .......................................... –55 °C to +125 °C Supply voltage to ground potential .......................................–0.3 V to VCC(max) + 0.3 V DC voltage applied to outputs in high Z State [3, 4] ......................–0.3 V to VCC(max) + 0.3 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (MIL-STD-883, method 3015) ................................. > 2001 V Latch-up current .................................................... > 200 mA Operating Range Device Range Ambient Temperature VCC[5] CY62128EV30LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH voltage VOL Output LOW voltage VIH VIL Input HIGH voltage Input LOW voltage Test Conditions 45 ns (Industrial) Unit Min Typ [6] Max IOH = –0.1 mA 2.0 – – V IOH = –1.0 mA, VCC > 2.70 V 2.4 – – V IOL = 0.1 mA – – 0.4 V IOL = 2.1 mA, VCC > 2.70 V – – 0.4 V VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 V V VCC= 2.7 V to 3.6 V 2.2 – VCC + 0.3 V V VCC = 2.2 V to 2.7 V –0.3 – 0.6 V VCC= 2.7 V to 3.6 V –0.3 – 0.8 V IIX Input leakage current GND < VI < VCC –1 – +1 µA IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 µA ICC VCC operating supply current f = fmax = 1/tRC – 11 16 mA – 1.3 2.0 mA f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels ISB1[7] Automatic CE power-down current — CMOS inputs CE1 > VCC0.2 V, CE2 < 0.2 V VIN > VCC – 0.2 V, VIN < 0.2 V f = fmax (address and data only), f = 0 (OE and WE), VCC = 3.60 V – 1 4 µA ISB2[7] Automatic CE power-down current — CMOS inputs CE1 > VCC – 0.2 V, CE2 < 0.2 V VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V – 1 4 µA Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05579 Rev. *J Page 4 of 18 [+] Feedback CY62128EV30 MoBL® Capacitance Parameter [8] CIN Description Test Conditions Input capacitance COUT TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Output capacitance Max Unit 10 pF 10 pF Thermal Resistance Parameter [8] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 32-pin TSOP I 32-pin SOIC 32-pin STSOP Unit Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 33.01 48.67 32.56 °C/W 3.42 25.86 3.59 °C/W AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES VCC R2 30 pF INCLUDING JIG AND SCOPE 90% 10% GND Rise Time = 1 V/ns Equivalent to: 90% 10% Fall Time = 1 V/ns THEVENIN EQUIVALENT RTH OUTPUT V Parameters 2.50 V 3.0 V Unit R1 16667 1103 R2 15385 1554 RTH 8000 645 VTH 1.20 1.75 V Note 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05579 Rev. *J Page 5 of 18 [+] Feedback CY62128EV30 MoBL® Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ [9] Max Unit 1.5 – – V – – 3 µA VDR VCC for data retention ICCDR[10] Data retention current tCDR[11] Chip deselect to data retention time 0 – – ns tR[12] Operation recovery time 45 – – ns VCC = 1.5 V, CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Industrial Data Retention Waveform Figure 5. Data Retention Waveform [13] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5 V VCC(min) tR CE Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 10. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) 100 µs. 13. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document #: 38-05579 Rev. *J Page 6 of 18 [+] Feedback CY62128EV30 MoBL® Switching Characteristics Over the Operating Range Parameter [14, 15] Description 45 ns (Industrial) Min Max Unit Read Cycle tRC Read cycle time 45 – ns tAA Address to data valid – 45 ns tOHA Data hold from address change 10 – ns tACE CE LOW to data valid – 45 ns tDOE OE LOW to data valid – 22 ns tLZOE OE LOW to low Z [16] 5 – ns tHZOE OE HIGH to high Z [16, 17] – 18 ns tLZCE CE LOW to low Z [16] 10 – ns tHZCE CE HIGH to high Z [16, 17] – 18 ns tPU CE LOW to power-up 0 – ns tPD CE HIGH to power-down – 45 ns tWC Write cycle time 45 – ns tSCE CE LOW to write end 35 – ns tAW Address setup to write end 35 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 35 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns – 18 ns 10 – ns Write Cycle [18] [16, 17] tHZWE WE LOW to high Z tLZWE WE HIGH to low Z [16] Notes 14. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 15. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 18. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05579 Rev. *J Page 7 of 18 [+] Feedback CY62128EV30 MoBL® Switching Waveforms Figure 6. Read Cycle 1 (Address Transition Controlled) [20, 21] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 7. Read Cycle No. 2 (OE Controlled) [21, 22, 23] 2 ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tLZCE tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 19. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 20. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 21. WE is HIGH for read cycle. 22. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 23. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. Document #: 38-05579 Rev. *J Page 8 of 18 [+] Feedback CY62128EV30 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (WE Controlled) [24, 25, 26, 27] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O NOTE 28 tHD DATA VALID tHZOE Figure 9. Write Cycle No. 2 (CE1 or CE2 Controlled) [24, 25, 26, 27] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Notes 24. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 25. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 26. Data I/O is high impedance if OE = VIH. 27. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 28. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05579 Rev. *J Page 9 of 18 [+] Feedback CY62128EV30 MoBL® Switching Waveforms (continued) Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [29, 30] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 31 tHD DATA VALID tHZWE tLZWE Notes 29. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 30. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 31. During this period, the I/Os are in output state. Do not apply input signals. Document #: 38-05579 Rev. *J Page 10 of 18 [+] Feedback CY62128EV30 MoBL® Truth Table CE1 WE OE Inputs/Outputs Mode Power [32] X X High Z Deselect/power-down Standby (ISB) [32] L X X High Z Deselect/power-down Standby (ISB) L H H L Data out Read Active (ICC) L H L X Data in Write Active (ICC) L H H H High Z Selected, outputs disabled Active (ICC) H X CE2 X Note 32. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document #: 38-05579 Rev. *J Page 11 of 18 [+] Feedback CY62128EV30 MoBL® Ordering Information Speed (ns) 45 Ordering Code Package Diagram Package Type CY62128EV30LL-45SXI 51-85081 32-pin 450-Mil SOIC (Pb-free) CY62128EV30LL-45ZXI 51-85056 32-pin TSOP Type I (Pb-free) CY62128EV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 2 8 E V30 LL - 45 XX X I Temperature Grade: I = Industrial Pb-free Package Type: XX = S or Z or ZA S = 32-pin SOIC Z = 32-pin TSOP Type I ZA = 32-pin STSOP Speed Grade: 45 ns LL = Low Power Voltage Range: 3 V typical E = Process Technology 90 nm Bus width = × 8 Density = 1-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document #: 38-05579 Rev. *J Page 12 of 18 [+] Feedback CY62128EV30 MoBL® Package Diagrams Figure 11. 32-pin Molded SOIC (450 Mil) S32.45/SZ32.45, 51-85081 51-85081 *C Document #: 38-05579 Rev. *J Page 13 of 18 [+] Feedback CY62128EV30 MoBL® Package Diagrams (continued) Figure 12. 32-pin TSOP I (8 × 20 × 1.0 mm) Z32, 51-85056 51-85056 *F Document #: 38-05579 Rev. *J Page 14 of 18 [+] Feedback CY62128EV30 MoBL® Package Diagrams (continued) Figure 13. 32-pin Small TSOP (8 × 13.4 × 1.2 mm) ZA32, 51-85094 51-85094 *F Document #: 38-05579 Rev. *J Page 15 of 18 [+] Feedback CY62128EV30 MoBL® Acronyms Acronym Document Conventions Description Units of Measure BHE byte high enable BLE byte low enable °C degree Celsius CE chip enable MHz Mega Hertz CMOS complementary metal oxide semiconductor A micro Amperes I/O input/output s micro seconds OE output enable mA milli Amperes SOIC small outline integrated circuit mm milli meter SRAM static random access memory ns nano seconds STSOP shrunk thin small outline package ohms TSOP thin small outline package % percent WE write enable pF pico Farad V Volts W Watts Document #: 38-05579 Rev. *J Symbol Unit of Measure Page 16 of 18 [+] Feedback CY62128EV30 MoBL® Document History Page Document Title: CY62128EV30 MoBL®, 1-Mbit (128 K × 8) Static RAM Document Number: 38-05579 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 285473 See ECN PCI New Data Sheet *A 461631 See ECN NXR Converted from Preliminary to Final Removed 35 ns Speed Bin Removed “L” version of CY62128EV30 Removed Reverse TSOP I package from Product offering. Changed ICC (Typ) from 8 mA to 11 mA and ICC (Max) from 12 mA to 16 mA for f = fmax Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz Changed ISB2 (max) from 1 A to 4 A Changed ISB2 (Typ) from 0.5 A to 1 A Changed ICCDR (max) from 1 A to 3 A Changed the AC Test load Capacitance value from 50 pF to 30 pF Changed tLZOE from 3 to 5 ns Changed tLZCE from 6 to 10 ns Changed tHZCE from 22 to 18 ns Changed tPWE from 30 to 35 ns Changed tSD from 22 to 25 ns Changed tLZWE from 6 to 10 ns Updated the Ordering Information table. *B 464721 See ECN NXR Updated the Block Diagram on page # 1 *C 1024520 See ECN VKN Added final Automotive-A and Automotive-E information Added footnote #9 related to ISB2 and ICCDR Updated Ordering Information table *D 2257446 See ECN NXR Changed the Maximum rating of Ambient Temperature with Power Applied from 55°C to +125°C to –55°C to +125°C. *E 2702841 05/06/2009 *F 2781490 10/08/2009 VKN Included “CY62128EV30LL-45ZAXA” part in the Ordering Information table *G 2934428 06/03/10 VKN Added footnote #21 related to chip enable Updated package diagrams Updated template *H 3026548 09/12/2010 AJU Updated Pin Configuration Added Ordering Code Definitions Added Acronyms and Units of Measure Minor edits *I 3115909 01/06/2011 RAME *J 3292906 06/25/2011 AJU Document #: 38-05579 Rev. *J VKN/PYRS Added -45SXA part in the Ordering Information table Corrected “tPD” spec description in the “Switching Characteristics” table. Separated Automotive and Industrial parts from this datasheet. Removed Automotive info completely Removed the Note “For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.” and its reference in Functional Description. Updated Package Diagrams. Updated in new template. Page 17 of 18 [+] Feedback CY62128EV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05579 Rev. *J Revised June 25, 2011 Page 18 of 18 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback