Rohm BR24T512-W High reliability serial eeprom Datasheet

High Reliability Serial EEPROMs
I2C BUS
BR24□□□□family
BR24T□□□□Series
No.11001EAT21
●Description
2
BR24T□□□-W series is a serial EEPROM of I C BUS interface method
●Features
2
1) Completely conforming to the world standard I C BUS.
All controls available by 2 ports of serial clock (SCL) and serial data(SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port
3) 1.7V～5.5V single power source action most suitable for battery use
4) 1.7V～5.5Vwide limit of action voltage, possible FAST MODE 400KHz action
5) Page write mode useful for initial value write at factory shipment
6) Auto erase and auto end function at data write
7) Low current consumption
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) DIP-T8/SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J/MSOP8/VSON008X2030 various packages
10) Data rewrite up to 1,000,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
●BR24T series
Capacity Bit format
Type
Power source
Voltage
DIP-T8
SOP8
SOP-J8
SSOP-B8 TSSOP-B8 TSSOP-B8J
MSOP8
VSON008
X2030
1Kbit
128×8
BR24T01-W 1.7～5.5V
●
●
●
●
●
●
●
●
2Kbit
256×8
BR24T02-W 1.7～5.5V
●
●
●
●
●
●
●
●
4Kbit
512×8
BR24T04-W 1.7～5.5V
●
●
●
●
●
●
●
●
8Kbit
1K×8
BR24T08-W 1.7～5.5V
●
●
●
●
●
●
●
●
16Kbit
2K×8
BR24T16-W 1.7～5.5V
●
●
●
●
●
●
●
●
32Kbit
4K×8
BR24T32-W 1.7～5.5V
●
●
●
●
●
●
●
●
64Kbit
8K×8
BR24T64-W 1.7～5.5V
●
●
●
●
●
●
●
●
128Kbit
16K×8
BR24T128-W 1.7～5.5V
●
●
●
●
●
●
●
●
256Kbit
32K×8
BR24T256-W 1.7～5.5V
●
●
●
●
●
512Kbit
64K×8
BR24T512-W 1.7～5.5V
☆
☆
☆
☆
☆
1024Kbit 128K×8
BR24T1M-W 1.7～5.5V
☆
☆
☆
☆:Developing
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© 2011 ROHM Co., Ltd. All rights reserved.
1/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Absolute maximum ratings (Ta=25℃)
Parameter
Symbol
Impressed voltage
VCC
Ratings
Unit
-0.3～+6.5
V
Number of data
rewrite times *1
450 (SOP8)*1
450 (SOP-J8)*2
Data hold years *1
300 (SSOP-B8)*3
Permissible
dissipation
330 (TSSOP-B8)*4
Pd
*5
310 (TSSOP-B8J)
●Memory cell characteristics (Ta=25℃, Vcc=1.7～
5.5V)
Limits
Parameter
Unit
Min.
Typ.
Max
1,000,000
－
－
Times
40
－
－
Years
*1Not 100% TESTED
mW
310 (MSOP8) *6
300 (VSON008X2030) *7
●Recommended operating conditions
800 (DIP-T8)*8
Storage
temperature range
Action
temperature range
Tstg
－65～+150
℃
Parameter
Topr
－40～+85
℃
*9
Terminal voltage
‐
Junction
temperature *10
Tjmax
*1,*2
*3,*7
*4
*5, *6
*8
*9
*10
-0.3～Vcc+1.0
150
V
℃
Symbol
Ratings
Power source
voltage
Vcc
1.7～5.5
Input voltage
VIN
Unit
V
0～Vcc
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.3mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
When using at Ta=25℃ or higher 8.1mW to be reduced per 1℃.
The Max value of Terminal Voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of
Terminal Voltage is not under -1.0V. (BR24T16/32/64/128/256/512/1M-W)
the Min value of Terminal Voltage is not under -0.8V. (BR24T01/02/04/08-W)
Junction temperature at the storage condition.
●Electrical characteristics (Unless otherwise specified, Ta=－40～+85℃, VCC=1.7～5.5V)
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
“H” input voltage 1
VIH1
0.7Vcc
*2
－
Vcc+1.0
V
Conditions
“L” input voltage 1
VIL1
-0.3
－
0.3Vcc
V
“L” output voltage 1
VOL1
－
－
0.4
V
IOL=3.0mA, 2.5V≦Vcc≦5.5V (SDA)
“L” output voltage 2
VOL2
－
－
0.2
V
IOL=0.7mA, 1.7V≦Vcc＜2.5V (SDA)
Input leak current
ILI
－1
－
1
µA
VIN=0～Vcc
Output leak current
ILO
－1
－
1
µA
－
－
2.0
－
－
2.5
－
－
4.5
－
－
0.5
VOUT=0～Vcc (SDA)
Vcc=5.5V,fSCL=400kHz, tWR=5ms,
Byte write, Page write
BR24T01/02/04/08/16/32/64-W
Vcc=5.5V,fSCL=400kHz, tWR=5ms,
Byte write, Page write
BR24T128/256-W
Vcc=5.5V,fSCL=400kHz, tWR=5ms,
Byte write, Page write
BR24T512/1M-W
Vcc=5.5V,fSCL=400kHz
Random read, current read, sequential read
BR24T01/02/04/08/16/32/64/128/256-W
Vcc=5.5V,fSCL=400kHz
Random read, current read, sequential read
BR24T512/1M-W
Vcc=5.5V, SDA・SCL=Vcc
A0,A1,A2=GND,WP=GND
BR24T01/02/04/08/16/32/64/128/256-W
Vcc=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
BR24T512/1M-W
ICC1
Current consumption
at action
mA
ICC2
Standby current
mA
－
－
2.0
－
－
2.0
－
－
3.0
ISB
µA
○ Radiation resistance design is not made.
*1 BR24T512/1M-W is a target value because it is developing.
*2 When the pulse width is 50ns or less, it is -1.0V. (BR24T16/32/64/128/256/512/1M-W)
When the pulse width is 50ns or less, it is -0.8V. (BR24T01/02/04/08-W)
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© 2011 ROHM Co., Ltd. All rights reserved.
2/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Action timing characteristics (Unless otherwise specified, Ta=－40～+85℃, VCC=1.7～5.5V)
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
SCL frequency
fSCL
－
－
400
kHz
Data clock “HIGH“ time
tHIGH
0.6
－
－
µs
Data clock “LOW“ time
tLOW
1.2
－
－
µs
SDA, SCL rise time *1
tR
－
－
1.0
µs
SDA, SCL fall time *1
tF
－
－
1.0
µs
Start condition hold time
tHD:STA
0.6
－
－
µs
Start condition setup time
tSU:STA
0.6
－
－
µs
Input data hold time
tHD:DAT
0
－
－
ns
Input data setup time
tSU:DAT
100
－
－
ns
Output data delay time
tPD
0.1
－
0.9
µs
Output data hold time
tDH
0.1
－
－
µs
tSU:STO
0.6
－
－
µs
Bus release time before transfer start
tBUF
1.2
－
－
µs
Internal write cycle time
tWR
－
－
5
ms
Stop condition setup time
Noise removal valid period (SDA, SCL terminal)
tI
－
－
0.1
µs
WP hold time
tHD:WP
1.0
－
－
µs
WP setup time
tSU:WP
0.1
－
－
µs
WP valid time
tHIGH:WP
1.0
－
－
µs
*1 Not 100% TESTED.
Condition Input data level:VIL=0.2×Vcc VIH=0.8×Vcc
Input data timing refarence level: 0.3×Vcc/0.7×Vcc
Output data timing refarence level: 0.3×Vcc/0.7×Vcc
Rise/Fall time : ≦20ns
●Sync data input / output timing
tR
tF
SCL
tHIGH
30%
30%
30%
30%
70%
70%
70%
70% 70%
tLOW
tHD:DAT
SDA
(input)
70%
70%
70%
30%
tPD
tBUF
DATA(n)
DATA(1)
tSU:DAT
70%
D0
D1
70%
ACK
ACK
tWR
tDH
30%
SDA
(output)
70%
70%
30%
30%
tSU:WP
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
70%
tHD:STA
DATA(n)
DATA(1)
D1
tSU:STA
tHD:WP
STOP CONDITION
Fig.1-(d) WP timing at write execution
70%
70%
30%
tSU:STO
D0
ACK
ACK
70%
tWR
tHIGH:WP
70%
30%
70%
30%
STOP CONDITION
START CONDITION
Fig.1-(b) Start-stop bit timing
D0
write data
(n-th address)
ACK
70%
Fig.1-(e) WP timing at write cancel
70%
70%
tWR
STOP CONDITION
START CONDITION
Fig.1-(c) Write cycle timing
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© 2011 ROHM Co., Ltd. All rights reserved.
3/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Block diagram
*2
A0
1
1Kbit～1024Kbit EEPROM array
8
Vcc
7
WP
*1
A0
1
A1
2
A2
3
GND
4
BR24T01-W
BR24T02-W
BR24T04-W
BR24T08-W
BR24T16-W
BR24T32-W
BR24T64-W
BR24T128-W
BR24T256-W
BR24T512-W
BR24T1M-W
8bit
*2
A1
Address
decoder
2
*17bit
13bit
8bit 14bit
9bit 15bit
10bit 16bit
11bit 17bit
12bit
Word
address register
START
*2
3
A2
Data
register
STOP
Control circuit
6
SCL
5
SDA
ACK
*
1
Power source
voltage detection
High voltage
generating circuit
4
GND
7bit: BR24T01-W
8bit: BR24T02-W
9bit: BR24T04-W
10bit: BR24T08-W
11bit: BR24T16-W
12bit: BR24T32-W
13bit: BR24T64-W
14bit: BR24T128-W
15bit: BR24T256-W
16bit: BR24T512-W
17bit: BR24T1M-W
*2
8
Vcc
7
WP
6
SCL
5
SDA
A0= Don't use : BR24T04-W, BR24T1M-W
A0, A1=Don't use: BR24T08-W
A0, A1, A2=Don't use: BR24T16-W
Fig.2 Block diagram
●Pin assignment and description
Terminal Input/
BR24T01-W
Name
Output
BR24T02-W
BR24T04-W
BR24T08-W
Slave address setting
BR24T32/64/
128/256/512-W
BR24T16-W
Slave address
Don’t use*
setting
Slave address setting
Don’t use*
A0
Input
A1
Input
A2
Input
GND
Reference voltage of all input / output, 0V
SCL
－
Input/
output
Input
WP
Input
Write protect terminal
Vcc
－
Connect the power source.
SDA
Slave address setting
Don’t use*
Slave address setting
BR24T1M-W
Don’t use*
Slave address setting
Serial data input serial data output
Serial clock input
*Pins not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.
●Characteristic data (The following values are Typ. ones.)
4
L INPUT VOLTAGE : VIL1(V)
Ta=-40℃
Ta=25℃
Ta=85℃
3
SPEC
2
1
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
L OUTPUT VOLTAGE : VOL1(V)
5
H INPUT VOLTAGE : VIH1(V)
1
6
6
3
2
1
SPEC
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
0
6
1
2
3
4
5
6
0.6
SPEC
0.4
0.2
1
0.8
0.6
Ta=-40℃
Ta=25℃
Ta=85℃
0.4
0.2
0
0
3
4
5
6
L OUTPUT CURRENT : IOL(mA)
Fig.6 'L' output voltage VOL2-IOL(Vcc=2.5V)
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© 2011 ROHM Co., Ltd. All rights reserved.
2
3
4
5
L OUTPUT CURRENT : IOL(mA)
6
1.2
OUTPUT LEAK CURRENT : I LO(uA)
INPUT LEAK CURRENT : ILI(uA)
Ta=-40℃
Ta=25℃
Ta=85℃
2
1
Fig.5 'L' output voltage VOL1-IOL(Vcc=1.7V)
SPEC
L OUTPUT VOLTAGE : VOL2(V)
0
1.2
1
0.2
Fig.4 'L' input voltage VIL1
(A0,A1,A2,SCL,SDA,WP)
1
0
SPEC
0.4
SUPPLY VOLTAGE : Vcc(V)
Fig.3 'H' input voltage VIH1
(A0,A1,A2,SCL,SDA,WP)
0.8
0.6
0
0
0
Ta=-40℃
Ta=25℃
Ta=85℃
0.8
0
1
2
3
4
5
SUPPLYVOLTAGE : Vcc(V)
Fig.7 Input leak current ILI
(A0,A1,A2,SCL,WP)
4/21
6
SPEC
1
0.8
0.6
Ta=-40℃
Ta=25℃
Ta=85℃
0.4
0.2
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Fig.8 Output leak current ILO(SDA)
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Characteristic data (The following values are Typ. ones.)
3.5
2.5
2
Ta=-40℃
Ta=25℃
Ta=85℃
1
0.5
2
1
2
3
4
5
Ta=-40℃
Ta=25℃
Ta=85℃
1.5
1
0.5
0
0
0
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
1.5
5
SPEC
2.5
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
6
3
SPEC
0
6
1
SUPPLY VOLTAGE : Vcc(V)
2
3
4
5
The plan for
inserting data.
(BR24T512/1M-W)
4
3
2
1
0
6
0
1
2
SUPPLY VOLTAGE : Vcc(V)
Fig.9 Current consumption at WRITE operation ICC1
(fscl=400kHz BR24T01/02/04/08/16/32/64-W)
Fig.10 Current consumption at WRITE operation Icc1
(fscl=400kHz BR24T128/256-W)
0.6
0.1
0.4
0.3
STANBY CURRENT : ISB(uA)
0.2
The plan for
inserting data.
(BR24T512/1M-W)
0.5
CURRENT CONSUMPTION
AT READING : Icc2(mA)
CURRENT CONSUMPTION
AT READING : Icc2(mA)
Ta=-40℃
Ta=25℃
Ta=85℃
0.3
0.2
0.1
0
0
1
2
3
4
5
0
2
5
1.5
1
0.5
4
5
1000
SPEC
100
Ta=-40℃
Ta=25℃
Ta=85℃
10
1
0
1
2
0.9
Ta=-40℃
Ta=25℃
Ta=85℃
0.6
0.3
0
0
1
2
3
4
5
6
START CONDITION HOLD TIME : tHD : STA(us)
1.2
3
4
5
SPEC
0.2
0
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
1.1
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
0.4
0.2
0.9
0.7
SPEC
0.5
Ta=-40℃
Ta=25℃
Ta=85℃
0.3
0.1
-0.1
0
0
1
2
3
4
5
0
6
1
2
3
4
5
6
Fig.20 Start Condition Setup Time tSU : STA
50
SPEC
0
-50
Ta=-40℃
Ta=25℃
Ta=85℃
-100
-150
-200
5
2
Fig.17 Data clock High Period tHIGH
0.6
INPUT DATA HOLD TIME : tHD :DAT(ns)
Ta=-40℃
Ta=25℃
Ta=85℃
4
1
SUPPLY VOLTAGE : Vcc(V)
-50
3
Ta=-40℃
Ta=25℃
Ta=85℃
0.4
Fig.19 Start Condition Hold Time tHD : STA
0
2
6
SUPPLY VOLTAGE : Vcc(V)
SPEC
1
5
0.6
6
0.8
50
0
4
Fig.16 SCL frequency fSCL
SUPPLY VOLTAGE : Vcc（V）
-150
3
0.8
1
Fig.18 Data clock Low Period tLOW
-100
2
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.15 Stanby operation ISB
(fscl=400kHz BR24T512/1M-W)
SPEC
1
0
6
1.5
0.5
1
INPUT DATA SET UP TIME : tSU: DAT(ns)
3
Ta=-40℃
Ta=25℃
Ta=85℃
1
Fig.14 Stanby operation ISB
(fscl=400kHz BR24T01/02/04/08/16/32/64/128/256-W)
START CONDITION
SET UP TIME : tSU:STA(us)
2
1.5
SUPPLY VOLTAGE : Vcc(V)
0.1
1
SPEC
2
0
6
DATA CLK H TIME : tHIGH(us)
SCL FREQUENCY : fｓｃｌ（ｋHZ）
The plan for
inserting data.
(BR24T512/1M-W)
2
0
ＤＡＴＡ CLK L TIME : tLOW(us)
4
10000
0
INPUT DATA HOLD TIME : tHD: STA(ns)
3
Fig.13 Current consumption at READ operation ICC2
(fscl=400kHz BR24T512/1M-W)
2.5
STANBY CURRENT : ISB(uA)
1
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.12 Current consumption at READ operation ICC2
(fscl=400kHz BR24T01/02/04/08/16/32/64/128/256-W)
6
0
0
6
5
2.5
0.6
0.4
4
Fig.11 Current consumption at WRITE operation Icc1
(fscl=400kHz BR24T512/1M-W)
SPEC
0.5
3
SUPPLY VOLTAGE : Vcc(V)
6
-200
SUPPLY VOLTAGE : Vcc(V)
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© 2011 ROHM Co., Ltd. All rights reserved.
200
SPEC
100
0
Ta=-40℃
Ta=25℃
Ta=85℃
-100
-200
0
0
Fig.21 Input Data Hold Time tHD : DAT（HIGH）
300
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
Fig.22 Input Data Hold Time ｔHD : DAT(LOW）
5/21
1
2
3
4
5
6
6
SUPPLY VOLTAGE : Vcc(V)
Fig.23 Input Data Setup Time ｔSU: DAT(HIGH)
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Characteristic data (The following values are Typ. ones.)
200
SPEC
100
0
Ta=-40℃
Ta=25℃
Ta=85℃
-100
-200
0
1
2
3
4
5
6
2.0
Ta=-40℃
Ta=25℃
Ta=85℃
1.5
SPEC
1.0
0.5
SPEC
0.0
0
1
2
SUPPLY VOLTAGE : Vcc(V)
4
5
6
SPEC
0.5
0.0
2
3
4
5
0
SPEC
1
Ta=-40℃
Ta=25℃
Ta=85℃
0.5
0
2
2
3
4
5
6
0.2
0.1
SPEC
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
Fig.29 Internal writing cycle time ｔWR
0.6
Ta=-40℃
Ta=25℃
Ta=85℃
0.5
0.4
0.3
0.2
0.1
SPEC
0
0
4
Ta=-40℃
Ta=25℃
Ta=85℃
0
NOISE REDUCTION
EFECTIVE TIME : tl(SDA H)(us)
NOISE REDUCTION
EFECTIVE TIME : tl(SCL L)(us)
0.3
3
6
0
1
0.6
2
5
3
SUPPLY VOLTAGE : Vcc(V)
Ta=-40℃
Ta=25℃
Ta=85℃
1
4
4
Fig.28 BUS open time before transmission ｔBUF
0.6
0
3
6
SUPPLY VOLTAGE : Vcc(V)
0.4
2
5
1
Fig.27 Stop condition setup time
ｔSU:STO
0.5
1
SPEC
0
1
SPEC
0.0
6
1.5
-0.5
0
0.5
SUPPLY VOLTAGE : Vcc(V)
INTERNAL WRITING
CYCLE TIME : tWR(ms)
Ta=-40℃
Ta=25℃
Ta=85℃
1.0
SPEC
1.0
Fig.26 'H' Data output delay time ｔPD1
2
2.0
1.5
Ta=-40℃
Ta=25℃
Ta=85℃
1.5
SUPPLY VOLTAGE : Vcc(V)
BUS OPEN TIME
BEFORE TRANSMISSION : tBUF(us)
STOP CONDITION SETUP TIME : tsu:STO(us)
3
2.0
Fig.25 'L' Data output delay time tPD0
Fig.24 Input Data setup time tSU : DAT(LOW)
NOISE REDUCTION
EFECTIVE TIME : tl(SCL H) (us)
OUTPUT DATA DELAY TIME : tPD(us)
OUTPUT DATA DELAY TIME : tPD(us)
INPUT DATA SET UP TIME : tSU : DAT(ns)
300
5
0
6
1
2
3
4
5
Ta=-40℃
Ta=25℃
Ta=85℃
0.5
0.4
0.3
0.2
0.1
SPEC
0
6
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Ta=-40℃
Ta=25℃
Ta=85℃
0.5
0.4
0.3
0.2
SPEC
0.1
0
0.2
SPEC
1.0
WP SET UP TIME : tSU : WP(us)
WP DATA HOLD TIME : tHD : WP(us)
NOISE REDUCTION
EFFECTIVE TIME : tl(SAD L)(us)
Fig.32 Noise resuction efecctive time ｔｌ（SDA H）
1.2
0.6
Ta=-40℃
Ta=25℃
Ta=85℃
0.8
0.6
0.4
0.2
1
2
3
4
5
6
SPEC
0.0
Ta=-40℃
Ta=25℃
Ta=85℃
-0.1
-0.2
-0.3
-0.4
-0.5
0
0
1
2
3
4
5
SUPPLYVOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.33 Noise reduction efective time tl（SDA L）
0.1
-0.6
0.0
0
WP EFFECTIVE TIME : tHIGH : WP(us)
SUPPLY VOLATGE : Vcc(V)
Fig.31 Noise reduction efective time tl（SCL L）
Fig.30 Noise reduction efection time tl（SCL H）
Fig.34 WP data hold time tHD:WP
1
2
3
4
5
6
6
SUPPLY VOLTAGE : Vcc(V)
Fig.35 WP setup time tSU : WP
1.2
SPEC
1.0
0.8
Ta=-40℃
Ta=25℃
Ta=85℃
0.6
0.4
0.2
0.0
0
1
2
3
4
5
6
SUPPLYVOLTAGE : Vcc(V)
Fig.36 WP efective time tHIGH : WP
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6/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●I2C BUS communication
2
○I C BUS data communication
2
I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
2
and acknowledge is always required after each byte. I C BUS carries out data transmission with plural devices connected
by 2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.
SDA
1-7
SCL
S
START ADDRESS
condition
8
9
R/W
ACK
1-7
8
1-7
9
DATA
ACK
8
DATA
9
ACK
P
STOP
condition
Fig.37 Data transfer timing
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is
satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・ Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When
acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
・The most insignificant bit (R/W --- READ / WRITE ) of slave address is used for designating write or read action,
and is as shown below.
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
BR24T01-W,BR24T02-W
BR24T04-W
BR24T08-W
Maximum number of
Connected buses
Slave address
Type
1
1
1
0
0
0
1
1
1
0
0
0
A2
A2
A2
A1
A1
P1
A0
P0
P0
――
R/W
――
R/W
――
R/W
――
BR24T16-W
1
0
1
0
P2
P1
P0
R/W
BR24T32-W,BR24T64-W,BR24T128-W,
BR24T256-W,BR24T512-W
1
0
1
0
A2
A1
A0
R/W
BR24T1M-W
1
0
1
0
A2
A1
P0
――
――
R/W
8
4
2
1
8
4
P0～P2 are page select bits.
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7/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write
continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write
bytes is specified per device of each capacity. Up to 256 arbitrary bytes can be written.(In the case of BR24T1M-W)
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS
WA
7
1 0 1 0 A2 A1 A0
WA
0
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
SDA
L IN E
W
R
I
T
E
SLAVE
ADDRESS
(BR24T01/02/04/08/16-W)
2nd WORD
ADDRESS
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0 1
0
15 14
R A
/ C
W K
注)
D7
D A TA (n +1 5 )
D0
D0
*1
As for WA12, BR24T32-W becomes Don't care.
As for WA13, BR24T32/64-W becomes Don't care.
As for WA14, BR24T32/64/128-W becomes Don't care.
As for WA15, BR24T32/64/128/256-W becomes Don't care.
*2
As for BR24T128/256-W becomes (n+63)
As for BR24T512-W becomes (n+127)
As for BR24T1M-W becomes (n+255)
A
C
K
A
C
K
2nd WORD
ADDRESS(n)
D7
0
13 12 11
A
C
K
Fig.41 Page write cycle
S
T
O
P
*2
DATA(n)
WA
*1
As for WA7, BR24T01-W becomes Don't care.
As for BR24T01/02-W becomes (n+7)
S
T
O
P
(BR24T01/02/04/08/16-W)
WA WA WA WA WA
0 A2 A1 A0
0
D A TA (n)
A
C
K
1st WORD
ADDRESS(n)
*1
*2
A
C
K
*2
WA
0
Fig.40 Page write cycle
S
T
A
R
T
As for WA12, BR24T32-W becomes Don't care.
As for WA13, BR24T32/64-W becomes Don't care.
As for WA14, BR24T32/64/128-W becomes Don't care.
As for WA15, BR24T32/64/128/256-W becomes Don't care.
(BR24T32/64/128/256/512/1M-W)
R A
/ C *1
W K
注)
*1
D0
D7
A
C
K
A
C
K
W ORD
A D D R E S S (n )
WA
7
1 0 1 0 A 2A 1A 0
S
T
O
P
DATA
WA
0
*1
Fig.39 Byte write cycle
S
T
A
R
T
A
C
K
WAWA WA WAWA
15 14 13 12 11
R A
/ C
W K
As for WA7, BR24T01-W becomes Don't care.
D0
1st WORD
ADDRESS
1 0 1 0 A2 A1 A0
Note)
D7
A
C
K
Fig.38 Byte write cycle
S
T
A
R
T
DATA
R A
/ C
W K
Note)
S
T
O
P
DATA(n+31)
D0
A
C
K
D0
A
C
K
A
C
K
(BR24T32/64/128/256/512/1M-W)
Note)
*1 In BR24T16-W, A2 becomes P2.
*2 In BR24T08/16-W, A1 becomes P1.
*3 In BR24T04/08/16/1M-W A0 becomes P0.
*1 *2 *3
1 0 1 0 A 2A 1A 0
Fig.42 Difference of slave address of each type
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8/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
・During internal write execution, all input commands are ignored, therefore ACK is not sent back.
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk :
Up to 8Byte (BR24T01-W, BR24T02-W)
Up to 16Byte (BR24T04-W, BR24T08-W, BR24T16-W)
Up to 32Byte (BR24T32-W, BR24T64-W)
Up to 64Byte (BR24T128-W, BR24T256-W)
Up to 128Byte (BR24T512-W)
Up to 256Byte (BR24T1M-W)
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P10.)
・As for page write cycle of BR24T01-W and BR24T02-W, after the significant 4 bits (in the case of BR24T01-W) of word
address, or the significant 5 bits (in the case of BR24T02-W) of word address are designated arbitrarily, by continuing
data input of 2 bytes or more, the address of insignificant 3 bits is incremented internally, and data up to 8 bytes can be
written.
・As for page write command of BR24T04-W, BR24T08-W and BR24T16-W, after page select bit ’P0’(in the case of
BR24T04-W), after page select bit ’P0,P1’(in the case of BR24T08-W), after page select bit ’P0,P1,P2’(in the case of
BR24T16-W) of slave address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of
insignificant 4 bits is incremented internally, and data up to 16 bytes can be written.
・As for page write cycle of BR24T32-W and BR24T64-W, after the significant 7 bits (in the case of BR24T32-W) of word
address, or the significant 8 bits (in the case of BR24T64-W) of word address are designated arbitrarily, by continuing
data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can
be written.
・As for page write cycle of BR24T128-W and BR24T256-W, after the significant 8 bits (in the case of BR24T128-W) of
word address, or the significant 9 bits (in the case of BR24T256-W) of word address are designated arbitrarily, by
continuing data input of 2 bytes or more, the address of insignificant 6 bits is incremented internally, and data up to 64
bytes can be written.
・As for page write cycle of BR24T512-W after the significant 9 bits of word address is designated arbitrarily, by continuing
data input of 2 bytes or more, the address of insignificant 7 bits is incremented internally, and data up to 128 bytes can
be written.
・As for page write cycle of BR24T1M-W after page select bit ’P0’ and the significant 8 bit of word address are designated
arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 8 bits is incremented internally, and
data up to 256 bytes can be written.
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9/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
○Notes on page write cycle
List of numbers of page write
Number of Pages
8Byte
Product number
BR24T01-W
BR24T02-W
16Byte
32Byte
64Byte
128Byte
256Byte
BR24T04-W
BR24T08-W
BR24T16-W
BR24T32-W
BR24T64-W
BR24T128-W
BR24T256-W
BR24T512-W
BR24T1M-W
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
In the case BR24T256-W, 1 page=64bytes, but the page
write cycle time is 5ms at maximum for 64byte bulk write.
It does not stand 5ms at maximum × 64byte=320ms(Max.)
○Internal address increment
Page write mode (in the case of BR24T16-W)
0Eh
WA7
WA4
WA3
WA2
WA1
WA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
0
0
1
0
Significant bit is fixed.
No digit up
Increment
For example, when it is started from address 0Eh,
therefore, increment is made as below,
0Eh→0Fh→00h→01h･･･ which please note.
※0Eh･･･0E in hexadecimal, therefore,
00001110 becomes a binary number.
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data
rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do
not use it open.
In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.
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10/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a
command to read data by designating address, and is used generally. Current read cycle is a command to read data of
internal address register without designating address, and is used when to verify just after write cycle. In both the read
cycles, sequential read cycle is available, and the next address data can be read in succession.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
S
T
A
R
T
WORD
ADDRESS(n)
R A *1
/ C
WK
Note)
SLAVE
ADDRESS
S
T
O
P
DATA(n)
*1
WA
0
WA
7
1 0 1 0 A2A1A0
R
E
A
D
D7
1 0 1 0 A2A1A0
A
C
K
R A
/ C
WK
A
C
K
As for WA7,BR24T01-W become Don’t care.
D0
Fig.43 Random read cycle (BR24T01/02/04/08/16-W)
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0
WAWAWAWAWA
WA
15 14 13 12 11
0
R A
/ C
WK
Note)
2nd WORD
ADDRESS(n)
1st WORD
ADDRESS
（ ）
1 0 A2 A1 A0
S
T
A
R
T
A
C
K
*1
R
E
A
D
SLAVE
ADDRESS
10 1 0
DATA(n)
D7
A2 A1A0
A
C
K
S
T
O
P
D0
R A
/ C
W K
A
C
K
*1 As for WA12, BR24T32-W become Don’t care.
As for WA13, BR24T32/64-W become Don’t care.
As for WA14, BR24T32/64/128-W become Don’t care.
As for WA15, BR24T32/64/128/256-W become Don’t care.
Fig.44 Random read cycle (BR24T32/64/128/256/512/1M-W)
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 A2A1A0
S
T
O
P
DATA(n)
D7
D0
A
C
K
R A
/ C
WK
Note)
*1 As for WA7, BR24T01-W becomes Don't care.
*2 As for BR24T01/02-W becomes (n+7)
Fig.45 Current read cycle
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 A2 A1A0
D0
R A
/ C
W K
Note）
DATA(n+x)
DATA(n)
D7
S
T
O
P
D7
A
C
K
D0
A
C
K
A
C
K
*1
As for WA12, BR24T32-W becomes Don't care.
As for WA13, BR24T32/64-W becomes Don't care.
As for WA14, BR24T32/64/128-W becomes Don't care.
As for WA15, BR24T32/64/128/256-W becomes Don't care.
*2
As for BR24T128/256-W becomes (n+63)
As for BR24T512-W becomes (n+127)
As for BR24T1M-W becomes (n+255)
Fig.46 Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next
address data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL
signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Note)
*1
*2
*3
*1 *2 *3
1 0 1 0 A2 A1A0
In BR24T16-W, A2 becomes P2.
In BR24T08/16-W, A1 becomes P1.
In BR24T08/16/1M-W, A0 becomes P0.
Fig.47 Difference of slave address of each type
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11/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.48-(a), Fig.48-(b), Fig.48-(c).) In
dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'
level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading
to instantaneous power failure of system power source or influence upon devices.
Dummy clock×14
SCL
1
2
Start×2
13
Normal command
14
SDA
Normal command
Fig.48-(a) The case of dummy clock +START+START+ command input
SCL
Start
Dummy clock×9
Start
1
2
8
Normal command
9
SDA
Normal command
Fig.48-(b) The case of START +9 dummy clocks +START+ command input
Start×9
SCL
1
2
3
7
8
Normal command
9
SDA
Normal command
SD
Fig.48-(c) START×9+ command input
※Start command from START input.
●Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then
it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next
command can be executed without waiting for tWR = 5ms.
When to write continuously, R / W = 0, when to carry out current read cycle after write, slave address R / W = 1 is sent,
and if ACK signal sends back 'L', then execute word address input and data output and so forth.
During internal write,
ACK = HIGH is sent back.
First write command
S
T
A
R
T
Write command
S
T
O
P
S
T Slave
A
R address
T
S
T Slave
A
R address
T
A
C
K
H
A
C
K
H
…
tWR
Second write command
…
S
T Slave
A
R address
T
A
C
K
H
S
T Slave
A
R address
T
A
C
K
L
Word
address
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
After completion of internal write,
ACK=LOW is sent back, so input
next word address and data in
succession.
Fig.49 Case to continuously write by acknowledge polling
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2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. The area from the rise of SCL to take in D0 to input the stop condition is cancel
valid area. And, after execution of forced end by WP, standby status gets in.
・Rise of SDA
・Rise of D0 taken clock
SCL
SDA
SCL
D1
D0
ACK
SDA
S
T Slave
A
R address
T
A
C Word
K address
L
ACK
Enlarged view
Enlarged view
SDA
D0
A
C D7 D6 D5 D4 D3 D2 D1 D0
K
L
WP cancel invalid area
A
C
K
L
Data
A
C
K
L
S
T
O
P
WP cancel valid area
tWR
WP cancel invalid area
WP
Data is not written.
Fig.50 WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Fig.51)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Fig.51 Case of cancel by start, stop condition during slave address input
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13/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to
this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is
limited. The smaller the RPU, the larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
①SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by input leak total (IL) of device connected to bus at output of 'H' to
②The bus electric potential ○
SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including
recommended noise margin 0.2Vcc.
VCC－ILRPU－0.2 VCC ≧ VIH
0.8 VCC  VIH
 RPU 
IL
Ex.) VCC =3V IL=10µA VIH=0.7 VCC
from②
0 .8  3  0 .7  3
RPU 
10  10  6
Microcontroller
BR24TXX
RPU
SDA terminal
A
IL
 300 [kΩ]
IL
Bus line
capacity
CBUS
Fig.52 I/O circuit diagram
○ Minimum value of RPU
The minimum value of RPU is determined by the following factors.
When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
VCC  VOL
 IOL
RPU
VCC  VOL
 RPU 
IOL
②VOLMAX= should secure the input 'L' level (VIL) of microcontroller and EEPROM
including recommended noise margin 0.1Vcc.
VOLMAX ≦ VIL－0.1 VCC
Ex.) VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc
3  0 .4
from① RPU 
3  10  3

867[Ω]
And
VOL=0.4［V］
VIL=0.3×3
=0.9［V］
Therefore, the condition ② is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
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14/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Cautions on microcontroller connection
○RS
2
In I C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
ACK
RPU
SCL
RS
SDA
'H' output of microcontroller
EEPROM
Microcontroller
'L' output of EEPROM
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
Fig.53 I/O circuit diagram
Fig.54 Input / output collision timing
○Maximum value of Rs
The maximum value of Rs is determined by the following relations.
①SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
②The bus electric potential ○
sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC  VOL   VOL  0.1VCC  VIL
VCC
RPU  RS
RPU
RS
A
 RS 
VOL
VCC  VOL   RPU
1.1VCC  VIL
IOL
Ex)VCC=3V VIL=0.3VCC VOL=0.4V RPU=20kΩ
Bus line
capacity
CBUS
VIL
RS 
EEPROM
Micro controller
Fig.55 I/O Circuit Diagram
0 . 3  3  0 . 4  0 . 1 3
 20  103
1 . 1 3  0 . 3  3
 1.67[kΩ]
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
RPU
RS
VCC
I
RS
'L'output
 RS 
VCC
I
Over current I
EX) VCC=3V I=1mA
'H' output
RS 
Microcontroller
EEPROM
 300 [Ω]
Fig.56 I/O circuit diagram
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© 2011 ROHM Co., Ltd. All rights reserved.
3
10  10 3
15/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●I2C BUS input / output circuit
○Input (A0, A1, A2, SCL, WP)
Fig.57 Input pin circuit diagram
○Input / output (SDA)
Fig.58 Input / output pin circuit diagram
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16/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H’
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
Recommended conditions of tR, tOFF,Vbot
tR
tOFF
Vbot
0
Fig.59
tOFF
Vbot
10ms or below
10ms or larger
0.3V or below
100msor below
10msor larger
0.2V or below
Rise waveform diagram
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
Fig.60 When SCL= 'H' and SDA= 'L'
tSU:DAT
Fig.61 When SCL='L' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P12).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it
prevent data rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a bypass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as
possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
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17/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Notes for use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case
of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it
that conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that
of GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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18/21
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
●Order part number
B R
2
Part No.
4
T
1
Operating
temperature/
Power source
Voltage
BUS type
24：I2C
2
Capacity
01=1K
02=2K
04=4K
08=8K
16=16K
32=32K
-40℃~+85℃
1.7V~5.5V
8
F V T
64=64K
128=128K
256=256K
512=512K
1M=1024K
- W
Package
Blank :DIP-T8
F
:SOP8
FJ
:SOP-J8
FV
: SSOP-B8
FVT : TSSOP-B8
FVJ : TSSOP-B8J
FVM : MSOP8
NUX :VSON008X2030
Double
Cell
G
Halogen
Free
E
2
Packaging and forming specification
E2: Embossed tape and reel
(SOP8, SOP8-J8, SSOP-B8,
TSSOP-B8, TSSOP-B8J)
TR: Embossed tape and reel
(MSOP8, VSON008X2030)
None: Tube
(DIP-T8)
DIP-T8
<Tape and Reel information>
9.3±0.3
Tube
Quantity
2000pcs
Direction of feed
Direction of products is fixed in a container tube
5
6.5±0.3
8
Container
1
3.2±0.2 3.4±0.3
0.51Min.
4
7.62
0.3±0.1
0°−15°
2.54
0.5±0.1
∗ Order quantity needs to be multiple of the minimum quantity.
(Unit : mm)
SOP8
<Tape and Reel information>
7
6
5
+6°
4° −4°
6.2±0.3
4.4±0.2
0.3MIN
8
1 2
3
0.9±0.15
5.0±0.2
(MAX 5.35 include BURR)
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
0.595
1.5±0.1
+0.1
0.17 -0.05
S
S
0.11
0.1
1.27
1pin
0.42±0.1
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
SOP-J8
<Tape and Reel information>
4.9±0.2
(MAX 5.25 include BURR)
+6°
4° −4°
6
5
0.45MIN
7
3.9±0.2
6.0±0.3
8
1
2
3
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
4
0.545
0.2±0.1
0.175
1.375±0.1
S
1.27
0.42±0.1
0.1 S
1pin
Reel
(Unit : mm)
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19/21
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2011.03 - Rev.A
Technical Note
BR24T□□□□Series
TSSOP-B8
<Tape and Reel information>
3.0 ± 0.1
(MAX 3.35 include BURR)
8
7
6
4±4
3000pcs
2
3
4
1PIN MARK
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1.0±0.2
0.5±0.15
6.4±0.2
4.4±0.1
1
+0.05
0.145 −0.03
S
0.1±0.05
1.2MAX
Embossed carrier tape
Quantity
Direction
of feed
0.525
1.0±0.05
Tape
5
0.08 S
+0.05
0.245 −0.04
0.08
M
Direction of feed
1pin
0.65
Reel
(Unit : mm)
∗ Order quantity needs to be multiple of the minimum quantity.
TSSOP-B8J
<Tape and Reel information>
3.0 ± 0.1
(MAX 3.35 include BURR)
8
7
5
Embossed carrier tape
Quantity
2500pcs
2
3
4
1PIN MARK
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
0.95±0.2
0.45±0.15
3.0±0.1
4.9±0.2
+0.05
0.145 −0.03
0.525
S
0.1±0.05
0.85±0.05
Tape
Direction
of feed
1
1.1MAX
6
4±4
0.08 S
+0.05
0.32 −0.04
0.08
M
Direction of feed
1pin
0.65
Reel
(Unit : mm)
∗ Order quantity needs to be multiple of the minimum quantity.
MSOP8
<Tape and Reel information>
2.8±0.1
4.0±0.2
8 7 6 5
0.6±0.2
+6°
4° −4°
0.29±0.15
2.9±0.1
(MAX 3.25 include BURR)
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1 2 3 4
1PIN MARK
1pin
+0.05
0.145 −0.03
0.475
0.08±0.05
0.75±0.05
0.9MAX
S
+0.05
0.22 −0.04
0.08 S
Direction of feed
0.65
Reel
(Unit : mm)
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20/21
∗ Order quantity needs to be multiple of the minimum quantity.
2011.03 - Rev.A
Technical Note
BR24T□□□-W Series
VSON008X2030
<Tape and Reel information>
3.0±0.1
2.0±0.1
0.6MAX
1PIN MARK
0.25
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
(0.12)
+0.03
0.02 −0.02
1.5±0.1
4000pcs
0.5
1
4
8
5
1.4±0.1
0.3±0.1
C0.25
Embossed carrier tape
Quantity
Direction
of feed
S
0.08 S
Tape
1pin
+0.05
0.25 −0.04
Reel
(Unit : mm)
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Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2011.03 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
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R1120A