AD AD7691 250 ksps pulsar differential adc in msop/lfcsp Datasheet

18-Bit, 1.5 LSB INL, 250 kSPS PulSAR
Differential ADC in MSOP/LFCSP
AD7691
Data Sheet
FEATURES
APPLICATION DIAGRAM
APPLICATIONS
Battery-powered equipment
Data acquisitions
Seismic data acquisition systems
Instrumentation
Medical instruments
1.5
POSITIVE INL = 0.43LSB
NEGATIVE INL = –0.62LSB
1.0
+2.5V TO +5V
IN+
REF VDD VIO
SDI
IN–
SDO
SCK
±10V, ±5V, ...
GND
+1.8V TO VDD
3- OR 4-WIRE
INTERFACE
(SPI, DAISY CHAIN, CS)
CNV
ADA4941
AD7691
Figure 2.
Table 1. MSOP, LFCSP/SOT-23 14-/16-/18-Bit PulSAR® ADC
Type
18-Bit True
Differential
16-Bit True
Differential
16-Bit
Pseudo
Differential
14-Bit
Pseudo
Differential
100
kSPS
250
kSPS
AD7691
400 kSPS to
500 kSPS
AD7690
AD7684
AD7687
AD7680
AD7683
AD7685
AD7694
AD7688
AD7693
AD7686
AD7940
AD7942
≥1000
kSPS
AD7982
AD7984
AD7980
AD7946
ADC
Driver
ADA4941-1
ADA4841-2
ADA4941-1
ADA4841-2
ADA4841-1
ADA4841-1
GENERAL DESCRIPTION
The AD7691 1 is an 18-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single power supply, VDD, between 2.3 V and 5 V. It
contains a low power, high speed, 18-bit sampling ADC with no
missing codes, an internal conversion clock, and a versatile
serial interface port. On the CNV rising edge, it samples the
voltage difference between the IN+ and IN− pins. The voltages
on these pins swing in opposite phases between 0 V and REF.
The reference voltage, REF, is applied externally and can be set
up to the supply voltage.
The part’s power scales linearly with throughput.
0.5
INL (LSB)
+0.5V TO VDD
06146-001
18-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.75 LSB typical, ±1.5 LSB maximum (±6 ppm of FSR)
Dynamic range: 102 dB typical at 250 kSPS
Oversampled dynamic range: 125 dB at1 kSPS
Noise-free code resolution: 20 bits at 1 kSPS
Effective resolution: 22.7 bits at 1 kSPS
SINAD: 101.5 dB typical at 1 kHz
THD: −125 dB typical at 1 kHz
True differential analog input range: ±VREF
0 V to VREF with VREF up to VDD on both inputs
No pipeline delay
Single-supply 2.3 V to 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Proprietary serial interface
SPI/QSPI/MICROWIRE™/DSP compatible
Ability to daisy-chain multiple ADCs
Optional busy indicator feature
Power dissipation
1.35 mW at 2.5 V/100 kSPS, 4 mW at 5 V/100 kSPS
1.4 µW at 2.5 V/100 SPS
Standby current: 1 nA
10-lead packages: MSOP (MSOP-8 size) and
3 mm × 3 mm LFCSP (SOT-23 size)
Pin-for-pin compatible with the18-bit AD7690 and
16-bit AD7693, AD7688, and AD7687
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.
0
–0.5
The AD7691 is housed in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +85°C.
–1.5
0
65536
131072
196608
262144
CODE
06146-025
–1.0
1
Protected by U.S. Patent 6,703,961.
Figure 1. Integral Nonlinearity vs. Code, 5 V
Rev. E
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AD7691* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
REFERENCE MATERIALS
View a parametric search of comparable parts.
Product Selection Guide
EVALUATION KITS
Technical Articles
• AD7691 Evaluation Kit
• MS-1779: Nine Often Overlooked ADC Specifications
• Precision ADC PMOD Compatible Boards
• MS-2210: Designing Power Supplies for High Speed ADC
• SAR ADC & Driver Quick-Match Guide
DOCUMENTATION
Tutorials
Application Notes
• MT-001: Taking the Mystery out of the Infamous Formula,
"SNR=6.02N + 1.76dB", and Why You Should Care
• AN-742: Frequency Domain Response of SwitchedCapacitor ADCs
• MT-002: What the Nyquist Criterion Means to Your
Sampled Data System Design
• AN-931: Understanding PulSAR ADC Support Circuitry
• AN-932: Power Supply Sequencing
• MT-031: Grounding Data Converters and Solving the
Mystery of "AGND" and "DGND"
Data Sheet
• MT-074: Differential Drivers for Precision ADCs
• AD7691-DSCC: Military Data Sheet
• AD7691-EP: Enhanced Product Data Sheet
• AD7691: 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential
ADC in MSOP/LFCSP Data Sheet
DESIGN RESOURCES
• AD7691 Material Declaration
• PCN-PDN Information
Technical Books
• Quality And Reliability
• The Data Conversion Handbook, 2005
• Symbols and Footprints
User Guides
• UG-340: Evaluation Board for the 10-Lead Family 14-/16-/
18-Bit PulSAR ADCs
• UG-682: 6-Lead SOT-23 ADC Driver for the 8-/10-Lead
Family of 14-/16-/18-Bit PulSAR ADC Evaluation Boards
SOFTWARE AND SYSTEMS REQUIREMENTS
• AD7691 FMC-SDP Interposer & Evaluation Board / Xilinx
KC705 Reference Design
DISCUSSIONS
View all AD7691 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
• BeMicro FPGA Project for AD7691 with Nios driver
Submit a technical question or find your regional support
number.
TOOLS AND SIMULATIONS
DOCUMENT FEEDBACK
• AD7685 IBIS Models
Submit feedback for this data sheet.
REFERENCE DESIGNS
• CN0261
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AD7691
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 16
Applications ....................................................................................... 1
Single-to-Differential Driver .................................................... 16
Application Diagram ........................................................................ 1
Voltage Reference Input ............................................................ 16
General Description ......................................................................... 1
Power Supply............................................................................... 17
Revision History ............................................................................... 2
Supplying the ADC from the Reference.................................. 17
Specifications..................................................................................... 3
Digital Interface .......................................................................... 17
Timing Specifications .................................................................. 5
CS Mode, 3-Wire Without Busy Indicator ............................. 18
Absolute Maximum Ratings............................................................ 7
CS Mode, 3-Wire with Busy Indicator .................................... 19
Thermal Resistance ...................................................................... 7
CS Mode, 4-Wire Without Busy Indicator ............................. 20
ESD Caution .................................................................................. 7
CS Mode, 4-Wire with Busy Indicator .................................... 21
Pin Configurations and Function Descriptions ........................... 8
Chain Mode Without Busy Indicator ...................................... 22
Typical Performance Characteristics ............................................. 9
Chain Mode with Busy Indicator ............................................. 23
Terminology .................................................................................... 13
Application Hints ........................................................................... 24
Theory of Operation ...................................................................... 14
Layout .......................................................................................... 24
Circuit Information .................................................................... 14
Evaluating the AD7691 Performance ...................................... 24
Converter Operation .................................................................. 14
Outline Dimensions ....................................................................... 25
Typical Connection Diagram ................................................... 15
Ordering Guide .......................................................................... 25
Analog Inputs .............................................................................. 15
REVISION HISTORY
6/15—Rev. D to Rev. E
Change to Digital Interface Section ............................................. 17
Change to CS Mode, 3-Wire with Busy Indicator Section........ 19
Change to CS Mode, 4-Wire with Busy Indicator Section........ 21
Changes to the Ordering Guide.................................................... 25
7/14—Rev. C to Rev. D
Changed QFN (LFCSP) to LFCSP .............................. Throughout
Changes to Features Section............................................................ 1
Added Patent Note, Note 1 .............................................................. 1
Change to Acquisition Time Parameter, Table 5 .......................... 6
Changes to Evaluating the AD7691 Performance Section ........ 24
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
3/12—Rev. B to Rev. C
Change to Table 9 ........................................................................... 14
Changes to Ordering Guide .......................................................... 25
11/07—Rev. 0 to Rev. A
Deleted QFN Package in Development References ....... Universal
Changes to Features, Applications, Figure 1 and Figure 2 ...........1
Changes to Accuracy, Table 2 ..........................................................3
Changes to Power Dissipation, Table 3...........................................4
Added Thermal Resistance Section ................................................7
Changes to Figure 22...................................................................... 11
Changes to Format ......................................................................... 12
Changes to Terminology Section ................................................. 13
Changes to Format and Figure 29 ................................................ 15
Inserted Figure 31........................................................................... 15
Changes to Format ......................................................................... 17
Changes to Figure 44...................................................................... 22
Changes to Figure 46...................................................................... 23
Updated QFN Outline Dimensions ............................................. 25
Changes to Ordering Guide .......................................................... 25
7/06—Revision 0: Initial Version
7/11—Rev. A to Rev. B
Changes to Common-Mode Input Range Min Parameter ......... 3
Added EPAD Note to Figure 6 and Table 8................................... 8
Updated Outline Dimensions ....................................................... 25
Rev. E | Page 2 of 28
Data Sheet
AD7691
SPECIFICATIONS
VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range, VIN
Absolute Input Voltage
Common-Mode Input Range
Analog Input CMRR
Leakage Current at 25°C
Input Impedance 1
THROUGHPUT
Conversion Rate
Transient Response
ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
Gain Error 3
Gain Error Temperature Drift
Zero Error3
Zero Temperature Drift
Power Supply Sensitivity
AC ACCURACY 4
Dynamic Range
Oversampled Dynamic Range 5
Signal-to-Noise
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Conditions/Comments
Min
18
IN+ − (IN−)
IN+, IN−
IN+, IN−
fIN = 250 kHz
Acquisition phase
−VREF
−0.1
VREF/2 − 0.1
VDD = 4.5 V to 5.25 V
VDD = 2.3 V to 4.5 V
Full-scale step
0
0
18
−1.5
−1
REF = VDD = 5 V
VDD = 4.5 V to 5.25 V
VDD = 2.3 V to 4.5 V
−40
−80
VDD = 4.5 V to 5.25 V
VDD = 2.3 V to 4.5 V
−0.8
−3.5
VDD = 5 V ± 5%
VREF = 5 V
fIN = 1 kSPS
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
Intermodulation Distortion 6
101
100
95
100
95
Typ
VREF/2
65
1
±0.75
±0.5
0.75
±2
±2
±0.3
±0.1
±0.7
±0.3
±0.25
Max
Unit
Bits
+VREF
VREF + 0.1
VREF/2 + 0.1
V
V
V
dB
nA
250
180
1.8
kSPS
kSPS
μs
+1.5
+1.25
+40
+80
+0.8
+3.5
102
125
101.5
96.5
−125
−118
101.5
96.5
115
See the Analog Inputs section.
LSB means least significant bit. With the ±5 V input range, one LSB is 38.15 µV.
3
See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
4
All ac accuracy specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5
Dynamic range obtained by oversampling the ADC running at a throughput fS of 250 kSPS, followed by postdigital filtering with an output word rate fO.
6
fIN1 = 21.4 kHz and fIN2 = 18.9 kHz, with each tone at −7 dB below full scale.
1
2
Rev. E | Page 3 of 28
Bits
LSB 2
LSB2
LSB2
LSB2
LSB2
ppm/°C
mV
mV
ppm/°C
LSB2
dB
dB
dB
dB
dB
dB
dB
dB
dB
AD7691
Data Sheet
VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay 1
VOL
VOH
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current 2, 3
Power Dissipation
Energy per Conversion
TEMPERATURE RANGE 4
Specified Performance
Conditions/Comments
Min
Typ
0.5
Max
Unit
VDD + 0.3
250 kSPS, REF = 5 V
60
V
µA
VDD = 5 V
2
2.5
MHz
ns
−0.3
0.7 × VIO
−1
−1
+0.3 × VIO
VIO + 0.3
+1
+1
V
V
µA
µA
0.4
V
V
5.25
VDD + 0.3
VDD + 0.3
50
V
V
V
nA
µW
mW
mW
mW
mW
nJ/sample
Serial 18-bit, twos complement
ISINK = +500 µA
ISOURCE = −500 µA
VIO − 0.3
Specified performance
Specified performance
2.3
2.3
1.8
VDD and VIO = 5 V, TA = 25°C
VDD = 2.5 V, 100 SPS throughput
VDD = 2.5 V, 100 kSPS throughput
VDD = 2.5 V, 180 kSPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 250 kSPS throughput
TMIN to TMAX
1
1.4
1.35
2.4
4.24
10.6
50
−40
Conversion results are available immediately after completed conversion.
With all digital inputs forced to VIO or GND as required.
3
During acquisition phase.
4
Contact an Analog Devices, Inc., sales representative for the extended temperature range.
1
2
Rev. E | Page 4 of 28
5
12.5
+85
°C
Data Sheet
AD7691
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. 1
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
VIO Above 2.3 V
1
See Figure 3 and Figure 4 for load conditions.
Rev. E | Page 5 of 28
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
0.5
1.8
4
10
15
Typ
Max
2.2
17
18
19
20
7
7
4
Unit
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
15
16
17
ns
ns
ns
ns
15
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
26
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
10
3
4
AD7691
Data Sheet
VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. 1
Table 5.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
tSCKL
tSCKH
tHSDO
tDSDO
Min
0.5
1.8
5.5
10
25
Typ
Max
3.7
29
35
40
12
12
5
Unit
µs
μs
µs
ns
ns
ns
ns
ns
ns
ns
ns
24
30
35
ns
ns
ns
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
30
0
5
8
8
10
36
See Figure 3 and Figure 4 for load conditions.
70% VIO
IOL
30% VIO
tDELAY
tDELAY
1.4V
TO SDO
CL
50pF
500µA
IOH
2V OR VIO – 0.5V1
2V OR VIO – 0.5V1
0.8V OR 0.5V2
0.8V OR 0.5V2
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO
VIO BELOW 2.5V.
BELOW 2.5V.
Figure 4. Voltage Levels for Timing
Figure 3. Load Circuit for Digital Interface Timing
Rev. E | Page 6 of 28
06146-003
500µA
06146-002
1
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
Data Sheet
AD7691
ABSOLUTE MAXIMUM RATINGS
Thermal Resistance
Table 6.
Parameter
Analog Inputs (IN+, IN−)1
REF
Supply Voltages
VDD, VIO to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
Lead Temperature Range
1
Rating
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
GND − 0.3 V to VDD + 0.3 V
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type
10-Lead MSOP
10-Lead LFCSP
−0.3 V to +7 V
±7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
JEDEC J-STD-20
ESD CAUTION
See the Analog Inputs section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Rev. E | Page 7 of 28
θJA
200
43.4
θJC
44
6.5
Unit
°C/W
°C/W
AD7691
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1
IN+ 3
REF 1
10 VIO
IN– 4
VDD 2
AD7691
9
SDI
GND 5
TOP VIEW
(Not to Scale)
8
SCK
7
SDO
6
CNV
IN– 4
GND 5
AD7691
TOP VIEW
(Not to Scale)
9
SDI
8
SCK
7
SDO
6
CNV
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED RELIABILITY OF
THE SOLDER JOINTS, IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO THE GROUND PLANE.
06146-004
IN+ 3
10 VIO
Figure 5. 10-Lead MSOP Pin Configuration
06146-005
VDD 2
Figure 6. 10-Lead LFCSP Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type1
AI
2
3
VDD
IN+
P
AI
4
IN−
AI
5
6
GND
CNV
P
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
10
VIO
P
EPAD
Description
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin.
This pin should be decoupled closely to the pin with a 10 μF capacitor.
Power Supply.
Differential Positive Analog Input. Referenced to IN−. The input range for IN+ is between 0 V and VREF,
centered about VREF/2 and must be driven 180° out of phase with IN−.
Differential Negative Analog Input. Referenced to IN+. The input range for IN− is between 0 V and VREF,
centered about VREF/2 and must be driven 180° out of phase with IN+.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the part, either chain or CS mode. In CS mode, it enables the SDO pin when
low. In chain mode, the data should be read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface
(1.8 V, 2.5 V, 3 V, or 5 V).
Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints, it is
recommended that the pad be soldered to the ground plane.
1
AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. E | Page 8 of 28
Data Sheet
AD7691
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.5
POSITIVE DNL = 0.37LSB
NEGATIVE DNL = –0.33LSB
POSITIVE INL = 0.39LSB
NEGATIVE INL = –0.73LSB
1.0
0.5
DNL (LSB)
INL (LSB)
0.5
0
0
–0.5
–0.5
–1.0
131072
196608
262144
–1.0
CODE
65536
0
131072
Figure 10. Differential Nonlinearity vs. Code, 5 V
80k
45k
VDD = REF = 5V
σ = 0.76LSB
69769
70k
40k
30k
28179
COUNTS
50k
40k
28527
30k
24411
25k
20k
17460
27770
14362
15k
20k
10k
5k
0
26
25
26
27
2904
28
2062
29
2A
2B
2C
14
0
0
2D
2E
2F
CODE IN HEX
0
06146-027
0
4055
2997
0
12
910 78
29 501
9
0
23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31
CODE IN HEX
Figure 8. Histogram of a DC Input at the Code Center, 5 V
06146-030
10k
Figure 11. Histogram of a DC Input at the Code Center, 2.5 V
0
0
32768 POINT FFT
VDD = REF = 5V
fS = 250kSPS
fIN = 2kHz
SNR = 101.4dB
THD = –120.1dB
2ND HARMONIC = –140.7dB
3RD HARMONIC = –120.3dB
–40
–60
32768 POINT FFT
VDD = REF = 2.5V
fS = 180kSPS
fIN = 2kHz
SNR = 96.4dB
THD = –120.3dB
2ND HARMONIC = –132.5dB
3RD HARMONIC = –121.2dB
–20
AMPLITUDE (dB of Full Scale)
–20
–80
–100
–120
–140
–160
–40
–60
–80
–100
–120
–140
–160
0
20
40
60
80
FREQUENCY (kHz)
100
120
–180
06146-028
–180
0
10
20
30
40
50
60
FREQUENCY (kHz)
Figure 9. 2 kHz FFT Plot, 5 V
Figure 12. 2 kHz FFT Plot, 2.5 V
Rev. E | Page 9 of 28
70
80
90
06146-031
COUNTS
VDD = REF = 2.5V
σ = 1.42LSB
38068
35k
60k
AMPLITUDE (dB of Full Scale)
262144
CODE
Figure 7. Integral Nonlinearity vs. Code 2.5 V
0
196608
06146-029
65536
0
06146-026
–1.5
AD7691
Data Sheet
104
–105
18
SNR
102
–110
100
17
96
16
94
ENOB (Bits)
ENOB
THD, SFDR (dB)
98
92
–115
THD
–120
–125
15
90
–130
88
2.9
3.2
3.5
3.8
4.1
4.7
4.4
5.0
14
5.3
–135
2.3
06146-032
2.6
REFERENCE VOLTAGE (V)
2.6
2.9
3.2
3.5
3.8
4.1
4.4
4.7
5.0
5.3
105
125
REFERENCE VOLTAGE (V)
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
06146-038
SFDR
86
2.3
Figure 16. THD, SFDR vs. Reference Voltage
105
–90
VREF = 5V
100
–100
95
THD (dB)
SNR (dB)
VREF = 2.5V
90
–110
VREF = 5V
–120
85
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
–130
–55
06146-033
–35
–35
–15
5
25
45
65
85
TEMPERATURE (°C)
Figure 14. SNR vs. Temperature
06146-039
VREF = 2.5V
80
–55
Figure 17. THD vs. Temperature
105
–60
VREF = 5V, –10dB
VREF = 5V, –1dB
100
–70
95
–80
VREF = 5V, –1dB
VREF = 2.5V, –1dB
VREF = 2.5V, –10dB
85
–90
–100
80
–110
75
–120
70
0
25
50
75
FREQUENCY (kHz)
100
125
Figure 15. SINAD vs. Frequency
VREF = 2.5V, –10dB
VREF = 5V, –10dB
–130
0
25
50
75
FREQUENCY (kHz)
Figure 18. THD vs. Frequency
Rev. E | Page 10 of 28
100
125
06146-040
THD (dB)
VREF = 2.5V, –1dB
90
06146-037
SINAD (dB)
SNR, SINAD (dB)
SINAD
Data Sheet
AD7691
105
6
–90
SNR 5V
GAIN ERROR
–95
102
SNR 2.5V
99
–100
–110
93
THD 5V
90
–115
87
–120
2
0
–2
–4
THD 2.5V
84
THD (dB)
–105
96
SNR (dB)
OFFSET, GAIN ERROR (LSB)
4
–125
–8
–6
–4
0
–2
–6
–55
06146-041
–130
INPUT LEVEL (dB)
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 19. SNR, THD vs. Input Level
Figure 22. Zero Error, Gain Error vs. Temperature
1000
1000
fS =100kSPS
POWER-DOWN CURRENT (nA)
VDD = 5V
750
VDD = 2.5V
500
250
750
500
250
VDD + VIO
VIO
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
06146-042
0
–55
0
–55
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
06146-047
OPERATING CURRENT (µA)
–35
06146-044
OFFSET ERROR
81
–10
Figure 23. Power-Down Current vs. Temperature
Figure 20. Operating Current vs. Temperature
25
1000
fS =100kSPS
tDSDO DELAY (ns)
500
250
15
VDD = 5V, 85°C
10
VDD = 5V, 25°C
5
2.6
2.9
3.2
3.5
3.8
4.1
SUPPLY (V)
4.4
4.7
5.0
5.3
0
0
20
40
60
80
SDO CAPACITIVE LOAD (pF)
100
Figure 24. tDSDO Delay vs. Capacitance Load and Supply
Figure 21. Operating Current vs. Supply
Rev. E | Page 11 of 28
120
06146-034
VIO
0
2.3
06146-043
OPERATING CURRENT (µA)
20
VDD
750
AD7691
Data Sheet
90
95
VREF = VDD = 5V
85
90
80
75
CMRR (dB)
80
75
70
65
60
55
50
70
65
1
10
100
1000
FREQUENCY (kHz)
10000
Figure 25. PSSR vs. Frequency
40
1
10
100
1000
FREQUENCY (kHz)
Figure 26. Analog Input CMRR vs. Frequency
Rev. E | Page 12 of 28
10000
06146-036
45
06146-035
PSRR (dB)
85
Data Sheet
AD7691
TERMINOLOGY
Least Significant Bit (LSB)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For an analog-to-digital
converter with N bits of resolution, the LSB expressed in volts is
LSB(V) =
V INpp
2N
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 28).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
Gain Error
The first transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level ½ LSB above nominal negative full scale (−4.999981 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999943 V for the ±5 V range). The gain
error is the deviation in LSBs (or % of full-scale range) of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels. The closely related full-scale error, which is
expressed also in LSBs or % of full-scale range, includes the
contribution from the zero error.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
Noise-Free Code Resolution
It is the number of bits beyond which it is impossible to resolve
individual codes distinctly. It is calculated as
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Effective Resolution
It is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to acquire
its input accurately after a full-scale step function is applied.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Rev. E | Page 13 of 28
AD7691
Data Sheet
THEORY OF OPERATION
IN+
SWITCHES CONTROL
MSB
131,072C 65,536C
LSB
4C
2C
C
SW+
C
BUSY
REF
COMP
GND
131,072C 65,536C
4C
2C
C
CONTROL
LOGIC
OUTPUT CODE
C
MSB
LSB
SW–
06146-024
CNV
IN–
Figure 27. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7691 is a fast, low power, single-supply, precise, 18-bit
ADC using a successive approximation architecture.
The part is capable of converting 250,000 samples per second
(250 kSPS) and powers down between conversions. When
operating at 1 kSPS, for example, it consumes 50 µW typically,
which is ideal for battery-powered applications.
The AD7691 provides the user with an on-chip track-and-hold
and does not exhibit pipeline delay or latency, making it ideal
for multiple multiplexed channel applications.
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the
acquisition phase, and the control logic generates the ADC
output code and a busy signal indicator.
Because the AD7691 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Transfer Functions
The ideal transfer characteristic for the AD7691 is shown in
Figure 28 and Table 9.
ADC CODE (TWOS COMPLEMENT)
The AD7691 is specified from 2.3 V to 5.25 V and can be
interfaced to any 1.8 V to 5 V digital logic family. It is housed in
a 10-lead MSOP or a tiny 10-lead LFCSP that combines space
savings and allows flexible configurations.
The part is pin-for-pin compatible with the 18-bit AD7690 as
well as the 16-bit AD7687 and AD7688.
CONVERTER OPERATION
The AD7691 is a successive approximation ADC based on a
charge redistribution DAC. Figure 27 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary-weighted capacitors, which are
connected to the two comparator inputs.
011...111
011...110
011...101
100...010
100...000
–FSR
–FSR + 1LSB
+FSR – 1LSB
+FSR – 1.5LSB
–FSR + 0.5LSB
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/262,144).
ANALOG INPUT
06146-006
100...001
Figure 28. ADC Ideal Transfer Function
Table 9. Output Codes and Ideal Input Voltages
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
1
2
Analog Input
VREF = 5 V
+4.999962 V
+38.15 µV
0V
−38.15 µV
−4.999962 V
−5 V
Digital Output
Code (Hex)
0x1FFFF1
0x00001
0x00000
0x3FFFF
0x20001
0x200002
This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
Rev. E | Page 14 of 28
Data Sheet
AD7691
TYPICAL CONNECTION DIAGRAM
Figure 29 shows an example of the recommended connection diagram for the AD7691 when multiple supplies are available.
V+
REF1
5V
10µF2
100nF
V+
1.8V TO VDD
100nF
15Ω
REF
0 TO VREF
VDD
IN+
ADA4841-2 3
2.7nF
V–
AD7691
SCK
3- OR 4-WIRE INTERFACE5
SDO
4
V+
VIO
SDI
IN–
CNV
GND
15Ω
VREF TO 0
ADA4841-2 3
2.7nF
V–
4
06146-008
1 SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2C
REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3 SEE TABLE 9 FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4 OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
5 SEE THE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE.
Figure 29. Typical Application Diagram with Multiple Supplies
ANALOG INPUTS
Figure 30 shows an equivalent circuit of the input structure of
the AD7691.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the supply rails by more
than 0.3 V because this causes the diodes to become forward
biased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur if the input buffer (U1)
supplies are different from VDD. In such a case (for example, an
input buffer with a short circuit), the current limitation can be
used to protect the part.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a
1-pole, low-pass filter that reduces undesirable aliasing effects
and limits noise.
When the source impedance of the driving circuit is low, the
AD7691 can be driven directly. Large source impedances
significantly affect the ac performance, especially total harmonic
distortion (THD). The dc performances are less sensitive to
the input impedance. The maximum source impedance
depends on the amount of THD that can be tolerated.
The THD degrades as a function of the source impedance and
the maximum input frequency as shown in Figure 31.
–80
VDD
RIN
–90
CIN
–95
250Ω
GND
Figure 30. Equivalent Analog Input Circuit
THD (dB)
D2
06146-007
CPIN
–100
33Ω
–110
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
–115
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination
of the capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 3 kΩ and is a lumped component composed of
serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
–130
Rev. E | Page 15 of 28
100Ω
–105
15Ω
50Ω
–120
–125
0
10
20
30
40
50
60
70
80
90
FREQUENCY (kHz)
Figure 31. THD vs. Analog Input Frequency and Source Resistance
06146-009
D1
IN+
OR IN–
VREF = VDD 5V
–85
AD7691
Data Sheet
DRIVER AMPLIFIER CHOICE
SINGLE-TO-DIFFERENTIAL DRIVER
Although the AD7691 is easy to drive, the driver amplifier must
meet the following requirements:
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-1 single-ended-to-differential
driver allows for a differential input into the part. The schematic
is shown in Figure 32.
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7691. The noise coming from
the driver is filtered by the AD7691 analog input circuit’s
1-pole, low-pass filter made by RIN and CIN or by the
external filter, if one is used. The SNR degradation due to
the amplifier is as follows:
R5
R6
R3
R4
+5V REF
10µF
15Ω
SNRLOSS =
2.7nF


V NADC
20 log 
π
π
 V NADC 2  f 3 dB (Ne N  ) 2  f 3 dB (Ne N  ) 2
2
2







REF
VDD
AD7691
IN–
GND
R1
R2
CF
VINpp
Figure 32. Single-Ended-to-Differential Driver Circuit
2 2
R1 and R2 set the attenuation ratio between the input range and
the ADC range (VREF). R1, R2, and CF are chosen depending on
the desired input resistance, signal bandwidth, antialiasing, and
noise contribution. For example, for the ±10 V range with a 4 kΩ
impedance, R2 = 1 kΩ and R1 = 4 kΩ.
SNR
10 20
f−3 dB is the input bandwidth, in MHz, of the AD7691 (2 MHz)
or the cutoff frequency of the input filter, if one is used.
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).
eN+ and eN− are the equivalent input noise voltage densities
of the op amps connected to IN+ and IN−, in nV/√Hz.

15Ω
IN+
ADA4941
VNADC is the noise of the ADC, in μV, given by the following:

2.7nF
100nF
±10V, ±5V, ...
where:
VNADC 
+5.2V
+5.2V
100nF
06146-010

This approximation can be used when the resistances around
the amplifier are small. If larger resistances are used, their
noise contributions should also be root-sum-squared.
For ac applications, the driver should have a THD
performance commensurate with the AD7691.
For multichannel multiplexed applications, the driver
amplifier and the AD7691 analog input circuit must settle
for a full-scale step onto the capacitor array at an 18-bit
level (0.0004%, 4 ppm). In the amplifier’s data sheet,
settling at 0.1% to 0.01% is more commonly specified. This
may differ significantly from the settling time at an 18-bit
level and should be verified prior to driver selection.
Table 10. Recommended Driver Amplifiers
Amplifier
ADA4941-1
ADA4841-2
AD8655
AD8021
AD8022
OP184
AD8605, AD8615
Typical Application
Very low noise, low power single-ended-todifferential
Very low noise, small, and low power
5 V single supply, low noise
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single supply, low power
R3 and R4 set the common mode on the IN− input, and R5 and
R6 set the common mode on the IN+ input of the ADC. The
common mode should be set close to VREF/2; however, if single
supply is desired, it can be set slightly above VREF/2 to provide
some headroom for the ADA4941-1 output stage. For example,
for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 =
11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ.
VOLTAGE REFERENCE INPUT
The AD7691 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8605, a
10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR431, ADR433,
ADR434, and ADR435 reference.
If desired, smaller reference decoupling capacitor values as low
as 2.2 μF can be used with a minimal impact on performance,
especially DNL.
Rev. E | Page 16 of 28
Data Sheet
AD7691
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
5V
10Ω
POWER SUPPLY
5V
The AD7691 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and VDD. To reduce the
supplies needed, the VIO and VDD pins can be tied together. The
AD7691 is independent of power supply sequencing between VIO
and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 25.
The AD7691 powers down automatically at the end of each
conversion phase, and therefore, the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rate (as low as a few hertz) and low battery-powered applications.
10
VIO
0.1
1k
10k
100k
1M
SAMPLING RATE (SPS)
06146-045
OPERATING CURRENT (µA)
VDD = 5V
100
Figure 33. Operating Current vs. Sample Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7691, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 34. The reference line can be driven by



10kΩ
1µF
AD8031
10µF
1µF
1
REF
VDD
VIO
1OPTIONAL
REFERENCE BUFFER AND FILTER.
06146-046
AD7691
Figure 34. Example of an Application Circuit
DIGITAL INTERFACE
Though the AD7691 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7691 is compatible with SPI, QSPI™,
digital hosts, and DSPs, for example, the Blackfin® processors or
the high performance, mixed-signal DSP family. In this mode,
the AD7691 can use either a 3-wire or 4-wire interface. A 3wire interface using the CNV, SCK, and SDO signals minimizes
wiring connections and is useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
1000
0.001
10
5V
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR431, ADR433, ADR434, and ADR435.
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 34.
When in chain mode, the AD7691 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the device operates depends on the SDI
level when the CNV rising edge occurs. The CS mode is
selected if SDI is high, and the chain mode is selected if SDI is
low. The SDI hold time is such that when SDI and CNV are
connected together, the chain mode is selected.
The initial state of SDO on power up is indeterminate.
Therefore, in order to put SDO in a known state, a conversion
must be initiated and all data bits clocked out.
In either mode, the AD7691 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.
The busy indicator feature is enabled


Rev. E | Page 17 of 28
In the CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 38 and Figure 42).
In the chain mode if SCK is high during the CNV rising
edge (see Figure 46).
AD7691
Data Sheet
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge can allow a faster reading rate, provided it has
an acceptable hold time. After the 18th SCK falling edge, or
when CNV goes high, whichever occurs first, SDO returns to
high impedance.
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 35, and the corresponding timing is given in
Figure 36.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers, but CNV must be returned high before
the minimum conversion time elapses and then held high for
the maximum possible conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete,
the AD7691 enters the acquisition phase and powers down.
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are clocked by subsequent SCK falling
CONVERT
DIGITAL HOST
CNV
VIO
SDI
AD7691
DATA IN
SDO
06146-011
SCK
CLK
Figure 35. 3-Wire CS Mode Without Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
16
tHSDO
18
tSCKH
tDSDO
tEN
SDO
17
D17
D16
D15
tDIS
D1
D0
Figure 36. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)
Rev. E | Page 18 of 28
06146-012
SCK
Data Sheet
AD7691
SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge can allow a faster reading
rate, provided it has an acceptable hold time. After the optional
19th SCK falling edge, or when CNV goes high, whichever
occurs first, SDO returns to high impedance.
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 37, and the
corresponding timing is given in Figure 38.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can select other
SPI devices, such as analog multiplexers, but CNV must be
returned low before the minimum conversion time elapses and
then held low for the maximum possible conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low
impedance. With a pull-up on the SDO line, this transition is
used as an interrupt signal to initiate the data reading controlled
by the digital host. When using this option, select the value of
the pull-up resistor such that it maintains an appropriate rise
time on the SDO line for the application. This is a function of
the resistance of the pull-up and the capacitance of the SDO
line. The AD7691 then enters the acquisition phase and powers
down. The data bits are clocked out, MSB first, by subsequent
If multiple AD7691 devices are selected at the same time, the
SDO output pin handles this contention without damage or
induced latch-up. Meanwhile, it is recommended to keep this
contention as short as possible to limit extra power dissipation.
CONVERT
VIO
DIGITAL HOST
CNV
VIO
47kΩ
AD7691
DATA IN
SDO
SCK
IRQ
06146-013
SDI
CLK
Figure 37. 3-Wire CS Mode with Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
17
tHSDO
18
19
tSCKH
tDSDO
SDO
D17
D16
tDIS
D1
D0
Figure 38. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High)
Rev. E | Page 19 of 28
06146-014
SCK
AD7691
Data Sheet
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7691 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 18th SCK
falling edge, or when SDI goes high, whichever occurs first, SDO
returns to high impedance and another AD7691 is read.
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7691 devices are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7691devices is
shown in Figure 39, and the corresponding timing is given in
Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
CS2
CS1
CONVERT
CNV
SDI
AD7691
DIGITAL HOST
CNV
SDO
SDI
AD7691
SCK
SDO
SCK
06146-015
DATA IN
CLK
Figure 39. 4-Wire CS Mode Without Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI (CS1)
tHSDICNV
SDI (CS2)
tSCK
tSCKL
1
2
16
3
tHSDO
18
19
20
D1
D0
D17
D16
34
35
36
D1
D0
tDSDO
tEN
SDO
17
tSCKH
D17
D16
D15
tDIS
Figure 40. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing
Rev. E | Page 20 of 28
06146-016
SCK
Data Sheet
AD7691
maintains an appropriate rise time on the SDO line for the
application. This is a function of the resistance of the pull-up
and the capacitance of the SDO line. The AD7691 then enters
the acquisition phase and powers down. The data bits are
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge is
used to capture the data, a digital host using the SCK falling
edge can allow a faster reading rate, provided it has an
acceptable hold time. After the optional 19th SCK falling edge,
or SDI going high, whichever occurs first, SDO returns to high
impedance.
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is normally used when a single AD7691 is connected
to an SPI-compatible digital host with an interrupt input, and it
is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This requirement is particularly important in applications
where low jitter on CNV is desired.
The connection diagram is shown in Figure 41, and the
corresponding timing is given in Figure 42.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition is used as an interrupt signal to initiate the
data readback controlled by the digital host. When using this
option, select the value of the pull-up resistor such that it
CS1
CONVERT
VIO
DIGITAL HOST
CNV
AD7691
DATA IN
SDO
SCK
IRQ
06146-017
SDI
47kΩ
CLK
Figure 41. 4-Wire CS Mode with Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
1
2
3
tHSDO
17
18
19
tSCKH
tDSDO
tDIS
tEN
SDO
D17
D16
D1
Figure 42. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
Rev. E | Page 21 of 28
D0
06146-018
SCK
AD7691
Data Sheet
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7691 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge can allow a faster reading
rate and, consequently, more AD7691 devices in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time.
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7691 devices
on a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7691 devices is
shown in Figure 43, and the corresponding timing is given in
Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
CONVERT
CNV
AD7691
AD7691
A
SDO
SDI
DIGITAL HOST
SDO
B
SCK
DATA IN
SCK
06146-019
SDI
CNV
CLK
Figure 43. Chain Mode Without Busy Indicator Connection Diagram
SDIA = 0
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
tHSCKCNV
2
3
16
17
tSSDISCK
18
19
20
DA17
DA16
34
35
36
DA1
DA0
tSCKH
tHSDISCK
tEN
SDOA = SDIB
DA17
DA16
DA15
DA1
DA0
DB17
DB16
DB15
DB1
DB0
SDOB
Figure 44. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. E | Page 22 of 28
06146-020
tHSDO
tDSDO
Data Sheet
AD7691
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7691 ADC labeled C in Figure 45) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7691 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N + 1 clocks are required to
readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate and, consequently, more AD7691 devices
in the chain, provided the digital host has an acceptable hold
time.
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7691
devices on a 3-wire serial interface while providing a busy
indicator. This feature is useful for reducing component count
and wiring connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register.
A connection diagram example using three AD7691 devices is
shown in Figure 45, and the corresponding timing is given in
Figure 46.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
CONVERT
SDI
AD7691
A
CNV
SDO
SDI
SCK
AD7691
B
DIGITAL HOST
CNV
SDO
SDI
AD7691
SCK
C
DATA IN
SDO
SCK
IRQ
06146-021
CNV
CLK
Figure 45. Chain Mode with Busy Indicator Connection Diagram
tCYC
ACQUISITION
tCONV
tACQ
ACQUISITION
CONVERSION
tSSCKCNV
SCK
tHSCKCNV
tSCKH
1
tEN
SDOA = SDIB
SDOB = SDIC
tDSDOSDI
2
tSSDISCK
3
4
tSCK
17
18
19
20
21
35
36
37
38
39
tSCKL
tHSDISCK
54
55
tDSDOSDI
DA17 DA16 DA15
DA1
DA0
DB17 DB16 DB15
DB1
DB0 DA17 DA16
DA1
DA0
DC17 DC16 DC15
DC1
DC0 DB17 DB16
DB1
DB0 DA17 DA16
tHSDO
tDSDO
tDSDOSDI
tDSDOSDI
SDOC
53
tDSDOSDI
Figure 46. Chain Mode with Busy Indicator Serial Interface Timing
Rev. E | Page 23 of 28
DA1
DA0
06146-022
CNV = SDIA
AD7691
Data Sheet
APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7691 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pin
configuration of the AD7691, with its analog signals on the left
side and its digital signals on the right side, eases this task.
Avoid running digital lines under the device because this couples
noise onto the die unless a ground plane under the AD7691 is
used as a shield. Fast switching signals, such as CNV or clocks,
should not run near analog signal paths. Crossover of digital
and analog signals should be avoided.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the latter case,
the planes should be joined underneath the AD7691.
Figure 47. Example Layout of the AD7691 (Top Layer)
The AD7691 voltage reference input, REF, has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the power supplies, VDD and VIO, of the AD7691
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7691 and connected using short, wide
traces to provide low impedance paths and to reduce the effect
of glitches on the power supply lines.
An example layout following these rules is shown in Figure 47
and Figure 48.
EVALUATING THE AD7691 PERFORMANCE
Other recommended layouts for the AD7691 are outlined
in the documentation of the evaluation board for the AD7691
(EVAL-AD7691SDZ). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-SDP-CB1Z.
Rev. E | Page 24 of 28
Figure 48. Example Layout of the AD7691 (Bottom Layer)
Data Sheet
AD7691
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
0.70
0.55
0.40
0.23
0.13
6°
0°
091709-A
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 49.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
BOTTOM VIEW
0.80
0.75
0.70
SEATING
PLANE
0.30
0.25
0.20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-C
TOP VIEW
0.20 REF
Figure 50. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2, 3
AD7691BCPZRL
AD7691BCPZRL7
AD7691BRMZ
AD7691BRMZ-RL7
EVAL-AD7691SDZ
EVAL-SDP-CB1Z
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
Evaluation Board
Controller Board
Package Option
CP-10-9
CP-10-9
RM-10
RM-10
Branding
C4E
C4E
C4E
C4E
Ordering Quantity
Reel, 5,000
Reel, 1,500
Tube, 50
Reel, 1,000
Z = RoHS Compliant Part.
The EVAL-AD7691SDZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
3
The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.
1
2
Rev. E | Page 25 of 28
AD7691
Data Sheet
NOTES
Rev. E | Page 26 of 28
Data Sheet
AD7691
NOTES
Rev. E | Page 27 of 28
AD7691
Data Sheet
NOTES
©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06146-0-6/15(E)
Rev. E | Page 28 of 28