Cypress CY7C1472BV33-250BZI 72-mbit (2m x 36/4m x 18/1m x 72) pipelined sram with nobl architecture Datasheet

CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■
Pin-compatible and functionally equivalent to ZBT™
■
Supports 250 MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
■
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■
Fully registered (inputs and outputs) for pipelined operation
■
Byte Write capability
■
Single 3.3V power supply
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back read
or write operations with no wait states. The CY7C1470BV33,
CY7C1472BV33, and CY7C1474BV33 are equipped with the
advanced (NoBL) logic required to enable consecutive read or
write operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data in
systems that require frequent read or write transitions. The
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are pin
compatible and functionally equivalent to ZBT devices.
■
3.3V/2.5V IO power supply
■
Fast clock-to-output time
❐ 3.0 ns (for 250-MHz device)
■
Clock Enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
CY7C1470BV33, CY7C1472BV33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1474BV33
available in Pb-free and non-Pb-free 209-ball FBGA package
■
IEEE 1149.1 JTAG Boundary Scan compatible
■
Burst capability—linear or interleaved burst order
■
“ZZ” Sleep Mode option and Stop Clock option
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the Byte Write Selects
for
CY7C1470BV33,
BWa–BWb
for
(BWa–BWd
CY7C1472BV33, and BWa–BWh for CY7C1474BV33) and a
Write Enable (WE) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
Document #: 001-15031 Rev. *C
250 MHz
3.0
500
120
•
198 Champion Court
200 MHz
3.0
500
120
•
167 MHz
3.4
450
120
Unit
ns
mA
mA
San Jose, CA 95134-1709
•
408-943-2600
Revised February 29, 2008
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Logic Block Diagram – CY7C1470BV33 (2M x 36)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
ADV/LD
C
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW a
BW b
BW c
BW d
WRITE
DRIVERS
O
U
T
P
U
T
S
E
N
S
E
MEMORY
ARRAY
R
E
G
I
S
T
E
R
S
A
M
P
S
WE
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
E
INPUT
REGISTER 0
E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
E
READ LOGIC
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1472BV33 (4M x 18)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
BW a
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
BW b
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
Document #: 001-15031 Rev. *C
E
DQ s
DQ Pa
DQ Pb
E
INPUT
REGISTER 0
E
READ LOGIC
Sleep
Control
Page 2 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Logic Block Diagram – CY7C1474BV33 (1M x 72)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
BW a
BW b
BW c
BW d
BW e
BW f
BW g
BW h
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
E
E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
DQ Pe
DQ Pf
DQ Pg
DQ Ph
WE
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
Document #: 001-15031 Rev. *C
E
INPUT
REGISTER 0
E
READ LOGIC
Sleep
Control
Page 3 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1472BV33
(4M x 18)
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 001-15031 Rev. *C
A
A
A
A
A
A
A
A
VSS
VDD
A
NC(288)
NC(144)
A
A
A
A
A
A
A
A
A
VSS
VDD
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
DQPb
NC
DQb
NC
DQb
VDDQ VDDQ
VSS
VSS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
VDDQ VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
V
DDQ
VDDQ
NC
DQa
DQa
NC
DQPa
NC
MODE
A
A
A
A
A1
A0
CY7C1470BV33
(2M x 36)
NC(288)
NC(144)
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
Figure 1. 100-Pin TQFP Pinout
Page 4 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Pin Configurations
(continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1470BV33 (2M x 36)
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
3
NC/1G
A
DQPc
DQc
NC
DQc
VDDQ
DQc
R
4
5
6
7
8
9
10
11
A
NC
BWc
BWb
CE3
ADV/LD
BWa
VSS
CLK
OE
A
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
BWd
VSS
VDD
CEN
WE
A
VDDQ
NC
DQb
DQPb
DQb
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
CE1
CE2
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
NC
DQd
DQc
NC
DQd
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQb
NC
DQa
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
NC/144M
A
A
A
TDI
A1
TDO
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
NC/288M
CY7C1472BV33 (4M x 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
NC/576M
A
CE1
CE2
BWb
NC
NC
6
7
8
9
10
11
CE3
CLK
CEN
ADV/LD
A
A
A
OE
VSS
VDD
A
NC
VDDQ
VSS
WE
VSS
VSS
A
VSS
VSS
VDDQ
NC
NC
DQPa
DQa
NC/1G
A
NC
NC
NC
DQb
VDDQ
VDDQ
VSS
VDD
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
NC
NC
DQb
DQb
VDD
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
DQb
NC
NC
VDDQ
VDDQ
NC
VDDQ
NC
NC
DQa
DQa
DQa
ZZ
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
DQPb
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
NC
NC
NC/144M
A
A
A
TDI
A1
TDO
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
Document #: 001-15031 Rev. *C
BWa
VSS
NC/288M
A
Page 5 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Pin Configurations
(continued)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1474BV33 (1M × 72)
1
2
3
4
5
6
7
8
9
10
11
A
DQg
DQg
A
CE2
A
ADV/LD
A
CE3
A
DQb
DQb
B
DQg
DQg
BWSc
BWSg
NC
WE
A
BWSb
BWSf
DQb
DQb
C
DQg
DQg
BWSh
BWSd
NC/576M
CE1
NC
BWSe
BWSa
DQb
DQb
D
DQg
DQg
VSS
NC
NC/1G
OE
NC
NC
VSS
DQb
DQb
E
DQPg
DQPc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPf
DQPb
F
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
DQf
G
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
H
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
DQf
J
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
K
NC
NC
CLK
NC
VSS
CEN
VSS
NC
NC
NC
NC
L
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
M
DQh
DQh
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQa
DQa
N
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
P
DQh
DQh
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQa
DQa
R
DQPd
DQPh
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPa
DQPe
T
DQd
DQd
VSS
NC
NC
MODE
NC
NC
VSS
DQe
DQe
U
DQd
DQd
NC/144M
A
A
A
A
A
NC/288M
DQe
DQe
V
DQd
DQd
A
A
A
A1
A
A
A
DQe
DQe
W
DQd
DQd
TMS
TDI
A
A0
A
TDO
TCK
DQe
DQe
Document #: 001-15031 Rev. *C
Page 6 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Table 1. Pin Definitions
Pin Name
IO Type
Pin Description
A0
A1
A
InputSynchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge
of the CLK.
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
InputSynchronous
Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
WE
InputSynchronous
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputSynchronous
Advance/Load Input Used to Advance the On-chip Address Counter or Load a New
Address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD
must be driven LOW to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
InputSynchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select or deselect the device.
CE2
InputSynchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select or deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select or deselect the device.
OE
InputAsynchronous
Output Enable, Active LOW. Combined with the synchronous logic block inside the device to
control the direction of the IO pins. When LOW, the IO pins are enabled to behave as outputs.
When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
CEN
InputSynchronous
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQS
IOSynchronous
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
DQPX
IOSynchronous
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQX. During write
sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg
is controlled by BWg, DQPh is controlled by BWh.
MODE
TDO
TDI
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE must not change states during operation. When
left floating MODE defaults HIGH, to an interleaved burst order.
JTAG Serial
Output
Synchronous
Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
JTAG Serial Input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.
Synchronous
Document #: 001-15031 Rev. *C
Page 7 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Table 1. Pin Definitions (continued)
Pin Name
TMS
IO Type
Test Mode Select This Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.
Synchronous
TCK
JTAG Clock
VDD
Power Supply
VDDQ
Pin Description
Clock Input to the JTAG Circuitry.
Power Supply Inputs to the Core of the Device.
IO Power Supply Power Supply for the IO Circuitry.
VSS
Ground
NC
–
No Connects. This pin is not connected to the die.
NC(144M,
288M,
576M, 1G)
–
These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and
1G densities.
InputAsynchronous
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin must be LOW or left floating.
ZZ pin has an internal pull-down.
ZZ
Ground for the Device. Should be connected to ground of the system.
Functional Overview
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during read or write transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 3.0 ns
(250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If CEN is
active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE). BW[x] can be used to conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the input signal WE is
deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
Address Register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
Document #: 001-15031 Rev. *C
register and onto the data bus within 3.0 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW to drive out the requested
data. During the second clock, a subsequent operation (read,
write, or deselect) can be initiated. Deselecting the device is also
pipelined. Therefore, when the SRAM is deselected at clock rise
by one of the chip enable signals, its output tri-states following
the next clock rise.
Burst Read Accesses
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four reads without reasserting
the address inputs. ADV/LD must be driven LOW to load a new
address into the SRAM, as described in the Single Read
Accesses section. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects
a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the Address Register. The write signals are latched
into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for
CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for
CY7C1474BV33). In addition, the address for the subsequent
Page 8 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
access (read, write, or deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for
CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for
CY7C1474BV33) (or a subset for byte write operations, see
“Partial Write Cycle Description” on page 11 for details) inputs is
latched into the device and the write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d for CY7C1470BV33, BWa,b for CY7C1472BV33, and
BWa,b,c,d,e,f,g,h
for
CY7C1474BV33)
signals.
The
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
provides Byte Write capability that is described in “Partial Write
Cycle Description” on page 11. Asserting the Write Enable input
(WE) with the selected BW input selectively writes to only the
desired bytes. Bytes not selected during a Byte Write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte Write
capability has been included to greatly simplify read, modify, or
write sequences, which can be reduced to simple Byte Write
operations.
Because the CY7C1470BV33, CY7C1472BV33, and
CY7C1474BV33 are common IO devices, data must not be
driven into the device while the outputs are active. The OE can
be deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for
CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for
CY7C1474BV33) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1470BV33, DQa,b/DQPa,b for CY7C1472BV33, and
DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474BV33) are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs
are ignored and the burst counter is incremented. The correct
BW (BWa,b,c,d for CY7C1470BV33, BWa,b for CY7C1472V33,
and BWa,b,c,d,e,f,g,h for CY7C1474BV33) inputs must be driven
in each cycle of the burst write to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Table 2. Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Table 3. Linear Burst Address Table (MODE = GND)
Burst Write Accesses
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
has an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in “Single Write Accesses”
on page 8. When ADV/LD is driven HIGH on the subsequent
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Max
Unit
ZZ > VDD − 0.2V
120
mA
ZZ > VDD − 0.2V
2tCYC
ns
IDDZZ
Sleep mode standby current
tZZS
Device operation to ZZ
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
Document #: 001-15031 Rev. *C
Min
2tCYC
ns
2tCYC
0
ns
ns
Page 9 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Table 4. Truth Table
The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows.[1, 2, 3, 4, 5, 6, 7]
Operation
Address Used
CE
ZZ
ADV/LD
WE
BWx
OE
CEN
CLK
DQ
Deselect Cycle
None
H
L
L
X
X
X
L
L-H
Tri-State
Continue
Deselect Cycle
None
X
L
H
X
X
X
L
L-H
Tri-State
Read Cycle
(Begin Burst)
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Read Cycle
(Continue Burst)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
NOP/Dummy Read
(Begin Burst)
External
L
L
L
H
X
H
L
L-H
Tri-State
Dummy Read
(Continue Burst)
Next
X
L
H
X
X
H
L
L-H
Tri-State
Write Cycle
(Begin Burst)
External
L
L
L
L
L
X
L
L-H
Data In (D)
Write Cycle
(Continue Burst)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
NOP/Write Abort
(Begin Burst)
None
L
L
L
L
H
X
L
L-H
Tri-State
Write Abort
(Continue Burst)
Next
X
L
H
X
H
X
L
L-H
Tri-State
Ignore Clock Edge
(Stall)
Current
X
L
X
X
X
X
H
L-H
-
Sleep Mode
None
X
H
X
X
X
X
X
X
Tri-State
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see “Partial Write Cycle Description” on page 11 for details.
2. Write is defined by WE and BW[a:d]. See “Partial Write Cycle Description” on page 11 for details.
3. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQs and DQP[a:d] = tri-state when OE is
inactive or when the device is deselected, and DQs= data when OE is active.
Document #: 001-15031 Rev. *C
Page 10 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Table 5. Partial Write Cycle Description
The partial write cycle description for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows.[1, 2, 3, 8]
Function (CY7C1470BV33)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
L
H
H
H
L
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Function (CY7C1472BV33)
WE
BWb
BWa
Read
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Function (CY7C1474BV33)
WE
BWx
H
x
Write – No Bytes Written
L
H
Write Byte X − (DQx and DQPx)
L
L
Write All Bytes
L
All BW = L
Read
Note
8. Table lists only a partial listing of the Byte Write combinations. Any combination of BW[a:d] is valid. Appropriate Write is based on which Byte Write is active.
Document #: 001-15031 Rev. *C
Page 11 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
incorporates a serial boundary scan test access port (TAP). This
port operates in accordance with IEEE Standard 1149.1-1990
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V IO logic levels.
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull up resistor. TDO must be left
unconnected. During power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See TAP Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)
Figure 3. TAP Controller Block Diagram
Figure 2. TAP Controller State Diagram
1
0
TEST-LOGIC
RESET
Bypass Register
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCA N
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
0
EXIT1-DR
Boundary Scan Register
EXIT1-IR
0
TDO
x . . . . . 2 1 0
0
1
1
Selection
Circuitry
Identification Register
SHIFT-IR
1
Instruction Register
31 30 29 . . . 2 1 0
0
SHIFT-DR
1
0
PAUSE-DR
0
PAUSE-IR
1
0
0
TCK
TM S
1
EXIT2-DR
TAP CONTROLLER
EXIT2-IR
1
1
UPDATE-DR
1
TDI
Selection
Circuitry
CAPTURE-IR
0
0
2 1 0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Document #: 001-15031 Rev. *C
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
During power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
scans data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register.
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.
Page 12 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the “TAP Controller Block Diagram”
on page 12. During power up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
Bypass Register
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller is moved
into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is executed
whenever the instruction register is loaded with all 0s. EXTEST
is not implemented in this SRAM TAP controller, and therefore
this device is not compliant to 1149.1. The TAP controller does
recognize an all-0 instruction.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
Boundary Scan Register
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the IO ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in “Identification Register Definitions” on
page 17.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Identification
Codes” on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the IO buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the IO ring when these instructions are executed.
Document #: 001-15031 Rev. *C
IDCODE
The IDCODE instruction is loaded into the instruction register
during power up or whenever the TAP controller is in a test logic
reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO balls when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High-Z
state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output may undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
Page 13 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing
a SAMPLE/PRELOAD instruction has the same effect as the
Pause-DR command.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Figure 4. TAP Timing
1
2
Test Clock
(TCK )
3
t TH
t TM SS
t TM SH
t TDIS
t TDIH
t
TL
4
5
6
t CY C
Test M ode Select
(TM S)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CA RE
Document #: 001-15031 Rev. *C
UNDEFINED
Page 14 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
TAP AC Switching Characteristics
Over the Operating Range[9, 10]
Parameter
Description
Min
Max
Unit
20
MHz
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
20
ns
tTL
TCK Clock LOW time
20
ns
50
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
Notes
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document #: 001-15031 Rev. *C
Page 15 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels................................................. VSS to 3.3V
Input pulse levels................................................. VSS to 2.5V
Input rise and fall times....................................................1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels........................................... 1.5V
Input timing reference levels ........................................ 1.25V
Output reference levels .................................................. 1.5V
Output reference levels ................................................ 1.25V
Test load termination supply voltage .............................. 1.5V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Test Conditions
Min
Max
Unit
Output HIGH Voltage IOH = –4.0 mA,VDDQ = 3.3V
IOH = –1.0 mA,VDDQ = 2.5V
2.4
V
2.0
V
Output HIGH Voltage IOH = –100 µA
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
V
Output LOW Voltage
Output LOW Voltage
IOL = 8.0 mA
VDDQ = 3.3V
0.4
V
IOL = 1.0 mA
VDDQ = 2.5V
0.4
V
IOL = 100 µA
VDDQ = 3.3V
0.2
V
VDDQ = 2.5V
0.2
V
Input HIGH Voltage
Input LOW Voltage
Input Load Current
GND < VIN < VDDQ
VDDQ = 3.3V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
Note
11. All voltages refer to VSS (GND).
Document #: 001-15031 Rev. *C
Page 16 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Table 6. Identification Register Definitions
CY7C1470BV33
(2M x 36)
CY7C1472BV33
(4M x 18)
CY7C1474BV33
(1M x 72)
000
000
000
Device Depth (28:24)
01011
01011
01011
Architecture/Memory
Type(23:18)
001000
001000
001000
Defines memory type and architecture
Bus Width/Density(17:12)
100100
010100
110100
Defines width and density
Cypress JEDEC ID Code
(11:1)
00000110100
00000110100
00000110100
Enables unique identification of
SRAM vendor
1
1
1
Indicates the presence of an ID
register
Instruction Field
Revision Number (31:29)
[12]
ID Register Presence
Indicator (0)
Description
Describes the version number
Reserved for internal use
Table 7. Scan Register Sizes
Register Name
Instruction
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
3
3
3
Bypass
1
1
1
ID
32
32
32
Boundary Scan Order – 165 FBGA
71
52
-
Boundary Scan Order – 209 FBGA
-
-
110
Table 8. Identification Codes
Instruction
Code
Description
EXTEST
000
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
Note
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 001-15031 Rev. *C
Page 17 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Table 9. Boundary Scan Exit Order (2M x 36)
Bit #
165-Ball ID
Bit #
165-Ball ID
Bit #
165-Ball ID
Bit #
165-Ball ID
1
C1
21
R3
2
D1
22
P2
41
J11
61
B7
42
K10
62
B6
3
E1
23
R4
43
J10
63
A6
4
D2
24
P6
44
H11
64
B5
5
E2
25
R6
45
G11
65
A5
6
F1
26
R8
46
F11
66
A4
7
G1
27
P3
47
E11
67
B4
8
F2
28
P4
48
D10
68
B3
9
G2
29
P8
49
D11
69
A3
10
J1
30
P9
50
C11
70
A2
11
K1
31
P10
51
G10
71
B2
12
L1
32
R9
52
F10
13
J2
33
R10
53
E10
14
M1
34
R11
54
A9
15
N1
35
N11
55
B9
16
K2
36
M11
56
A10
17
L2
37
L11
57
B10
18
M2
38
M10
58
A8
19
R1
39
L10
59
B8
20
R2
40
K11
60
A7
165-Ball ID
Bit #
165-Ball ID
B10
Table 10. Boundary Scan Exit Order (4M x 18)
Bit #
165-Ball ID
Bit #
165-Ball ID
Bit #
1
D2
14
R4
27
L10
40
2
E2
15
P6
28
K10
41
A8
3
F2
16
R6
29
J10
42
B8
4
G2
17
R8
30
H11
43
A7
5
J1
18
P3
31
G11
44
B7
6
K1
19
P4
32
F11
45
B6
7
L1
20
P8
33
E11
46
A6
8
M1
21
P9
34
D11
47
B5
9
N1
22
P10
35
C11
48
A4
10
R1
23
R9
36
A11
49
B3
11
R2
24
R10
37
A9
50
A3
12
R3
25
R11
38
B9
51
A2
13
P2
26
M10
39
A10
52
B2
Document #: 001-15031 Rev. *C
Page 18 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Boundary Scan Exit Order (1M x 72)
Bit #
209-Ball ID
Bit #
209-Ball ID
Bit #
209-Ball ID
Bit #
209-Ball ID
1
A1
29
T1
57
U10
85
B11
2
A2
30
T2
58
T11
86
B10
3
B1
31
U1
59
T10
87
A11
4
B2
32
U2
60
R11
88
A10
5
C1
33
V1
61
R10
89
A7
6
C2
34
V2
62
P11
90
A5
7
D1
35
W1
63
P10
91
A9
8
D2
36
W2
64
N11
92
U8
9
E1
37
T6
65
N10
93
A6
10
E2
38
V3
66
M11
94
D6
11
F1
39
V4
67
M10
95
K6
12
F2
40
U4
68
L11
96
B6
13
G1
41
W5
69
L10
97
K3
14
G2
42
V6
70
P6
98
A8
15
H1
43
W6
71
J11
99
B4
16
H2
44
V5
72
J10
100
B3
17
J1
45
U5
73
H11
101
C3
18
J2
46
U6
74
H10
102
C4
19
L1
47
W7
75
G11
103
C8
20
L2
48
V7
76
G10
104
C9
21
M1
49
U7
77
F11
105
B9
22
M2
50
V8
78
F10
106
B8
23
N1
51
V9
79
E10
107
A4
24
N2
52
W11
80
E11
108
C6
25
P1
53
W10
81
D11
109
B7
26
P2
54
V11
82
D10
110
A3
27
R2
55
V10
83
C11
28
R1
56
U11
84
C10
Document #: 001-15031 Rev. *C
Page 19 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch Up Current ................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND ........–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
Range
DC to Outputs in Tri-State.................... –0.5V to VDDQ + 0.5V
Commercial
Industrial
Ambient
Temperature
VDD
VDDQ
0°C to +70°C
3.3V
–5%/+10%
2.5V – 5%
to VDD
–40°C to +85°C
Electrical Characteristics
Over the Operating Range[13, 14]
Parameter
Description
VDD
Power Supply Voltage
VDDQ
IO Supply Voltage
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH
VIL
Input LOW
IX
Voltage[13]
Voltage[13]
Input Leakage Current
except ZZ and MODE
Test Conditions
Min
Max
Unit
3.135
3.6
V
For 3.3V IO
3.135
VDD
V
For 2.5V IO
2.375
2.625
V
For 3.3V IO, IOH = −4.0 mA
2.4
V
For 2.5V IO, IOH= −1.0 mA
2.0
V
For 3.3V IO, IOL= 8.0 mA
0.4
V
For 2.5V IO, IOL= 1.0 mA
0.4
V
For 3.3V IO
2.0
VDD + 0.3V
V
For 2.5V IO
1.7
VDD + 0.3V
V
For 3.3V IO
–0.3
0.8
V
For 2.5V IO
–0.3
0.7
V
–5
5
μA
GND ≤ VI ≤ VDDQ
Input Current of MODE Input = VSS
Input = VDD
Input Current of ZZ
5
Input = VSS
30
μA
5
μA
4.0-ns cycle, 250 MHz
500
mA
5.0-ns cycle, 200 MHz
500
mA
6.0-ns cycle, 167 MHz
450
mA
4.0-ns cycle, 250 MHz
245
mA
5.0-ns cycle, 200 MHz
245
mA
6.0-ns cycle, 167 MHz
245
mA
120
mA
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
[15]
ISB1
ISB2
VDD Operating Supply
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL,
f = fMAX = 1/tCYC
μA
μA
–5
Input = VDD
IOZ
μA
–30
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power Down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = 0
–5
Notes
13. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC)> –2V (pulse width less than tCYC/2).
14. TPower-up: assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
15. The operation current is calculated with 50% read cycle and 50% write cycle.
Document #: 001-15031 Rev. *C
Page 20 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Electrical Characteristics
Over the Operating Range[13, 14] (continued)
Parameter
ISB3
Description
Test Conditions
Min
Automatic CE
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
Power Down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
5.0-ns cycle, 200 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
6.0-ns cycle, 167 MHz
ISB4
Automatic CE
Power Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All speed grades
Max
Unit
245
mA
245
mA
245
mA
135
mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Test Conditions
100 TQFP
Max
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ = 2.5V
6
6
6
pF
5
5
5
pF
8
8
8
pF
Description
165 FBGA 209 FBGA
Max
Max
Unit
CADDRESS
Address Input Capacitance
CDATA
Data Input Capacitance
CCTRL
Control Input Capacitance
CCLK
Clock Input Capacitance
6
6
6
pF
CIO
Input/Output Capacitance
5
5
5
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameters
Test Conditions
100 TQFP
Package
165 FBGA
Package
209 FBGA
Package
Unit
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.
24.63
16.3
15.2
°C/W
2.28
2.1
1.7
°C/W
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
AC Test Loads and Waveforms
3.3V IO Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
10%
90%
10%
90%
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
VL = 1.5V
INCLUDING
JIG AND
SCOPE
(a)
(c)
(b)
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
Z0 = 50Ω
10%
R = 1538Ω
VL = 1.25V
Document #: 001-15031 Rev. *C
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
(b)
≤ 1 ns
≤ 1 ns
(c)
Page 21 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Switching Characteristics
Over the Operating Range. Timing reference is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. Test conditions shown in
(a) of “AC Test Loads and Waveforms” on page 21 unless otherwise noted.
Parameter
tPower[16]
Description
VCC (typical) to the First Access Read or Write
–250
Min
–200
Max
Min
–167
Max
Min
Max
Unit
1
1
1
ms
4.0
5.0
6.0
ns
Clock
tCYC
Clock Cycle Time
FMAX
Maximum Operating Frequency
tCH
Clock HIGH
2.0
2.0
2.2
ns
tCL
Clock LOW
2.0
2.0
2.2
ns
250
200
167
MHz
Output Times
tCO
Data Output Valid After CLK Rise
3.0
3.0
3.4
ns
tOEV
OE LOW to Output Valid
3.0
3.0
3.4
ns
tDOH
Data Output Hold After CLK Rise
tCHZ
Clock to High-Z[17, 18, 19]
tCLZ
Low-Z[17, 18, 19]
tEOHZ
tEOLZ
Clock to
OE HIGH to Output
High-Z[17, 18, 19]
OE LOW to Output
Low-Z[17, 18, 19]
1.3
1.3
3.0
1.3
1.5
3.0
1.3
3.0
ns
3.4
1.5
3.0
ns
ns
3.4
ns
0
0
0
ns
Setup Times
tAS
Address Setup Before CLK Rise
1.4
1.4
1.5
ns
tDS
Data Input Setup Before CLK Rise
1.4
1.4
1.5
ns
tCENS
CEN Setup Before CLK Rise
1.4
1.4
1.5
ns
tWES
WE, BWx Setup Before CLK Rise
1.4
1.4
1.5
ns
tALS
ADV/LD Setup Before CLK Rise
1.4
1.4
1.5
ns
tCES
Chip Select Setup
1.4
1.4
1.5
ns
tAH
Address Hold After CLK Rise
0.4
0.4
0.5
ns
tDH
Data Input Hold After CLK Rise
0.4
0.4
0.5
ns
tCENH
CEN Hold After CLK Rise
0.4
0.4
0.5
ns
tWEH
WE, BWx Hold After CLK Rise
0.4
0.4
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.4
0.4
0.5
ns
tCEH
Chip Select Hold After CLK Rise
0.4
0.4
0.5
ns
Hold Times
Notes
16. This part has an internal voltage regulator; tpower is the time power is supplied above VDD minimum initially, before a read or write operation can be initiated.
17. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ±200 mV
from steady-state voltage.
18. At any voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z before Low-Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
Document #: 001-15031 Rev. *C
Page 22 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Switching Waveforms
Figure 5 shows read-write timing waveform.[20, 21, 22]
Figure 5. Read/Write Timing
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW x
A1
ADDRESS
A2
A7
t CO
t AS
t DS
t AH
Data
In-Out (DQ)
t DH
D(A1)
t CLZ
D(A2)
D(A2+1)
t DOH
Q(A3)
t OEV
Q(A4)
t CHZ
Q(A4+1)
D(A5)
Q(A6)
t OEHZ
t DOH
t OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
DON’T CARE
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
20. For this waveform ZZ is tied LOW.
21. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.
22. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional.
Document #: 001-15031 Rev. *C
Page 23 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Switching Waveforms
(continued)
Figure 6 shows NOP, STALL and DESELECT Cycles waveform.
[20, 21, 23]
Figure 6. NOP, STALL and DESELECT Cycles
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
t CHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
Figure 7 shows ZZ Mode timing waveform.
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
[24, 25]
Figure 7. ZZ Mode Timing
CLK
t ZZ
ZZ
I
t
t ZZREC
ZZI
SUPPLY
I DDZZ
t RZZI
A LL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes
23. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A Write is not performed during this cycle.
24. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.
25. IOs are in High-Z when exiting ZZ sleep mode.
Document #: 001-15031 Rev. *C
Page 24 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
167
Ordering Code
CY7C1470BV33-167AXC
Package
Diagram
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Operating
Range
Commercial
CY7C1472BV33-167AXC
CY7C1470BV33-167BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-167BZC
CY7C1470BV33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-167BZXC
CY7C1474BV33-167BGC
CY7C1474BV33-167BGXC
CY7C1470BV33-167AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
lndustrial
CY7C1472BV33-167AXI
CY7C1470BV33-167BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-167BZI
CY7C1470BV33-167BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-167BZXI
CY7C1474BV33-167BGI
CY7C1474BV33-167BGXI
200
CY7C1470BV33-200AXC
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Commercial
CY7C1472BV33-200AXC
CY7C1470BV33-200BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-200BZC
CY7C1470BV33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-200BZXC
CY7C1474BV33-200BGC
CY7C1474BV33-200BGXC
CY7C1470BV33-200AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
lndustrial
CY7C1472BV33-200AXI
CY7C1470BV33-200BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-200BZI
CY7C1470BV33-200BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-200BZXI
CY7C1474BV33-200BGI
CY7C1474BV33-200BGXI
Document #: 001-15031 Rev. *C
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
Page 25 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Ordering Information
(continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
250
Ordering Code
CY7C1470BV33-250AXC
Package
Diagram
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Operating
Range
Commercial
CY7C1472BV33-250AXC
CY7C1470BV33-250BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-250BZC
CY7C1470BV33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-250BZXC
CY7C1474BV33-250BGC
CY7C1474BV33-250BGXC
CY7C1470BV33-250AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free
Industrial
CY7C1472BV33-250AXI
CY7C1470BV33-250BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-250BZI
CY7C1470BV33-250BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-250BZXI
CY7C1474BV33-250BGI
CY7C1474BV33-250BGXI
Document #: 001-15031 Rev. *C
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
Page 26 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Package Diagrams
Figure 8. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
1.00 REF.
DETAIL
Document #: 001-15031 Rev. *C
A
51-85050-*B
Page 27 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Package Diagrams
(continued)
Figure 9. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45±0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
F
F
G
G
H
J
14.00
E
17.00±0.10
E
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
1.00
5.00
0.35
0.15 C
+0.05
-0.10
0.53±0.05
0.25 C
10.00
B
15.00±0.10
0.15(4X)
SEATING PLANE
Document #: 001-15031 Rev. *C
1.40 MAX.
0.36
C
51-85165-*A
Page 28 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Package Diagrams
(continued)
Figure 10. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167
51-85167-**
Document #: 001-15031 Rev. *C
Page 29 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Document History Page
Document Title: CY7C1470BV33/CY7C1472BV33/CY7C1474BV33, 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
with NoBL™ Architecture
Document Number: 001-15031
Orig. of
Change
REV.
ECN No.
Issue Date
**
1032642
See ECN
*A
1897447
See ECN
VKN/AESA
*B
2082487
See ECN
VKN
*C
2159486
See ECN
VKN/PYRS
Description of Change
VKN/KKVTMP New Data Sheet
Added footnote 15 related to IDD
Converted from preliminary to final
Minor Change-Moved to the external web
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15031 Rev. *C
Revised February 29, 2008
Page 30 of 30
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective holders.
[+] Feedback