LC2MOS 16-Bit Voltage Output DAC AD7846 16-bit monotonicity over temperature ±2 LSBs integral linearity error Microprocessor compatible with readback capability Unipolar or bipolar output Multiplying capability Low power (100 mW typical) FUNCTIONAL BLOCK DIAGRAM VREF+ 7 4 R A2 6 RIN 5 VOUT 23 CS 22 R/W 25 LDAC 24 CLR R 16 SEGMENT SWITCH MATRIX A3 12-BIT DAC R VREF– VDD 21 AD7846 R R VCC 12 A1 8 DAC LATCH 4 CONTROL LOGIC 12 I/O LATCH 10 9 VSS 3 DB15 DB0 20 DGND 08490-001 FEATURES Figure 1. GENERAL DESCRIPTION The AD7846 is a 16-bit DAC constructed with the Analog Devices, Inc., LC2MOS process. It has VREF+ and VREF− reference inputs and an on-chip output amplifier. These can be configured to give a unipolar output range (0 V to +5 V, 0 V to +10 V) or bipolar output ranges (±5 V, ±10 V). The DAC uses a segmented architecture. The four MSBs in the DAC latch select one of the segments in a 16-resistor string. Both taps of the segment are buffered by amplifiers and fed to a 12-bit DAC, which provides a further 12 bits of resolution. This architecture ensures 16-bit monotonicity. Excellent integral linearity results from tight matching between the input offset voltages of the two buffer amplifiers. In addition to the excellent accuracy specifications, the AD7846 also offers a comprehensive microprocessor interface. There are 16 data I/O pins, plus control lines (CS, R/W, LDAC and CLR). R/W and CS allow writing to and reading from the I/O latch. This is the readback function, which is useful in ATE applications. LDAC allows simultaneous updating of DACs in a multi-DAC system and the CLR line will reset the contents of the DAC latch to 00…000 or 10…000 depending on the state of R/W. This means that the DAC output can be reset to 0 V in both the unipolar and bipolar configurations. The AD7846 is available in 28-lead plastic, ceramic, and PLCC packages. PRODUCT HIGHLIGHTS 1. 2. 3. 16-Bit Monotonicity The guaranteed 16-bit monotonicity over temperature makes the AD7846 ideal for closed-loop applications. Readback The ability to read back the DAC register contents minimizes software routines when the AD7846 is used in ATE systems. Power Dissipation Power dissipation of 100 mW makes the AD7846 the lowest power, high accuracy DAC on the market. Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. 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AD7846 TABLE OF CONTENTS Features .............................................................................................. 1 Output Stage................................................................................ 12 Functional Block Diagram .............................................................. 1 Unipolar Binary Operation ........................................................... 13 General Description ......................................................................... 1 Bipolar Operation ........................................................................... 14 Product Highlights ........................................................................... 1 Multiplying Operation ............................................................... 14 Revision History ............................................................................... 2 Position Measurement Application.............................................. 15 Specifications..................................................................................... 3 Microprocessor Interfacing ........................................................... 16 AC Performance Characteristics ................................................ 4 AD7846-to-8086 Interface ........................................................ 16 Timing Characteristics ................................................................ 5 AD7846-to-MC68000 Interface ............................................... 16 Absolute Maximum Ratings............................................................ 6 Digital Feedthrough ....................................................................... 17 ESD Caution .................................................................................. 6 Application Hints ........................................................................... 18 Pin Configurations and Function Descriptions ........................... 7 Noise ............................................................................................ 18 Typical Performance Characteristics ............................................. 8 Grounding ................................................................................... 18 Terminology .................................................................................... 10 Printed Circuit Board Layout ................................................... 18 Circuit Description ......................................................................... 11 Outline Dimensions ....................................................................... 20 Digital Section............................................................................. 11 Ordering Guide .......................................................................... 22 Digital-to-Analog Conversion .................................................. 11 REVISION HISTORY 4/10—Rev. F to Rev. G Change to Figure 1 ........................................................................... 1 12/09—Rev. E to Rev. F Updated Format .................................................................. Universal Changes to Table 4 ............................................................................ 6 Deleted Other Output Voltage Ranges Section ............................ 9 Deleted Figure 20 and Table 5; Renumbered Sequentially ......... 9 Deleted Test Application Section and Figure 21 ........................ 10 Deleted Figure 29 to Figure 31 ...................................................... 14 Changes to Printed Circuit Board Layout Section ..................... 18 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 22 Rev. G | Page 2 of 24 AD7846 SPECIFICATIONS VDD = +14.25 V to +15.75 V; VSS = −14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V. VOUT loaded with 2 kΩ, 1000 pF to 0 V; VREF+ = +5 V; RIN connected to 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 RESOLUTION UNIPOLAR OUTPUT Relative Accuracy at +25°C TMIN to TMAX Differential Nonlinearity Error Gain Error at +25°C TMIN to TMAX Offset Error at +25°C TMIN to TMAX Gain TC 2 Offset TC2 J, A Versions 16 K, B Versions 16 Unit Bits ±12 ±16 ±1 ±12 ±16 ±12 ±16 ±1 ±1 ±4 ±8 ±0.5 ±6 ±16 ±6 ±16 ±1 ±1 LSB typ LSB max LSB max LSB typ LSB max LSB typ LSB max ppm FSR/°C typ ppm FSR/°C typ BIPOLAR OUTPUT Relative Accuracy at +25°C TMIN to TMAX Differential Nonlinearity Error Gain Error at +25°C TMIN to TMAX Offset Error at +25°C TMIN to TMAX Bipolar Zero Error at +25°C TMIN to TMAX Gain TC2 Offset TC2 Bipolar Zero TC2 ±6 ±8 ±1 ±6 ±16 ±6 ±16 ±6 ±12 ±1 ±1 ±1 ±2 ±4 ±0.5 ±4 ±16 ±4 ±12 ±4 ±8 ±1 ±1 ±1 LSB typ LSB max LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max ppm FSR/°Ctyp ppm FSR/°Ctyp ppm FSR/°Ctyp 20 40 VSS + 6 to VDD − 6 VSS + 6 to VDD − 6 20 40 VSS + 6 to VDD − 6 VSS + 6 to VDD − 6 kΩ min kΩ max V min to V max V min to V max VSS + 4 to VDD − 3 2 1000 0.3 ±25 VSS + 4 to VDD − 3 2 1000 0.3 ±25 V max 2.4 0.8 ±10 10 2.4 0.8 ±10 10 V min V max μA max pF max REFERENCE INPUT Input Resistance VREF+ Range VREF− Range OUTPUT CHARACTERISTICS Output Voltage Swing Resistive Load Capacitive Load Output Resistance Short Circuit Current DIGITAL INPUTS VIH (Input High Voltage) VIL (Input Low Voltage) IIN (Input Current) CIN (Input Capacitance)2 Rev. G | Page 3 of 24 kΩ min pF max Ω typ mA typ Test Conditions/Comments VREF− = 0 V, VOUT = 0 V to +10 V 1 LSB = 153 μV All grades guaranteed monotonic VOUT load = 10 MΩ VREF− = –5 V, VOUT = −10 V to +10 V 1 LSB = 305 μV All grades guaranteed monotonic VOUT load = 10 MΩ VOUT load = 10 MΩ Resistance from VREF+ to VREF− Typically 30 kΩ To 0 V To 0 V To 0 V or any power supply AD7846 Parameter 1 DIGITAL OUTPUTS VOL (Output Low Voltage) VOH (Output High Voltage) Floating State Leakage Current Floating State Output Capacitance2 POWER REQUIREMENTS 3 VDD VSS VCC IDD ISS ICC Power Supply Sensitivity 4 Power Dissipation J, A Versions K, B Versions Unit Test Conditions/Comments 0.4 4.0 ±10 10 0.4 4.0 ±10 10 V max V min μA max pF max ISINK = 1.6 mA ISOURCE = 400 μA DB0 to DB15 = 0 to VCC +11.4/+15.75 −11.4/−15.75 +4.75/+5.25 5 5 1 1.5 100 +11.4/+15.75 −11.4/−15.75 +4.75/+5.25 5 5 1 1.5 100 V min/V max V min/V max V min/V max mA max mA max mA max LSB/V max mW typ VOUT unloaded VOUT unloaded VOUT unloaded 1 Temperature ranges as follows: J, K versions: 0°C to +70°C; A, B versions: −40°C to +85°C. Guaranteed by design and characterization, not production tested. The AD7846 is functional with power supplies of ±12 V. See the Typical Performance Characteristics section. 4 Sensitivity of gain error, offset error, and bipolar zero error to VDD, VSS variations. 2 3 AC PERFORMANCE CHARACTERISTICS These characteristics are included for design guidance and are not subject to test. VREF+ = +5 V; VDD = +14.25 V to +15.75 V; VSS = −14.25 V to −15.75 V; VCC = +4.75 V to +5.25 V; RIN connected to 0 V, unless otherwise noted. Table 2. Parameter Output Settling Time 1 Limit at TMIN to TMAX (All Versions) 6 9 7 Unit μs max μs max V/μs typ Test Conditions/Comments To 0.006% FSR, VOUT loaded, VREF− = 0 V, typically 3.5 μs To 0.003% FSR, VOUT loaded, VREF− = –5 V, typically 6.5 μs 70 nV-sec typ AC Feedthrough 0.5 mV p-p typ Digital Feedthrough Output Noise Voltage Density, 1 kHz to 100 kHz 10 50 nV-sec typ nV/√Hz typ DAC alternately loaded with 10…0000 and 01…1111, VOUT unloaded VREF− = 0 V, VREF+ = 1 V rms, 10 kHz sine wave, DAC loaded with all 0s DAC alternately loaded with all 1s and all 0s. CS high Measured at VOUT, DAC loaded with 0111011…11, VREF+ = VREF− = 0 V Slew Rate Digital-to-Analog Glitch Impulse 1 LDAC = 0. Settling time does not include deglitching time of 2.5 μs (typ). Rev. G | Page 4 of 24 AD7846 TIMING CHARACTERISTICS VDD = +14.25 V to +15.75 V, VSS = −14.25 V to −15.75 V, VCC = +4.75 V to +5.25 V, unless otherwise noted. Table 3. Parameter 1 Limit at TMIN to TMAX (All Versions) 0 60 0 60 0 120 10 60 0 70 0 70 130 t1 t2 t3 t4 t5 t6 2 t7 3 t8 t9 t10 t11 t12 Unit ns min ns min ns min ns min ns min ns max ns min ns max ns min ns min ns min ns min ns min Test Conditions/Comments R/W to CS setup time CS pulse width (write cycle) R/W to CS hold time Data setup time Data hold time Data access time Bus relinquish time CLR setup time CLR pulse width CLR hold time LDAC pulse width CS pulse width (read cycle) 1 Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2 t6 is measured with the load circuits of Figure 3 and Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V. 3 t7 is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 5 and Figure 6. t1 t3 t1 t3 5V R/W t2 5V t5 t4 t6 DATA VALID t8 t9 0V t7 5V DATA VALID t10 t8 t9 0V t10 5V CLR t11 LDAC 0V 5V 0V 08490-006 CS DB0 TO DB15 0V t12 Figure 2. Timing Diagram DBn 10pF 3kΩ 08490-002 DGND DGND 08490-004 DBn 100pF 3kΩ Figure 5. Load Circuit for Access Time (t7)—High Z to VOH Figure 3. Load Circuit for Access Time (t6)—High Z to VOH 5V 5V 3kΩ 3kΩ DGND 10pF 08490-003 100pF DGND 08490-005 DBn DBn Figure 6. Load Circuits for Bus Relinquish Time (t7)—High Z to VOL Figure 4. Load Circuits for Bus Relinquish Time (t6)—High Z to VOL Rev. G | Page 5 of 24 AD7846 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter VDD to DGND VCC to DGND VSS to DGND VREF+ to DGND VREF− to DGND VOUT to DGND1 RIN to DGND Digital Input Voltage to DGND Digital Output Voltage to DGND Power Dissipation (Any Package) To +75°C Derates above +75°C Operating Temperature Range J, K Versions A, B Versions Storage Temperature Range Lead Temperature (Soldering) 1 Rating −0.4 V to +17 V −0.4 V, VDD + 0.4 V, or +7 V (whichever is lower) +0.4 V to −17 V VDD + 0.4 V, VSS − 0.4 V VDD + 0.4 V, VSS − 0.4 V VDD + 0.4 V, VSS − 0.4 V, or ±10 V (whichever is lower) VDD + 0.4 V, VSS − 0.4 V −0.4 V to VCC + 0.4 V −0.4 V to VCC + 0.4 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1000 mW 10 mW/°C 0°C to +70°C −40°C to +85°C −65°C to +150°C +300°C VOUT can be shorted to DGND, VDD, VSS, or VCC provided that the power dissipation of the package is not exceeded. Rev. G | Page 6 of 24 AD7846 26 DB5 4 25 LDAC VOUT 5 24 CLR VREF+ 7 RIN 6 VREF– 8 VREF+ AD7846 23 CS 7 TOP VIEW 22 R/W VREF– 8 (Not to Scale) 21 V CC VOUT 5 19 DB6 12 13 14 15 16 17 18 08490-008 20 DGND DB14 11 DB7 15 DB10 21 VCC DB8 16 DB9 DB11 14 (Not to Scale) VSS 9 DB9 17 DB8 DB12 13 22 R/W DB10 DB13 12 23 CS TOP VIEW DB11 18 DB7 AD7846 DB15 10 DB12 19 DB6 DB14 11 25 LDAC 24 CLR DB13 DB15 10 28 27 26 PIN 1 IDENTIFIER RIN 6 20 DGND 9 1 08490-007 VSS 2 DB4 3 VDD 3 DB5 DB0 4 DB3 27 DB4 DB1 28 DB3 2 DB2 1 DB1 DB0 DB2 VDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 7. PDIP Pin Configuration Figure 8. CERDIP Pin Configuration Table 5. Pin Function Descriptions Pin 1 to 3 4 5 6 7 8 Mnemonic DB2 to DB0 VDD VOUT RIN VREF+ VREF− 9 10 to 19 20 21 22 23 24 25 26 to 28 VSS DB15 to DB6 DGND VCC R/W CS CLR LDAC DB5 to DB3 Description Data I/Os. DB0 is LSB. Positive Supply for Analog Circuitry. This is +15 V nominal. DAC Output Voltage. Input to Summing Resistor of DAC Output Amplifier. This is used to select output voltage ranges. See Table 6. VREF+ Input. The DAC is specified for VREF+ = +5 V. VREF− Input. For unipolar operation connect VREF− to 0 V, and for bipolar operation connect it to −5 V. The device is specified for both conditions. Negative Supply for the Analog Circuitry. This is −15 V nominal. Data I/Os. DB15 is MSB. Ground for Digital Circuitry. Positive Supply for Digital Circuitry. This is +5 V nominal. R/W Input. This pin can be used to load data to the DAC or to read back the DAC latch contents. Chip Select Input. This pin selects the device. Clear Input. The DAC can be cleared to 000…000 or 100…000. See Table 7. Asynchronous Load Input to DAC. Data I/Os. Table 6. Output Voltage Ranges Output Range 0 V to +5 V 0 V to +10 V +5 V to −5 V +5 V to −5 V +10 V to −10 V VREF+ +5 V +5 V +5 V +5 V +5 V VREF− 0V 0V −5 V 0V −5 V Rev. G | Page 7 of 24 RIN VOUT 0V VOUT +5 V 0V AD7846 TYPICAL PERFORMANCE CHARACTERISTICS 500 –0.40V 1V 2mV 08490-009 NOISE SPECTRAL DENSITY (nV/√Hz) 450 20µs 400 VREF+ = VREF– = 0V GAIN = +1 DAC LOADED WITH ALL 1s 350 300 250 200 150 100 50 0 100 1k 10k FREQUENCY (Hz) 100k 1M 08490-012 A1 Figure 12. Noise Spectral Density Figure 9. AC Feedthrough, VREF+ = 1 V rms, 10 kHz Sine Wave 8 7 VOUT (mV p-p) 6 VDD = +15V VSS = –15V VREF + = +1V rms VREF – = 0V 50mV/DIV VOUT 5 4 3 2 1k 10k FREQUENCY (Hz) 100k 1M 0.5µs/DIV 08490-010 0 100 Figure 10. AC Feedthrough to VOUT vs. Frequency 08490-013 5V/DIV DATA 1 Figure 13. Digital-to-Analog Glitch Impulse Without Internal Deglitcher (10…000 to 011…111 Transition) 30 25 VDD = +15V VSS = –15V VREF+ = ±5V SINE WAVE VREF– = 0V GAIN = +2 VOUT 50mV/DIV LDAC 5V/DIV DATA 5V/DIV 15 5 0 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 1µs/DIV 08490-014 10 08490-011 VOUT (V p-p) 20 Figure 14. Digital-to-Analog Glitch Impulse with Internal Deglitcher (10…000 to 011…111 Transition) Figure 11. Large Signal Frequency Response Rev. G | Page 8 of 24 AD7846 A1 4.0 0V TA = +25°C VREF+ = +5V VREF– = 0V GAIN = +1 3.5 VREF +, ±5V INL (LSB) 3.0 2.5 2.0 1.5 VOUT+, ±10V 1.0 0.5 11 12 13 14 VDD, VSS (V) 15 16 08490-018 2µs 16 08490-019 5V 08490-015 10V Figure 18. Typical Integral Nonlinearity vs. VDD/VSS Figure 15. Pulse Response (Large Signal) 1.0 A1 0.025V TA = +25°C VREF+ = +5V VREF– = 0V GAIN = +1 0.9 VREF +, ±50mV 0.8 DNL (LSB) 0.7 0.6 0.5 0.4 0.3 0.2 VOUT+, ±100mV 50mV 0.1 08490-016 100mV 1µs 0 11 12 13 14 VDD, VSS (V) 15 Figure 19. Typical Differential Nonlinearity vs. VDD/VSS Figure 16. Pulse Response (Small Signal) START 100.0Hz RBW 3Hz RANGE 3.98V VBW 10Hz MARKER 442.0Hz 1.70V STOP 2000.0Hz ST 422 SEC 08490-017 REF 2.24V 10dB/DIV Figure 17. Spectral Response of Digitally Constructed Sine Wave Rev. G | Page 9 of 24 AD7846 TERMINOLOGY Least Significant Bit This is the analog weighting of 1 bit of the digital word in a DAC. For the AD7846, 1 LSB = (VREF+ − VREF−)/216. Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for both endpoints (that is, offset and gain errors are adjusted out) and is normally expressed in least significant bits or as a percentage of full-scale range. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB over the operating temperature range ensures monotonicity. Gain Error Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. Gain error is adjustable to zero with an external potentiometer. Offset Error This is the error present at the device output with all 0s loaded in the DAC. It is due to op amp input offset voltage and bias current and the DAC leakage current. Bipolar Zero Error When the AD7846 is connected for bipolar output and 10…000 is loaded to the DAC, the deviation of the analog output from the ideal midscale of 0 V is called the bipolar zero error. Digital-to-Analog Glitch Impulse This is the amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-sec or nV-sec depending upon whether the glitch is measured as a current or a voltage. Multiplying Feedthrough Error This is an ac error due to capacitive feedthrough from either of the VREF terminals to VOUT when the DAC is loaded with all 0s. Digital Feedthrough When the DAC is not selected (that is, CS is held high), high frequency logic activity on the digital inputs is capacitively coupled through the device to show up as noise on the VOUT pin. This noise is digital feedthrough. Rev. G | Page 10 of 24 AD7846 CIRCUIT DESCRIPTION DIGITAL SECTION Table 7. Control Logic Truth Table Figure 20 shows the digital control logic and on-chip data latches in the AD7846. Table 7 is the associated truth table. The digitalto-analog converter (DAC) has two latches that are controlled by four signals: CS, R/W, LDAC, and CLR. The input latch is connected to the data bus (DB15 to DB0). A word is written to the input latch by bringing CS low and R/W low. The contents of the input latch can be read back by bringing CS low and R/W high. This feature is called readback and is used in system diagnostic and calibration routines. CS R/W LDAC CLR 1 0 X 0 X X X X 0 1 X X X X 0 1 X X 0 1 X X 0 0 Data is transferred from the input latch to the DAC latch with the LDAC strobe. The equivalent analog value of the DAC latch contents appears at the DAC output. The CLR pin resets the DAC latch contents to 000…000 or 100…000, depending on the state of R/W. Writing a CLR loads 000…000 and reading a CLR loads 100…000. To reset a DAC to 0 V in a unipolar system, the user should assert CLR while R/W is low; to reset to 0 V in a bipolar system, assert the CLR while R/W is high. DIGITAL-TO-ANALOG CONVERSION R/ W CLR DAC 16 DB15 RST DB15 TO DB0 LATCHES DB15 SET LDAC DB14 TO DB0 RST 16 3-STATE I/O LATCH 16 DB15 DB0 Figure 20. Input Control Logic 08490-020 CS Function 3-state DAC I/O latch in high-Z state DAC I/O latch loaded with DB15 to DB0 Contents of DAC I/O latch available on DB15 to DB0 Contents of DAC I/O latch transferred to DAC latch DAC latch loaded with 000…000 DAC latch loaded with 100…000 Figure 21 shows the digital-to-analog section of the AD7846. There are three DACs, each of which has its own buffer amplifiers. DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor string but have their own analog multiplexers. The voltage reference is applied to the resistor string. DAC3 is a 12-bit voltage mode DAC with its own output stage. The four MSBs of the 16-bit digital code drive DAC1 and DAC2, and the 12 LSBs control DAC3. Using DAC1 and DAC2, the MSBs select a pair of adjacent nodes on the resistor string and present that voltage to the positive and negative inputs of DAC3. This DAC interpolates between these two voltages to produce the analog output voltage. To prevent nonmonotonicity in the DAC due to amplifier offset voltages, DAC1 and DAC2 leap along the resistor string. For example, when switching from Segment 1 to Segment 2, DAC1 switches from the bottom of Segment 1 to the top of Segment 2 while DAC2 stays connected to the top of Segment 1. The code driving DAC3 is automatically complemented to compensate for the inversion of its inputs. This means that any linearity effects due to amplifier offset voltages remain unchanged when switching from one segment to the next and 16-bit monotonicity is ensured if DAC3 is monotonic. Thus, 12-bit resistor matching in DAC3 guarantees overall 16-bit monotonicity. This is much more achievable than 16-bit matching, which a conventional R-2R structure needs. Rev. G | Page 11 of 24 AD7846 VREF+ SEGMENT 16 R DAC2 DAC1 S1 S3 S2 RIN R DAC3 S4 A1 A3 VOUT 12-BIT DAC S15 S14 S17 S16 A2 DB15 TO DB12 DB11 TO DB0 DB15 TO DB12 08490-021 SEGMENT 1 VREF– Figure 21. Digital-to-Analog Conversion The output stage of the AD7846 is shown in Figure 22. It is capable of driving a 2 kΩ/1000 pF load. It also has a resistor feedback network that allows the user to configure it for gains of 1 or 2. Table 6 shows the different output ranges that are possible. operation. Figure 13 and Figure 14 show the outputs of the AD7846 without and with the deglitcher. An additional feature is that the output buffer is configured as a track-and-hold amplifier. Although normally tracking its input, this amplifier is placed in a hold mode for approximately 2.5 μs after the leading edge of LDAC. This short state keeps the DAC output at its previous voltage while the AD7846 is internally changing to its new value. Thus, any glitches that occur in the transition are not seen at the output. In systems where the LDAC is tied permanently low, the deglitching is not in Rev. G | Page 12 of 24 RIN 10kΩ 10kΩ C1 VOUT DAC3 ONE SHOT LDAC Figure 22. Output Stage 08490-022 OUTPUT STAGE AD7846 UNIPOLAR BINARY OPERATION Figure 23 shows the AD7846 in the unipolar binary circuit configuration. The DAC is driven by the AD586 +5 V reference. Because RIN is tied to 0 V, the output amplifier has a gain of 2 and the output range is 0 V to +10 V. If a 0 V to +5 V range is required, RIN should be tied to VOUT, configuring the output stage for a gain of 1. Table 8 gives the code table for the circuit of Figure 23. +15V Table 8. Code Table for Figure 23 Binary Number in DAC Latch MSB LSB1 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 +5V 1 2 AD586 5 21 VCC VOUT 5 R1 10kΩ AD7846* 4 8 VREF– LSB = 10 V/216 = 10 V/65,536 = 152 μV. Offset and gain can be adjusted in Figure 23 as follows: • VOUT (0V TO +10V) RIN 6 • DGND 20 VSS SIGNAL GROUND *ADDITIONAL PINS OMITTED FOR CLARITY –15V 08490-023 8 C1 1µF 4 VDD 7 VREF+ 6 Analog Output (VOUT) +10 (65,535/65,536) V +10 (32,768/65,536) V +10 (1/65,536) V 0V Figure 23. Unipolar Binary Operation Rev. G | Page 13 of 24 To adjust offset, disconnect the VREF− input from 0 V, load the DAC with all 0s, and adjust the VREF− voltage until VOUT = 0 V. For gain adjustment, the AD7846 should be loaded with all 1s and R1 adjusted until VOUT = 10 (65,535)/(65,536) = 9.999847 V. If a simple resistor divider is used to vary the VREF− voltage, it is important that the temperature coefficients of these resistors match that of the DAC input resistance (−300 ppm/°C). Otherwise, extra offset errors are introduced over temperature. Many circuits do not require these offset and gain adjustments. In these circuits, R1 can be omitted. Pin 5 of the AD586 can be left open circuit and Pin 8 (VREF−) of the AD7846 tied to 0 V. AD7846 BIPOLAR OPERATION Figure 24 shows the AD7846 set up for ±10 V bipolar operation. The AD588 provides precision ±5 V tracking outputs that are fed to the VREF+ and VREF− inputs of the AD7846. The code table for Figure 24 is shown in Table 9. +15V +15V +5V For bipolar zero adjustment on the AD7846, load the DAC with 100…000 and adjust R3 until VOUT = 0 V. Full scale is adjusted by loading the DAC with all 1s and adjusting R2 until VOUT = 9.999694 V. R1 39kΩ C1 1µF 6 2 7 9 AD588 R2 10kΩ +15V 7 3 1 4 21 VDD VCC VREF+ VOUT 5 AD7846* 5 RIN 6 14 10 8 15 11 16 VREF– DGND 20 –15V VSS R3 100kΩ 12 8 VOUT (–10V TO +10V) 13 SIGNAL GROUND 9 –15V *ADDITIONAL PINS OMITTED FOR CLARITY Figure 24. Bipolar ±10 V Operation 08490-024 4 Full-scale and bipolar zero adjustment are provided by varying the gain and balance on the AD588. R2 varies the gain on the AD588 while R3 adjusts the +5 V and −5 V outputs together with respect to ground. When bipolar zero and full-scale adjustment are not needed, R2 and R3 can be omitted, Pin 12 on the AD588 should be connected to Pin 11, and Pin 5 should be left floating. If a user wants a 5 V output range, there are two choices. By tying Pin 6 (RIN) of the AD7846 to VOUT (Pin 5), the output stage gain is reduced to unity and the output range is ±5 V. If only a positive 5 V reference is available, bipolar ±5 V operation is still possible. Tie VREF− to 0 V and connect RIN to VREF+. This also gives a ±5 V output range. However, the linearity, gain, and offset error specifications are the same as the unipolar 0 V to 5 V range. Table 9. Offset Binary Code Table for Figure 24 MULTIPLYING OPERATION Binary Number in DAC Latch The AD7846 is a full multiplying DAC. To obtain four-quadrant multiplication, tie VREF− to 0 V, apply the ac input to VREF+, and tie RIN to VREF+. Figure 11 shows the large signal frequency response when the DAC is used in this fashion. MSB LSB1 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 1 Analog Output (VOUT) +10 (32,767/32,768) V +10 (1/32,768) V 0V −10 (1/32,768) V −10 (32,768/32,768) V LSB = 10 V/215 = 10 V/32,768 = 305 μV. Rev. G | Page 14 of 24 AD7846 POSITION MEASUREMENT APPLICATION ASIN ω t LVDT x ASIN ω t V 7 VREF+ OUT 5 RIN 6 AD7846* –(1–x) ASIN ω t 8 VREF– DGND 20 DB15 DB0 10 3 SIGNAL GROUND PROCESSOR DATA BUS 9 R1 100kΩ 10 16 AD630* 13 C1 1µF TO PROCESSOR PORT *ADDITIONAL PINS OMITTED FOR CLARITY Figure 25. AD7846 in Position Measurement Application Rev. G | Page 15 of 24 08490-027 Figure 25 shows the AD7846 in a position measurement application using an linear variable displacement transducer (LVDT), an AD630 synchronous demodulator and a comparator to make a 16-bit LVDT-to-digital converter. The LVDT is excited with a fixed frequency and fixed amplitude sine wave (usually 2.5 kHz, 2 V p-p). The outputs of the secondary coil are in antiphase and their relative amplitudes depend on the position of the core in the LVDT. The AD7846 output interpolates between these two inputs in response to the DAC input code. The AD630 is set up so that it rectifies the DAC output signal. Thus, if the output of the DAC is in phase with the VREF+ input, the inverting input to the comparator is positive, and if it is in phase with VREF−, the output is negative. By turning on each bit of the DAC in succession starting with the MSB and deciding to leave it on or turn it off based on the comparator output, a 16-bit measurement of the core position is obtained. AD7846 MICROPROCESSOR INTERFACING AD7846-TO-8086 INTERFACE AD7846-TO-MC68000 INTERFACE Figure 26 shows the 8086 16-bit processor interfacing to the AD7846. The double buffering feature of the DAC is not used in this circuit because LDAC is permanently tied to 0 V. AD0 to AD15 (the 16-bit data bus) are connected to the DAC data bus (DB0 to DB15). The 16-bit word is written to the DAC in one MOV instruction and the analog output responds immediately. In this example, the DAC address is 0xD000. Interfacing between the AD7846 and MC68000 is accomplished using the circuit of Figure 28. The following routine writes data to the DAC latches and then outputs the data via the DAC latch. 1000 MOVE.W #W, D0 The desired DAC data, W, is loaded into Data Register 0. W may be any value between 0 and 65535 (decimal) or 0 and FFFF (hexadecimal). MOVE.W D0, $E000 The data, W, is transferred between D0 and the DAC register. MOVE.W TRAP #228, D7 #14 Control is returned to the System Monitor using these two instructions. ADDRESS BUS ALE ADDRESS DECODE 16-BIT LATCH CS LDAC 8086 +5V CLR DEN AD7846* RD R/W WR DATA BUS DB0 TO DB15 08490-028 AD0 TO AD15 *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 26. AD7846-to-8086 Interface Circuit ADDRESS BUS ALE ADDRESS DECODE 16-BIT LATCH DS ADDRESS DECODE CS +5V DTACK AD7846* R/ W DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY LDAC DEN AD7846* RD R/W WR CLR DATA BUS +5V DB0 TO DB15 CS AD7846* LDAC R/W CLR +5V DB0 TO DB15 CS AD7846* LDAC R/W CLR +5V 08490-029 DB0 TO DB15 *LINEAR CIRCUITRY OMITTED FOR CLARITY CLR LDAC R/W D0 TO D15 CS ADDRESS BUS Figure 28. AD7846-to-MC68000 Interface 8086 AD0 TO AD15 A1 TO A23 MC68000 Figure 27. AD7846-to-8086 Interface: Multiple DAC System Rev. G | Page 16 of 24 DB0 TO DB15 08490-030 In a multiple DAC system, the double buffering of the AD7846 allows the user to simultaneously update all DACs. In Figure 27, a 16-bit word is loaded to the input latches of each of the DACs in sequence. Then, with one instruction to the appropriate address, CS4 (that is, LDAC) is brought low, updating all the DACs simultaneously. AD7846 DIGITAL FEEDTHROUGH the DAC from the noise source. Figure 29 shows an interface circuit that isolates the DAC from the bus. In the preceding interface configurations, most digital inputs to the AD7846 are directly connected to the microprocessor bus. Even when the device is not selected, these inputs are constantly changing. The high frequency logic activity on the bus can feed through the DAC package capacitance to show up as noise on the analog output. To minimize this digital feedthrough, isolate A1 TO A15 Note that to make use of the AD7846 readback feature using the isolation technique of Figure 29, the latch needs to be bidirectional. ADDRESS BUS ADDRESS DECODE CS MICROPROCESSOR +5V CLR LDAC R/W DIR D0 TO D15 DATA BUS B BUS G A BUS 2× 74LS245 *LINEAR CIRCUITRY OMITTED FOR CLARITY AD7846* DB0 TO DB15 08490-031 R/W Figure 29. AD7846 Interface Circuit Using Latches to Minimize Digital Feedthrough Rev. G | Page 17 of 24 AD7846 APPLICATION HINTS R1 to R5 represent lead and track resistances on the printed circuit board. R1 is the resistance between the analog power supply ground and the signal ground. Because current flowing in R1 is very low (bias current of AD588 sense amplifier), the effect of R1 is negligible. R2 and R3 represent track resistance between the AD588 outputs and the AD7846 reference inputs. Because of the force and sense outputs on the AD588, these resistances will also have a negligible effect on accuracy. NOISE In high resolution systems, noise is often the limiting factor. With a 10 V span, a 16-bit LSB is 152 μV (–96 dB). Thus, the noise floor must stay below −96 dB in the frequency range of interest. Figure 12 shows the noise spectral density for the AD7846. GROUNDING As well as noise, the other prime consideration in high resolution DAC systems is grounding. With an LSB size of 152 μV and a load current of 5 mA, 1 LSB of error can be introduced by series resistance of only 0.03 Ω. Figure 30 shows recommended grounding for the AD7846 in a typical application. ANALOG SUPPLY +15V 0V DIGITAL SUPPLY –15V +5V DGND PRINTED CIRCUIT BOARD LAYOUT Figure 31 shows the AD7846 in a typical application with the AD588 reference, producing an output analog voltage in the ±10 V range. Full-scale and bipolar zero adjustment are provided by Potentiometer R2 and Potentiometer R3. Latches (2 × 74LS245) isolate the DAC digital inputs from the active microprocessor bus and minimize digital feedthrough. R1 SIGNAL GROUND 2 9 16 4 1 R2 9 21 R4 is the resistance between the DAC output and the load. If RL is constant, then R4 introduces a gain error only that can be trimmed out in the calibration cycle. R5 is the resistance between the load and the analog common. If the output voltage is sensed across the load, R5 introduces a further gain error, which can be trimmed out. If, on the other hand, the output voltage is sensed at the analog supply common, R5 appears as part of the load and therefore introduces no errors. 20 7 6 AD7846* 3 15 R3 8 5 R4 VOUT (+5V TO –5V) RL 14 R5 *ADDITIONAL PINS OMITTED FOR CLARITY 08490-032 AD588* Figure 30. AD7846 Grounding Rev. G | Page 18 of 24 AD7846 +15V J1 C1 10µF 4 C12 1µF 21 DB15 10 C2 0.1µF 6 DB14 11 DB13 12 2 7 7 3 VREF+ AD7846 AD588 14 R2 100kΩ 8 VREF– –15V 9 16 C4 0.1µF 18 17 16 5 6 15 14 74LS245 7 8 13 12 9 11 10 1 C4/A4 C5/A5 C6/A6 C7/A7 C8/A8 C9/A9 C10/A10 C11/A11 19 C3 10µF VSS DB5 26 DB4 27 9 DB2 1 20 R3 100kΩ DGND +5V DB7 18 DB3 28 13 20 2 3 4 DB9 16 DB6 19 11 12 15 C31/A31 DB8 17 15 10 DB11 14 DB10 1 8 +5V C7 0.1µF DB12 13 5 C6 0.1µF DB1 2 DB0 3 20 2 18 3 4 17 16 5 6 74LS245 15 14 13 12 7 8 11 9 10 1 19 C12/A12 C13/A13 C14/A14 C15/A15 C16/A16 C17/A17 C18/A18 C19/A19 C20/A20 C21/A21 C22/A22 6 RIN R/W 22 C23/A23 C32/A32 CS 23 VOUT (+10V TO –10V) 5 VOUT CLR 24 LDAC 25 Figure 31. Schematic for AD7846 Board Rev. G | Page 19 of 24 08490-033 R1 39kΩ 4 C5 10µF AD7846 OUTLINE DIMENSIONS 0.005 (0.13) MIN 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.500 (12.70) 1 14 PIN 1 0.620 (15.75) 0.590 (14.99) 0.015 (0.38) MIN 1.490 (37.85) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.026 (0.66) 0.014 (0.36) 0.070 (1.78) SEATING 0.030 (0.76) PLANE 0.018 (0.46) 0.008 (0.20) 15° 0° CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 030106-A 0.225(5.72) MAX Figure 32. 28-Lead Ceramic Dual In-Line Package [CERDIP] (Q-28-2) Dimensions shown in inches and (millimeters) 1.565 (39.75) 1.380 (35.05) 28 15 0.580 (14.73) 0.485 (12.31) 1 14 0.625 (15.88) 0.600 (15.24) 0.100 (2.54) BSC 0.250 (6.35) MAX 0.195 (4.95) 0.125 (3.17) 0.015 (0.38) GAUGE PLANE 0.015 (0.38) MIN 0.200 (5.08) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.014 (0.36) 0.005 (0.13) MIN 0.700 (17.78) MAX 0.015 (0.38) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MS-011 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS. Figure 33. 28-Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-28-2) Dimensions shown in inches and (millimeters) Rev. G | Page 20 of 24 071006-A 0.070 (1.78) 0.050 (1.27) AD7846 0.300 (7.62) REF 0.075 (1.91) REF 0.020 (0.51) MIN 19 0.458 (11.63) SQ 0.442 (11.23) 0.028 (0.71) 0.022 (0.56) 25 26 18 0.05 (1.27) 0.458 (11.63) MAX SQ BOTTON VIEW 28 1 0.15 (3.81) REF 0.075 (1.91) REF 12 4 11 5 0.095 (2.41) 0.075 (1.90) 0.055 (1.40) 0.045 (1.14) 0.088 (2.24) 0.054 (1.37) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 022106-A 0.100 (2.54) 0.064 (1.63) Figure 34. 28-Terminal Ceramic Leadless Chip Carrier [LCC] (E-28-1) Dimensions shown in inches and (millimeters) 0.180 (4.57) 0.165 (4.19) 0.048 (1.22) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 4 5 PIN 1 IDENTIFIER 26 25 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC TOP VIEW (PINS DOWN) 11 12 0.020 (0.51) MIN 0.032 (0.81) 0.026 (0.66) 19 18 0.456 (11.582) SQ 0.450 (11.430) 0.495 (12.57) SQ 0.485 (12.32) 0.120 (3.04) 0.090 (2.29) 0.430 (10.92) 0.390 (9.91) BOTTOM VIEW (PINS UP) 0.045 (1.14) R 0.025 (0.64) COMPLIANT TO JEDEC STANDARDS MO-047-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 35. 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28) Dimensions shown in inches and (millimeters) Rev. G | Page 21 of 24 042508-A 0.048 (1.22) 0.042 (1.07) AD7846 ORDERING GUIDE Model 1 5962-89697013A 5962-8969701XA AD7846JN AD7846JNZ AD7846KN AD7846KNZ AD7846JP AD7846JP-REEL AD7846JPZ AD7846JPZ-REEL AD7846KP AD7846KP-REEL AD7846KPZ AD7846KPZ-REEL AD7846AP AD7846APZ AD7846AQ AD7846BP AD7846BPZ AD7846ACHIPS 1 Temperature Range −55°C to +125°C −55°C to +125°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Relative Accuracy ±16 LSB ±16 LSB ±16 LSB ±16 LSB ±8 LSB ±8 LSB ±16 LSB ±16 LSB ±16 LSB ±16 LSB ±8 LSB ±8 LSB ±8 LSB ±8 LSB ±16 LSB ±16 LSB ±16 LSB ±8 LSB ±8 LSB ±16 LSB Package Description 28-Terminal Ceramic Leadless Chip Carrier [LCC] 28-Lead Ceramic Dual In-Line Package [CERDIP] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Ceramic Dual In-Line Package [CERDIP] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] Z = RoHS Compliant Part. Rev. G | Page 22 of 24 Package Option E-28-1 Q-28-2 N-28-2 N-28-2 N-28-2 N-28-2 P-28 P-28 P-28 P-28 P-28 P-28 P-28 P-28 P-28 P-28 Q-28-2 P-28 P-28 DIE AD7846 NOTES Rev. G | Page 23 of 24 AD7846 NOTES ©2000–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08490-0-4/10(G) Rev. G | Page 24 of 24