Cypress CY14B104M-ZSP25XI 4-mbit (512 k x 8/256 k x 16) nvsram with real time clock 25 ns and 45 ns access time Datasheet

CY14B104K, CY14B104M
4-Mbit (512 K × 8/256 K × 16) nvSRAM
with Real Time Clock
4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock
Features
■
25 ns and 45 ns access times
■
Internally organized as 512 K × 8 (CY14B104K) or 256 K × 16
(CY14B104M)
■
Hands off automatic STORE on power-down with only a small
capacitor
■
STORE to QuantumTrap non-volatile elements is initiated by
software, device pin, or AutoStore on power-down
■
RECALL to SRAM is initiated by software or power-up
■
High reliability
■
Infinite read, write, and RECALL cycles
■
1 million STORE cycles to QuantumTrap
■
20 year data retention
■
Single 3 V +20%, –10% operation
■
Data integrity of Cypress nvSRAM combined with full-featured
real time clock (RTC)
■
Watchdog timer
■
Clock alarm with programmable interrupts
■
Capacitor or battery backup for RTC
■
Industrial temperature
■
44-pin and 54-pin thin small outline package (TSOP) Type II
■
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B104K and CY14B104M combines a 4-Mbit
non-volatile static RAM (nvSRAM) with a full-featured RTC in a
monolithic integrated circuit. The embedded non-volatile
elements incorporate QuantumTrap technology producing the
world’s most reliable non-volatile memory. The SRAM is read
and written infinite number of times, while independent
non-volatile data resides in the non-volatile elements.
Logic Block Diagram [1, 2, 3]
The RTC function provides an accurate clock with leap year
tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
Quatrum
Trap
2048 X 2048
A0
A1
A2
R
O
W
A3
A4
A5
A6
A7
A8
A17
A18
D
E
C
O
D
E
R
STORE
VCA
VCC
P
POWER
CONTROL
VRTCbat
VRTCcap
RECALL
STATIC RAM
ARRAY
2048 X 2048
STORE/RECALL
CONTROL
SOFTWARE
DETECT
HSB
A14 - A2
DQ0
DQ1
DQ2
DQ3
RTC
I
N
P
U
T
B
U
F
F
E
R
S
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
Xout
Xin
INT
COLUMN I/O
MUX
A18- A 0
OE
COLUMN DEC
WE
DQ12
DQ13
CE
DQ14
BLE
A9 A10 A11 A12 A13 A14 A15 A16
DQ15
BHE
Notes
1. Address A0–A18 for × 8 configuration and Address A0–A17 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-07103 Rev. *U
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 12, 2011
[+] Feedback
CY14B104K, CY14B104M
Contents
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
AutoStore Operation ........................................................ 4
Hardware STORE (HSB) Operation ................................. 5
Hardware RECALL (Power-Up) ....................................... 5
Software STORE ............................................................... 5
Software RECALL ............................................................. 5
Preventing AutoStore ....................................................... 6
Data Protection ................................................................. 7
Noise Considerations ....................................................... 7
Real Time Clock Operation .............................................. 7
nvTIME Operation ....................................................... 7
Clock Operations ......................................................... 7
Reading the Clock ....................................................... 7
Setting the Clock ......................................................... 7
Backup Power ............................................................. 7
Stopping and Starting the Oscillator ............................ 8
Calibrating the Clock ................................................... 8
Alarm ........................................................................... 8
Watchdog Timer .......................................................... 8
Power Monitor ............................................................. 9
Interrupts ..................................................................... 9
Flags Register ........................................................... 10
Best Practices ................................................................. 15
Maximum Ratings ........................................................... 16
Document #: 001-07103 Rev. *U
Operating Range ............................................................. 16
DC Electrical Characteristics ........................................ 16
Data Retention and Endurance ..................................... 17
Capacitance .................................................................... 17
Thermal Resistance ........................................................ 17
AC Test Loads ................................................................ 17
AC Test Conditions ........................................................ 17
RTC Characteristics ....................................................... 18
AC Switching Characteristics ....................................... 19
SRAM Read Cycle .................................................... 19
SRAM Write Cycle ..................................................... 19
AutoStore/Power-Up RECALL ....................................... 22
Switching Waveforms .................................................... 22
Software Controlled STORE and RECALL Cycle ........ 23
Hardware STORE Cycle ................................................. 24
Truth Table For SRAM Operations ................................ 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 29
Document Conventions ............................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 35
Worldwide Sales and Design Support ....................... 35
Products .................................................................... 35
PSoC Solutions ......................................................... 35
Page 2 of 35
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CY14B104K, CY14B104M
Pinouts
Figure 1. Pin Diagram – 44-pin and 54-pin TSOP II
INT
[5]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
Xout
Xin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
44-pin TSOP II
(x 8)
Top View
(not to scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
19
20
21
22
HSB
NC
[4]
NC
A18
A17
A16
A15
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
VCAP
A14
A13
A12
A11
A10
VRTCcap
VRTCbat
INT
[5]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
NC
Xout
Xin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
54-pin TSOP II
(x 16)
Top View
(not to scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
[4]
NC
A17
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
NC
VRTCcap
VRTCbat
Pin Definitions
Pin Name
I/O Type
A0 – A18
Input
A0 – A17
Description
Address inputs. Used to select one of the 524,288 bytes of the nvSRAM for × 8 configuration.
Address inputs. Used to select one of the 262,144 words of the nvSRAM for × 16 configuration.
DQ0 – DQ7 Input/Output Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation.
DQ0 – DQ15
NC
No connect
WE
Input
Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE
Input
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
Deasserting OE HIGH causes the I/O pins to tristate.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15–DQ8.
BLE
Xout
Input
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
Output
Xin
Input
OE
No connects. This pin is not connected to the die.
Crystal connection. Drives crystal on startup.
Crystal connection. For 32.768 kHz crystal.
VRTCcap
Power supply Capacitor supplied backup RTC supply voltage. Left unconnected if VRTCbat is used.
VRTCbat
Power supply Battery supplied backup RTC supply voltage. Left unconnected if VRTCcap is used.
INT
Output
Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power monitor.
Also programmable to either active HIGH (push or pull) or LOW (open drain).
Notes
4. Address expansion for 8-Mbit. NC pin not connected to die.
5. Address expansion for 16-Mbit. NC pin not connected to die.
Document #: 001-07103 Rev. *U
Page 3 of 35
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CY14B104K, CY14B104M
Pin Definitions (continued)
Pin Name
I/O Type
VSS
Ground
VCC
HSB
VCAP
Description
Ground for the device. Must be connected to ground of the system.
Power supply Power supply inputs to the device. 3.0 V +20%, –10%
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a non-volatile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
Device Operation
AutoStore Operation
The CY14B104K/CY14B104M nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a non-volatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the non-volatile cell (the
STORE operation), or from the non-volatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14B104K/CY14B104M supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the non-volatile cells and up to 1 million STORE
operations. See Truth Table For SRAM Operations on page 25
for a complete description of read and write modes.
The CY14B104K/CY14B104M stores data to the nvSRAM using
one of three storage operations. These three operations are:
Hardware STORE, activated by the HSB; Software STORE,
activated by an address sequence; AutoStore, on device
power-down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B104K/CY14B104M.
The CY14B104K/CY14B104M performs a read cycle when CE
and OE are LOW, and WE and HSB are HIGH. The address
specified on pins A0–18 or A0–17 determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of tAA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DO0–15
are written into the memory if it is valid tSD before the end of a
WE controlled write or before the end of an CE controlled write.
The Byte Enable inputs (BHE, BLE) determine which bytes are
written, in the case of 16-bit words. It is recommended that OE
be kept HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
Document #: 001-07103 Rev. *U
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 6. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 2. AutoStore Mode
VCC
0.1 uF
10 kOhm
SRAM Read
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
VCC
WE
VCAP
VSS
VCAP
Figure 2 on page 4 shows the proper connection of the storage
capacitor (VCAP) for automatic STORE operation. Refer to DC
Electrical Characteristics on page 16 for the size of the VCAP. The
voltage on the VCAP pin is driven to VCC by a regulator on the
Page 4 of 35
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CY14B104K, CY14B104M
chip. A pull-up should be placed on WE to hold it inactive during
power-up. This pull-up is effective only if the WE signal is tristate
during power-up. Many MPUs tristate their controls on power-up.
This should be verified when using the pull-up. When the
nvSRAM comes out of power-on-RECALL, the MPU must be
active or the WE held inactive until the MPU comes out of reset.
To reduce unnecessary non-volatile STOREs, AutoStore, and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B104K/CY14B104M provides the HSB pin to control
and acknowledge the STORE operations. The HSB pin is used
to request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B104K/CY14B104M conditionally initiates a
STORE operation after tDELAY. An actual STORE cycle begins
only if a write to the SRAM has taken place since the last STORE
or RECALL cycle. The HSB pin also acts as an open drain driver
(internal 100 k weak pull-up resistor) that is internally driven
LOW to indicate a busy condition when the STORE (initiated by
any means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B104K/CY14B104M. But any SRAM read and
write cycles are inhibited until HSB is returned HIGH by MPU or
other external source.
During any STORE operation, regardless of how it is initiated,
the CY14B104K/CY14B104M continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on powerup, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Document #: 001-07103 Rev. *U
Software STORE
Data is transferred from the SRAM to the non-volatile memory
by a software address sequence. The CY14B104K/CY14B104M
Software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in
exact order. During the STORE cycle, an erase of the previous
non-volatile data is first performed, followed by a program of the
non-volatile elements. After a STORE cycle is initiate, further
input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place. To initiate the Software
STORE cycle, the following read sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the non-volatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
perform the following sequence of CE or OE controlled read
operations:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the non-volatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
Page 5 of 35
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CY14B104K, CY14B104M
Table 1. Mode Selection
OE
X
BHE, BLE[6]
X
A15–A0[7]
X
Mode
I/O
Power
Not selected
Output High Z
Standby
H
L
L
X
Read SRAM
Output data
Active
L
X
L
X
Write SRAM
Input data
Active
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output data
Output data
Output data
Output data
Output data
Output data
Active[8]
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Output data
Output data
Output data
Output data
Output data
Output data
Active[8]
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
STORE
Output data
Output data
Output data
Output data
Output data
Output High Z
Active ICC2[8]
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
RECALL
Output data
Output data
Output data
Output data
Output data
Output High Z
Active[8]
CE
H
WE
X
L
L
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power-down cycles.
The part comes from the factory with AutoStore enabled.
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
Notes
6. BHE and BLE are applicable for × 16 configuration only.
7. While there are 19 address lines on the CY14B104K (18 address lines on the CY14B104M), only 13 address lines (A14–A2) are used to control software modes. The
remaining address lines are don’t care.
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document #: 001-07103 Rev. *U
Page 6 of 35
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CY14B104K, CY14B104M
Data Protection
The CY14B104K/CY14B104M protects data from corruption
during low-voltage conditions by inhibiting all externally initiated
STORE and write operations. The low-voltage condition is
detected when VCC is less than VSWITCH. If the
CY14B104K/CY14B104M is in a write mode (both CE and WE
are LOW) at power-up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after tLZHSB (HSB to output
active). This protects against inadvertent writes during power-up
or brown out conditions.
Noise Considerations
Refer to CY application note AN1064.
Real Time Clock Operation
nvTIME Operation
The CY14B104K/CY14B104M offers internal registers that
contain clock, alarm, watchdog, interrupt, and control functions.
RTC registers use the last 16 address locations of the SRAM.
Internal double buffering of the clock and timer information
registers prevents accessing transitional internal clock data
during a read or write operation. Double buffering also
circumvents disrupting normal timing counts or the clock
accuracy of the internal clock when accessing clock data. Clock
and alarm registers store data in BCD format.
RTC functionality is described with respect to CY14B104K in the
following sections. The same description applies to
CY14B104M, except for the RTC register addresses. The RTC
register addresses for CY14B104K range from 0x7FFF0 to
0x7FFFF, while those for CY14B104M range from 0x3FFF0 to
0x3FFFF. Refer to Table 3 on page 11 and Table 4 on page 12
for a detailed Register Map description.
Clock Operations
The clock registers maintain time up to 9,999 years in one
second increments. The time can be set to any calendar time and
the clock automatically keeps track of days of the week and
month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Setting the Clock
Setting the write bit ‘W’ (in the flags register at 0x7FFF0) to a ‘1’
stops updates to the time keeping registers and enables the time
to be set. The correct day, date, and time is then written into the
registers and must be in 24 hour BCD format. The time written is
referred to as the “Base Time”. This value is stored in non-volatile
registers and used in the calculation of the current time.
Resetting the write bit to ‘0’ transfers the values of timekeeping
registers to the actual clock counters, after which the clock
resumes normal operation.
If the time written to the timekeeping registers is not in the correct
BCD format, each invalid nibble of the RTC registers continue
counting to 0xF before rolling over to 0x0 after which RTC
resumes normal operation.
Note After ‘W’ bit is set to 0, values written into the timekeeping,
alarm, calibration, and interrupt registers are transferred to the
RTC time keeping counters in tRTCp time. These counter values
must be saved to non-volatile memory either by initiating a
Software/Hardware STORE or AutoStore operation. While
working in AutoStore disabled mode, perform a STORE
operation after tRTCp time while writing into the RTC registers for
the modifications to be correctly recorded.
Backup Power
The RTC in the CY14B104K is intended for permanently
powered operation. The VRTCcap or VRTCbat pin is connected
depending on whether a capacitor or battery is chosen for the
application. When the primary power, VCC, fails and drops below
VSWITCH the device switches to the backup power supply.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the non-volatile
elements when power was lost.
During backup operation, the CY14B104K consumes 0.35 µA
(Typical) at room temperature. The user must choose capacitor
or battery values according to the application.
Backup time values based on maximum current specifications
are shown in the following table. Nominal backup times are
approximately two times longer.
Table 2. RTC Backup Time
Capacitor Value
Backup Time
0.1 F
72 hours
Reading the Clock
0.47 F
14 days
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. The user must stop
internal updates to the CY14B104K time keeping registers
before reading clock data, to prevent reading of data in transition.
Stopping the register updates does not affect clock accuracy.
1.0 F
30 days
The updating process is stopped by writing a ‘1’ to the read bit
‘R’ (in the flags register at 0x7FFF0), and does not restart until a
‘0’ is written to the read bit. The RTC registers are then read while
the internal clock continues to run. After a ‘0’ is written to the read
bit (‘R’), all RTC registers are simultaneously updated within
20 ms.
Document #: 001-07103 Rev. *U
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, a 3 V lithium is recommended and the CY14B104K
sources current only from the battery when the primary power is
removed. However the battery is not recharged at any time by
the CY14B104K. The battery capacity must be chosen for total
anticipated cumulative down time required over the life of the
system.
Page 7 of 35
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CY14B104K, CY14B104M
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x7FFF8 controls
the enable and disable of the oscillator. This bit is non-volatile
and is shipped to customers in the enabled (set to ‘0’) state. To
preserve the battery life when the system is in storage, OSCEN
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately one second (two seconds maximum) for
the oscillator to start.
While system power is off, if the voltage on the backup supply
(VRTCcap or VRTCbat) falls below their respective minimum level,
the oscillator may fail.The CY14B104K has the ability to detect
oscillator failure when system power is restored. This is recorded
in the oscillator fail bit (OSCF) of the flags register at the address
0x7FFF0. When the device is powered on (VCC goes above
VSWITCH) the OSCEN bit is checked for enabled status. If the
OSCEN bit is enabled and the oscillator is not active within the
first 5 ms, the OSCF bit is set to ‘1’. The system must check for
this condition and then write ‘0’ to clear the flag. Note that in
addition to setting the OSCF flag bit, the time registers are reset
to the “Base Time” (see Setting the Clock on page 7), which is
the value last written to the timekeeping registers. The control or
calibration registers and the OSCEN bit are not affected by the
‘oscillator failed’ condition.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit
which may have been set when the system was first powered on.
To reset OSCF, set the write bit ‘W’ (in the flags register at
0x7FFF0) to a ‘1’ to enable writes to the Flag register. Write a ‘0’
to the OSCF bit and then reset the write bit to ‘0’ to disable writes.
Calibrating the Clock
The RTC is driven by a quartz controlled crystal with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal and calibration. The crystals available in market
typically have an error of +20 ppm to +35 ppm. However,
CY14B104K employs a calibration circuit that improves the
accuracy to +1/–2 ppm at 25 °C. This implies an error of
+2.5 seconds to –5 seconds per month.
The calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in calibration register at 0x7FFF8. The
calibration bits occupy the five lower order bits in the calibration
register. These bits are set to represent any value between ‘0’
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates
positive calibration and a ‘0’ indicates negative calibration.
Adding counts speeds the clock up and subtracting counts slows
the clock down. If a binary ‘1’ is loaded into the register, it
corresponds to an adjustment of 4.068 or –2.034 ppm offset in
oscillator error, depending on the sign.
Calibration occurs within a 64-minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the
64-minute cycle are modified. If a binary 6 is loaded, the first 12
are affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
Document #: 001-07103 Rev. *U
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment per calibration step in the calibration register.
To determine the required calibration, the CAL bit in the flags
register (0x7FFF0) must be set to ‘1’. This causes the INT pin to
toggle at a nominal frequency of 512 Hz. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
indicates a +20 ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the calibration register to offset
this error.
Note Setting or changing the calibration register does not affect
the test output frequency.
To set or clear CAL, set the write bit ‘W’ (in the flags register at
0x7FFF0) to ‘1’ to enable writes to the flags register. Write a
value to CAL, and then reset the write bit to ‘0’ to disable writes.
Alarm
The alarm function compares user programmed values of alarm
time and date (stored in the registers 0x7FFF1–5) with the
corresponding time of day and date values. When a match
occurs, the alarm internal flag (AF) is set and an interrupt is
generated on INT pin if alarm interrupt enable (AIE) bit is set.
There are four alarm match fields - date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x7FFF0 indicates that a date or time match has occurred. The
AF bit is set to ‘1’ when a match occurs. Reading the flags
register clears the alarm flag bit (and all others). A hardware
interrupt pin may also be used to detect an alarm event.
To set, clear or enable an alarm, set the ‘W’ bit (in flags register
- 0x7FFF0) to ‘1’ to enable writes to alarm registers. After writing
the alarm value, clear the ‘W’ bit back to ‘0’ for the changes to
take effect.
Note CY14B104K requires the alarm match bit for seconds
(0x7FFF2–D7) to be set to ‘0’ for proper operation of alarm flag
and Interrupt.
Watchdog Timer
The watchdog timer is a free running down counter that uses the
32-Hz clock (31.25 ms) derived from the crystal oscillator. The
oscillator must be running for the watchdog to function. It begins
counting down from the value loaded in the watchdog timer
register.
The timer consists of a loadable register and a free running
counter. On power-up, the watchdog time out value in register
0x7FFF7 is loaded into the counter load register. Counting
begins on power-up and restarts from the loadable value any
time the watchdog strobe (WDS) bit is set to ‘1’. The counter is
compared to the terminal value of ‘0’. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
Page 8 of 35
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CY14B104K, CY14B104M
You can prevent the time out interrupt by setting WDS bit to ‘1’
prior to the counter reaching ‘0’. This causes the counter to
reload with the watchdog time out value and to be restarted. As
long as the user sets the WDS bit prior to the counter reaching
the terminal value, the interrupt and WDT flag never occur.
New time out values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out
value bits D5–D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5–D0 are ignored. The WDW function
enables a user to set the WDS bit without concern that the
watchdog timer value is modified. A logical diagram of the
watchdog timer is shown in Figure 3. Note that setting the
watchdog time out value to ‘0’ disables the watchdog function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. If the watchdog interrupt
enable (WIE) bit in the interrupt register is set, a hardware
interrupt on INT pin is also generated on watchdog timeout. The
flag and the hardware interrupt are both cleared when user reads
the flags registers.
Figure 3. Watchdog Timer Block Diagram
Clock
Divider
Oscillator
32,768 KHz
1 Hz
Zero
Compare
WDF
Load
Register
WDS
Q
D
WDW
Q
write to
Watchdog
Register
Watchdog
Register
.
Power Monitor
The CY14B104K provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protects the memory from low
VCC access. The power monitor is based on an internal band gap
reference circuit that compares the VCC voltage to VSWITCH
threshold.
As described in the section AutoStore Operation on page 4,
when VSWITCH is reached as VCC decays from power loss, a data
STORE operation is initiated from SRAM to the non-volatile
elements, securing the last SRAM data state. Power is also
switched from VCC to the backup supply (battery or capacitor) to
operate the RTC oscillator.
When operating from the backup source, read and write
operations to nvSRAM are inhibited and the RTC functions are
not available to the user. The RTC clock continues to operate in
the background. The updated RTC time keeping registers data
are available to the user after VCC is restored to the device (see
AutoStore/Power-Up RECALL on page 22).
Document #: 001-07103 Rev. *U
The CY14B104K has flags register, interrupt register, and
interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog timer,
power monitor, and alarm timer. Each of these can be individually
enabled to drive the INT pin by appropriate setting in the Interrupt
register (0x7FFF6). In addition, each has an associated flag bit
in the flags register (0x7FFF0) that the host processor uses to
determine the cause of the interrupt. The INT pin driver has two
bits that specify its behavior when an interrupt occurs.
An interrupt is raised only if both a flag is raised by one of the
three sources and the respective interrupt enable bit in interrupts
register is enabled (set to ‘1’). After an interrupt source is active,
two programmable bits, H/L and P/L, determine the behavior of
the output pin driver on INT pin. These two bits are located in the
interrupt register and can be used to drive level or pulse mode
output from the INT pin. In pulse mode, the pulse width is
internally fixed at approximately 200 ms. This mode is intended
to reset a host microcontroller. In the level mode, the pin goes to
its active polarity until the flags register is read by the user. This
mode is used as an interrupt to a host microcontroller. The
control bits are summarized in the following section.
Interrupts are only generated while working on normal power and
are not triggered when system is running in backup power mode.
32 Hz
Counter
Interrupts
Note CY14B104K generates valid interrupts only after the
Power-up RECALL sequence is completed. All events on INT pin
must be ignored for tHRECALL duration after powerup.
Interrupt Register
Watchdog Interrupt Enable (WIE): When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog time out occurs. When WIE is set to ‘0’, the watchdog
timer only affects the WDF flag in flags register.
Alarm Interrupt Enable (AIE): When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When AIE is set to ‘0’, the
alarm match only affects the AF flag in flags register.
Power Fail Interrupt Enable (PFE): When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When PFE is set
to ‘0’, the power fail monitor only affects the PF flag in flags
register.
High/Low (H/L): When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives HIGH only
when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin
is active LOW and the drive mode is open drain. The INT pin
must be pulled up to Vcc by a 10 k resistor while using the
interrupt in active LOW mode.
Pulse/Level (P/L): When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven HIGH or LOW (determined by H/L) until
the flags register is read.
When an enabled interrupt source activates the INT pin, an
external host reads the flags registers to determine the cause.
Remember that all flags are cleared when the register is read. If
the INT pin is programmed for Level mode, then the condition
clears and the INT pin returns to its inactive state. If the pin is
programmed for pulse mode, then reading the flag also clears
the flag and the pin. The pulse does not complete its specified
duration if the flags register is read. If the INT pin is used as a
host reset, the flags register is not read during a reset.
Page 9 of 35
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CY14B104K, CY14B104M
Flags Register
The flags register has three flag bits: WDF, AF, and PF, which can be used to generate an interrupt. These flags are set by the watchdog
timeout, alarm match, or power fail monitor respectively. The processor can either poll this register or enable interrupts when a flag
is set. These flags are automatically reset when the register is read. The flags register is automatically loaded with the value 0x00 on
power-up (except for the OSCF bit. See Stopping and Starting the Oscillator on page 8).
Figure 4. RTC Recommended Component Configuration
Recommended Values
Y1 = 32.768 kHz (12.5 pF)
C1 = 12 pF
C2 = 69 pF
Note The recommended values for C1 and C2 include
board trace capacitance.
C1
Y1
C2
Xout
Xin
Figure 5. Interrupt Block Diagram
WDF
Watchdog
Timer
WIE
P/L
VCC
PF
Power
Monitor
PFE
Pin
Driver
INT
VINT
H/L
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
Enable
PF - Power Fail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
VSS
AF
Clock
Alarm
AIE
Document #: 001-07103 Rev. *U
Page 10 of 35
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CY14B104K, CY14B104M
Table 3. RTC Register Map [9]
BCD Format Data[10]
Register
CY14B104K
CY14B104M
D7
D6
D5
D4
0
10s months
D3
D2
D1
Function/Range
0x7FFFF
0x3FFFF
0x7FFFE
0x3FFFE
0
0
0x7FFFD
0x3FFFD
0
0
0x7FFFC
0x3FFFC
0
0
0x7FFFB
0x3FFFB
0
0
0x7FFFA
0x3FFFA
0
10s minutes
Minutes
Minutes: 00–59
0x7FFF9
0x3FFF9
0
10s seconds
Seconds
Seconds: 00–59
0x7FFF8
0x3FFF8
OSCEN (0)
0
0x7FFF7
0x3FFF7
WDS (0)
WDW (0)
0x7FFF6
0x3FFF6
WIE (0)
AIE (0)
0x7FFF5
0x3FFF5
M (1)
0
0x7FFF4
0x3FFF4
M (1)
0
Alarm hours
Alarm, hours: 00–23
0x7FFF3
0x3FFF3
M (1)
10s alarm minutes
Alarm minutes
Alarm, minutes: 00–59
0x7FFF2
0x3FFF2
M (1)
10s alarm seconds
Alarm, seconds
Alarm, seconds: 00–59
Centuries
Centuries: 00–99
0x7FFF1
0x3FFF1
0x7FFF0
0x3FFF0
10s years
D0
10s day of month
0
0
AF
Years: 00–99
Months: 01–12
Day of month
Day of month: 01–31
0
Day of week
10s hours
Day of week: 01–07
Hours
Cal sign (0)
Hours: 00–23
Calibration values [11]
Calibration (00000)
Watchdog [11]
WDT (000000)
PFE (0)
0
H/L (1)
10s alarm date
10s alarm hours
PF
OSCF[12]
P/L (0)
0
0
Alarm day
10s Centuries
WDF
Years
Months
0
CAL (0)
W (0)
Interrupts [11]
Alarm, day of month: 01–31
R (0)
Flags[11]
Notes
9. Upper byte D15–D8 (CY14B104M) of RTC registers are reserved for future use.
10. ( ) designates values shipped from the factory.
11. This is a binary value, not a BCD value.
12. When user resets OSCF flag bit, the flags register will be updated after tRTCp time.
Document #: 001-07103 Rev. *U
Page 11 of 35
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CY14B104K, CY14B104M
Table 4. Register Map Detail
Register
CY14B104K
CY14B104M
0x7FFFF
0x3FFFF
0x7FFFE
0x3FFFE
0x7FFFD
0x3FFFD
0x7FFFC
0x3FFFC
0x7FFFB
0x3FFFB
0x7FFFA
0x3FFFA
0x7FFF9
0x3FFF9
Document #: 001-07103 Rev. *U
Description
Time Keeping - Years
D5
D4
D3
D2
D1
D0
10s years
Years
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years;
upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The
range for the register is 0–99.
Time Keeping - Months
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
10s month
Months
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range
for the register is 1–12.
Time Keeping - Date
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s day of month
Day of month
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit
and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3.
The range for the register is 1–31. Leap years are automatically adjusted for.
Time Keeping - Day
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
Day of week
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a
ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day
value, because the day is not integrated with the date.
Time Keeping - Hours
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s hours
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower
digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from
0 to 2. The range for the register is 0–23.
Time Keeping - Minutes
D7
D6
D5
D4
D3
D2
D1
D0
0
10s minutes
Minutes
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5.
The range for the register is 0–59.
Time Keeping - Seconds
D7
D6
D5
D4
D3
D2
D1
D0
0
10s seconds
Seconds
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range
for the register is 0–59.
D7
D6
Page 12 of 35
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CY14B104K, CY14B104M
Table 4. Register Map Detail (continued)
Register
CY14B104K
CY14B104M
0x7FFF8
0x3FFF8
OSCEN
Calibration Sign
Calibration
0x7FFF7
0x3FFF7
WDS
WDW
WDT
0x7FFF6
0x3FFF6
WIE
AIE
PFE
0
H/L
P/L
0x7FFF5
0x3FFF5
M
Document #: 001-07103 Rev. *U
Description
Calibration/Control
D5
D4
D3
D2
D1
D0
Calibration
Calibration
sign
Oscillator enable. When set to ‘1’, the oscillator is stopped. When set to ‘0’, the oscillator runs.
Disabling the oscillator saves battery or capacitor power during storage.
Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from
the time-base.
These five bits control the calibration of the clock.
WatchDog Timer
D7
D6
D5
D4
D3
D2
D1
D0
WDS
WDW
WDT
Watchdog strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to
‘0’ has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit
is write only. Reading it always returns a ‘0’.
Watchdog write enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value
(D5–D0). This allows the user to set the watchdog strobe bit without disturbing the timeout value.
Setting this bit to 0 allows bits D5–D0 to be written to the watchdog register when the next write
cycle is complete. This function is explained in more detail in Watchdog Timer on page 8.
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this
register. It represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is
31.25 ms (a setting of ‘1’) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to ‘0’
disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle.
Interrupt Status/Control
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFE
0
H/L
P/L
0
0
Watchdog interrupt enable. When set to ‘1’ and a watchdog timeout occurs, the watchdog timer
drives the INT pin and the WDF flag. When set to ‘0’, the watchdog timeout affects only the WDF
flag.
Alarm interrupt enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When
set to ‘0’, the alarm match only affects the AF flag.
Power fail enable. When set to ‘1’, the power fail monitor drives the INT pin and the PF flag. When
set to ‘0’, the power fail monitor affects only the PF flag.
Reserved for future use
High/Low. When set to ‘1’, the INT pin is driven active HIGH. When set to ‘0,’ the INT pin is open
drain, active LOW.
Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source
for approximately 200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L)
until the flags register is read.
Alarm - Day
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s alarm date
Alarm date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date
value.
Match. When this bit is set to ‘0’, the date value is used in the alarm match. Setting this bit to ‘1’
causes the match circuit to ignore the date value.
D7
OSCEN
D6
0
Page 13 of 35
[+] Feedback
CY14B104K, CY14B104M
Table 4. Register Map Detail (continued)
Register
CY14B104K
CY14B104M
0x7FFF4
0x3FFF4
M
0x7FFF3
0x3FFF3
M
0x7FFF2
0x3FFF2
M
0x7FFF1
0x3FFF1
0x7FFF0
0x3FFF0
WDF
AF
PF
OSCF
CAL
W
R
Document #: 001-07103 Rev. *U
Description
Alarm - Hours
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s alarm hours
Alarm hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’
causes the match circuit to ignore the hours value.
Alarm - Minutes
D7
D6
D5
D4
D3
D2
D1
D0
M
10s alarm minutes
Alarm minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
Match. When this bit is set to ‘0’, the minutes value is used in the alarm match. Setting this bit to
‘1’ causes the match circuit to ignore the minutes value.
Alarm - Seconds
D7
D6
D5
D4
D3
D2
D1
D0
M
10s alarm seconds
Alarm seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
Match. When this bit is set to ‘0,’ the seconds value is used in the alarm match. Setting this bit to
‘1’ causes the match circuit to ignore the seconds value.
Time Keeping - Centuries
D7
D6
D5
D4
D3
D2
D1
D0
10s centuries
Centuries
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0
to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is
0-99 centuries.
Flags
D7
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
OSCF
0
CAL
W
R
Watchdog timer flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach
0 without being reset by the user. It is cleared to 0 when the flags register is read or on power-up
Alarm flag. This read only bit is set to ‘1’ when the time and date match the values stored in the
alarm registers with the match bits = 0. It is cleared when the flags register is read or on power-up.
Power fail flag. This read only bit is set to ‘1’ when power falls below the power fail threshold
VSWITCH. It is cleared to 0 when the flags register is read or on power-up.
Oscillator fail flag. Set to ‘1’ on power-up if the oscillator is enabled and not running in the first
5 ms of operation. This indicates that RTC backup power failed and clock value is no longer valid.
This bit survives the power cycle and is never cleared internally by the chip. The user must check
for this condition and write '0' to clear this flag. When user resets OSCF flag bit, the bit will be
updated after tRTCp time.
Calibration mode. When set to ‘1’, a 512 Hz square wave is output on the INT pin. When set to
‘0’, the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power-up.
Write enable: Setting the ‘W’ bit to ‘1’ freezes updates of the RTC registers. The user can then
write to RTC registers, alarm registers, calibration register, interrupt register and flags register.
Setting the ‘W’ bit to ‘0’ causes the contents of the RTC registers to be transferred to the time
keeping counters if the time has changed. This transfer process takes tRTCp time to complete.
This bit defaults to 0 on power-up.
Read enable: Setting ‘R’ bit to ‘1’, stops clock updates to user RTC registers so that clock updates
are not seen during the reading process. Set ‘R’ bit to ‘0’ to resume clock updates to the holding
register. Setting this bit does not require ‘W’ bit to be set to ‘1’. This bit defaults to 0 on power-up.
Page 14 of 35
[+] Feedback
CY14B104K, CY14B104M
Best Practices
■
Power-up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, AutoStore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this maximum VCAP value. Customers
that want to use a larger VCAP value to make sure there is extra
store charge and store time should discuss their VCAP size
selection with Cypress to understand any impact on the VCAP
voltage level at the end of a tRECALL period.
■
When base time is updated, these updates are transferred to
the time keeping registers when ‘W’ bit is set to ‘0’. This transfer
takes tRTCp time to complete. It is recommended to initiate
software STORE or Hardware STORE after tRTCp time to save
the base time into non-volatile memory.
nvSRAM products have been used effectively for over 27 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The non-volatile cells in this nvSRAM product are delivered
from Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
Document #: 001-07103 Rev. *U
Page 15 of 35
[+] Feedback
CY14B104K, CY14B104M
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Maximum accumulated storage time
Surface mount Pb soldering
temperature (3 Seconds) ......................................... +260 C
At 150 C ambient temperature ................................. 1000 h
DC output current (1 output at a time, 1s duration) .... 15 mA
At 85 C ambient temperature ................................ 20 Years
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Ambient temperature with
power applied .......................................... –55 C to +150 C
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VCC + 0.5 V
Input voltage ....................................... –0.5 V to VCC + 0.5 V
Latch up current..................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
–40 C to +85 C
2.7 V to 3.6 V
Industrial
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7 V to 3.6 V)
Parameter
VCC
ICC1
Description
Power supply
Average VCC current
ICC2
Average VCC current during
STORE
Average VCC current at
tRC = 200 ns, VCC(Typ), 25 °C
ICC3
ICC4
ISB
IIX[14]
Average VCAP current during
AutoStore cycle
VCC standby current
IOZ
Input leakage current (except
HSB)
Input leakage current (for HSB)
Off state output leakage current
VIH
VIL
VOH
VOL
VCAP[15]
Input HIGH voltage
Input LOW voltage
Output HIGH voltage
Output LOW voltage
Storage capacitor
Test Conditions
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads
(IOUT = 0 mA)
All inputs don’t care, VCC = Max.
Average current for duration tSTORE
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA).
All inputs don’t care.
Average current for duration tSTORE
CE > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
W bit set to ‘0’. Standby current level
after non-volatile cycle is complete.
Inputs are static. f = 0 MHz.
VCC = Max, VSS < VIN < VCC
VCC = Max, VSS < VIN < VCC
VCC = Max, VSS < VOUT < VCC,
CE or OE > VIH or BHE/BLE > VIH or
WE < VIL
Min
2.7
–
Typ[13]
3.0
–
Max
3.6
70
52
Unit
V
mA
mA
–
–
10
mA
–
35
–
mA
–
–
5
mA
–
–
5
mA
–1
–
+1
A
–100
–1
–
–
+1
+1
A
A
–
–
–
–
68
VCC + 0.5
0.8
–
0.4
180
V
V
V
V
F
2.0
VSS – 0.5
IOUT = –2 mA
2.4
IOUT = 4 mA
–
Between VCAP pin and VSS, 5 V rated
61
Notes
13. Typical values are at 25 °C, VCC= VCC(Typ). Not 100% tested.
14. The HSB pin has IOUT = –2 µA for VOH of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
15. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on
VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it
is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options.
Document #: 001-07103 Rev. *U
Page 16 of 35
[+] Feedback
CY14B104K, CY14B104M
Data Retention and Endurance
Over the Operating Range
Parameter
Description
DATAR
Data retention
NVC
Non-volatile STORE operations
Min
Unit
20
Years
1,000
K
Capacitance
Parameter[16]
CIN
Description
Test Conditions
Max
Unit
7
pF
Input capacitance (for BHE, BLE
and HSB)
8
pF
Output capacitance (except
HSB)
7
pF
Output capacitance (for HSB)
8
pF
Input capacitance (except BHE,
BLE and HSB)
COUT
TA = 25 C, f = 1 MHz, VCC = VCC(Typ)
Thermal Resistance
Parameter[16]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
44-pin TSOP II
54-pin TSOP II
Unit
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, in
accordance with EIA/JESD51.
43.3
42.03
C/W
5.56
6.08
C/W
AC Test Loads
Figure 6. AC Test Loads
577 
577 
3.0 V
3.0 V
R1
R1
OUTPUT
OUTPUT
30 pF
R2
789 
5 pF
R2
789 
AC Test Conditions
Input pulse levels....................................................0 V to 3 V
Input rise and fall times (10%–90%)............................ < 3 ns
Input and output timing reference levels........................ 1.5 V
Note
16. These parameters are only guaranteed by design and are not tested.
Document #: 001-07103 Rev. *U
Page 17 of 35
[+] Feedback
CY14B104K, CY14B104M
RTC Characteristics
Over the Operating Range
Parameters
Description
VRTCbat
RTC battery pin voltage
IBAK[18]
RTC backup current
VRTCcap[19]
RTC capacitor pin voltage
Min
Typ [17]
Max
Units
1.8
3.0
3.6
V
TA (Min)
–
–
0.35
A
25 °C
–
0.35
–
A
TA (Max)
–
–
0.5
A
TA (Min)
1.6
–
3.6
V
25 °C
1.5
3.0
3.6
V
TA (Max)
1.4
–
3.6
V
tOCS
RTC oscillator time to start
–
1
2
sec
tRTCp
RTC processing time from end of ‘W’ bit set to ‘0’
–
–
350
s
RBKCHG
RTC backup capacitor charge current-limiting resistor
350
–
850

Notes
17. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested.
18. From either VRTCcap or VRTCbat.
19. If VRTCcap > 0.5 V or if no capacitor is connected to VRTCcap pin, the oscillator starts in tOCS time. If a backup capacitor is connected and VRTCcap < 0.5 V, the capacitor
must be allowed to charge to 0.5 V for oscillator to start.
Document #: 001-07103 Rev. *U
Page 18 of 35
[+] Feedback
CY14B104K, CY14B104M
AC Switching Characteristics
Over the Operating Range
Parameters [20]
Cypress
Alt Parameter
Parameter
25 ns
Description
45 ns
Unit
Min
Max
Min
Max
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
Byte enable to output active
Byte disable to output inactive
–
25
–
–
3
3
–
0
–
0
–
–
0
–
25
–
25
12
–
–
10
–
10
–
25
12
–
10
–
45
–
–
3
3
–
0
–
0
–
–
0
–
45
–
45
20
–
–
15
–
15
–
45
20
–
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
25
20
20
10
0
20
0
0
–
3
20
–
–
–
–
–
–
–
–
10
–
–
45
30
30
15
0
30
0
0
–
3
30
–
–
–
–
–
–
–
–
15
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRAM Read Cycle
tACE
tRC [21]
tAA [22]
tDOE
tOHA[22]
tLZCE [23, 24]
tHZCE [23, 24]
tLZOE [23, 24]
tHZOE [23, 24]
tPU [23]
tPD [23]
tDBE
tLZBE[23]
tHZBE[23]
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
–
–
–
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tHZWE [23, 24, 25]
tLZWE [23, 24]
tBW
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
tOW
–
Switching Waveforms
Figure 7. SRAM Read Cycle 1 (Address Controlled) [21, 22, 26]
tRC
Address
Address Valid
tAA
Data Output
Previous Data Valid
Output Data Valid
tOHA
Notes
20. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 6 on page 17.
21. WE must be HIGH during SRAM read cycles.
22. Device is continuously selected with CE, OE and BHE / BLE LOW.
23. These parameters are only guaranteed by design and are not tested.
24. Measured ±200 mV from steady state output voltage.
25. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
26. HSB must remain HIGH during read and write cycles.
Document #: 001-07103 Rev. *U
Page 19 of 35
[+] Feedback
CY14B104K, CY14B104M
Switching Waveforms (continued)
Figure 8. SRAM Read Cycle 2 (CE and OE Controlled) [27, 28, 29]
Address
Address Valid
tRC
tHZCE
tACE
CE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
Data Output
High Impedance
Output Data Valid
tPU
ICC
tPD
Active
Standby
Figure 9. SRAM Write Cycle 1 (WE Controlled) [27, 29, 30, 31]
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
tSA
tSD
Data Input
Input Data Valid
tHZWE
Data Output
tHD
Previous Data
tLZWE
High Impedance
Notes
27. BHE and BLE are applicable for × 16 configuration only.
28. WE must be HIGH during SRAM read cycles.
29. HSB must remain HIGH during read and write cycles.
30. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
31. CE or WE must be VIH during address transitions.
Document #: 001-07103 Rev. *U
Page 20 of 35
[+] Feedback
CY14B104K, CY14B104M
Switching Waveforms (continued)
Figure 10. SRAM Write Cycle 2 (CE Controlled) [32, 33, 34, 35]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Figure 11. SRAM Write Cycle 3 (BHE and BLE Controlled) [33, 34, 35, 36, 37]
(Not applicable for RTC register writes)
tWC
Address
Address Valid
tSCE
CE
tSA
tHA
tBW
BHE, BLE
tAW
tPWE
WE
tSD
Data Input
tHD
Input Data Valid
High Impedance
Data Output
Notes
32. BHE and BLE are applicable for × 16 configuration only.
33. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
34. HSB must remain HIGH during read and write cycles.
35. CE or WE must be VIH during address transitions.
36. While there are 19 address lines on the CY14B104K (18 address lines on the CY14B104M), only 13 address lines (A14–A2) are used to control software modes. The
remaining address lines are don’t care.
37. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.
Document #: 001-07103 Rev. *U
Page 21 of 35
[+] Feedback
CY14B104K, CY14B104M
AutoStore/Power-Up RECALL
Over the Operating Range
Parameter
tHRECALL [38]
tSTORE [39]
tDELAY [40]
VSWITCH
tVCCRISE[41]
VHDIS[41]
tLZHSB[41]
tHHHD[41]
CY14B104K/CY14B104M
Min
Max
–
20
–
8
–
25
–
2.65
150
–
–
1.9
–
5
–
500
Description
Power-Up RECALL duration
STORE cycle duration
Time allowed to complete SRAM write cycle
Low-voltage trigger level
VCC rise time
HSB output disable voltage
HSB to output active time
HSB High active time
Unit
ms
ms
ns
V
s
V
s
ns
Switching Waveforms
Figure 12. AutoStore or Power-Up RECALL[42]
VCC
VSWITCH
VHDIS
t VCCRISE
Note
tHHHD
Note39
tSTORE
Note
tHHHD
43
39
tSTORE
Note
43
HSB OUT
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
38. tHRECALL starts from the time VCC rises above VSWITCH.
39. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place.
40. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
41. These parameters are only guaranteed by design and are not tested.
42. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
43. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document #: 001-07103 Rev. *U
Page 22 of 35
[+] Feedback
CY14B104K, CY14B104M
Software Controlled STORE and RECALL Cycle
Over the Operating Range
Parameter [44, 45]
tRC
tSA
tCW
tHA
tRECALL
tSS [46, 47]
25 ns
Description
45 ns
Min
25
0
20
0
–
–
STORE/RECALL initiation cycle time
Address setup time
Clock pulse width
Address hold time
RECALL duration
Soft sequence processing time
Max
–
–
–
–
200
100
Min
45
0
30
0
–
–
Max
–
–
–
–
200
100
Unit
ns
ns
ns
ns
s
s
Switching Waveforms
Figure 13. CE and OE Controlled Software STORE and RECALL Cycle [45]
tRC
Address
tRC
Address #1
tSA
Address #6
tCW
tCW
CE
tHA
tSA
tHA
tHA
tHA
OE
tHHHD
HSB (STORE only)
tHZCE
tLZCE
t DELAY
48
Note
tLZHSB
High Impedance
tSTORE/tRECALL
DQ (DATA)
RWI
Figure 14. Autostore Enable and Disable Cycle
Address
tSA
CE
tRC
tRC
Address #1
Address #6
tCW
tCW
tHA
tSA
tHA
tHA
tHA
OE
tLZCE
tHZCE
tSS
48
Note
t DELAY
DQ (DATA)
Notes
44. The software sequence is clocked with CE controlled or OE controlled reads.
45. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles.
46. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command.
47. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
48. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
Document #: 001-07103 Rev. *U
Page 23 of 35
[+] Feedback
CY14B104K, CY14B104M
Hardware STORE Cycle
Over the Operating Range
Parameter
CY14B104K/CY14B104M
Description
Min
Max
Unit
tDHSB
HSB to output active time when write latch not set
–
25
ns
tPHSB
Hardware STORE pulse width
15
–
ns
Switching Waveforms
Figure 15. Hardware STORE Cycle [49]
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
tLZHSB
DQ (Data Out)
RWI
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100 kOhm resistor,
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
HSB (IN)
HSB (OUT)
tDELAY
tDHSB
tDHSB
RWI
Figure 16. Soft Sequence Processing [50, 51]
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
tSS
Soft Sequence
Command
Address #1
tSS
Address #6
tCW
CE
VCC
Notes
49. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place.
50. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command.
51. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document #: 001-07103 Rev. *U
Page 24 of 35
[+] Feedback
CY14B104K, CY14B104M
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
Table 5. Truth Table for × 8 Configuration
Inputs and Outputs[52]
CE
WE
OE
Mode
Power
H
X
X
High Z
Deselect/Power-down
Standby
L
H
L
Data out (DQ0–DQ7)
Read
Active
L
H
H
High Z
Output disabled
Active
L
L
X
Data in (DQ0–DQ7)
Write
Active
Table 6. Truth Table for × 16 Configuration
BHE[53]
BLE[53]
Inputs and Outputs[52]
CE
WE
OE
Mode
Power
H
X
X
X
X
High Z
Deselect/Power-down
Standby
L
X
X
H
H
High Z
Output disabled
Active
L
H
L
L
L
Data out (DQ0–DQ15)
Read
Active
L
H
L
H
L
Data out (DQ0–DQ7);
DQ8–DQ15 in High Z
Read
Active
L
H
L
L
H
Data out (DQ8–DQ15);
DQ0–DQ7 in High Z
Read
Active
L
H
H
L
L
High Z
Output disabled
Active
L
H
H
H
L
High Z
Output disabled
Active
L
H
H
L
H
High Z
Output disabled
Active
L
L
X
L
L
Data in (DQ0–DQ15)
Write
Active
L
L
X
H
L
Data in (DQ0–DQ7);
DQ8–DQ15 in High Z
Write
Active
L
L
X
L
H
Data in (DQ8–DQ15);
DQ0–DQ7 in High Z
Write
Active
Notes
52. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
53. BHE and BLE are applicable for × 16 configuration only.
Document #: 001-07103 Rev. *U
Page 25 of 35
[+] Feedback
CY14B104K, CY14B104M
Ordering Information
Speed
(ns)
25
45
Ordering Code
CY14B104K-ZS25XIT
Package Diagram
51-85087
Package Type
44-pin TSOP II
CY14B104K-ZS25XI
51-85187
44-pin TSOP II
CY14B104M-ZSP25XIT
51-85160
54-pin TSOP II
CY14B104M-ZSP25XI
51-85160
54-pin TSOP II
CY14B104K-ZS45XIT
51-85087
44-pin TSOP II
CY14B104K-ZS45XI
51-85187
44-pin TSOP II
CY14B104M-ZSP45XIT
51-85160
54-pin TSOP II
CY14B104M-ZSP45XI
51-85160
54-pin TSOP II
Operating Range
Industrial
All the above parts are Pb-free.
Ordering Code Definitions
CY14 B 104 K - ZSP 25 X I T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
I - Industrial (–40 to 85 °C)
Pb-free
Package:
ZSP - 44-pin TSOP II
ZSP - 54-pin TSOP II
Speed:
25 - 25 ns
45 - 45 ns
Data Bus:
K - × 8 + RTC
M - × 16 + RTC
Density:
104 - 4 Mb
Voltage:
B - 3.0 V
14 - nvSRAM
Cypress
Document #: 001-07103 Rev. *U
Page 26 of 35
[+] Feedback
CY14B104K, CY14B104M
Package Diagrams
Figure 17. 44-pin TSOP II, 51-85087
51-85087 *C
Document #: 001-07103 Rev. *U
Page 27 of 35
[+] Feedback
CY14B104K, CY14B104M
Package Diagrams (continued)
Figure 18. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm), 51-85160
51-85160 *A
Document #: 001-07103 Rev. *U
Page 28 of 35
[+] Feedback
CY14B104K, CY14B104M
Document Conventions
Acronyms
Acronym
Description
Units of Measure
BCD
binary coded decimal
BHE
byte high enable
°C
degree Celsius
BLE
byte low enable
F
Farads
CE
CMOS
chip enable
Hz
Hertz
complementary metal oxide semiconductor
kHz
kilo Hertz
EIA
electronic industries alliance
k
kilo ohms
HSB
I/O
hardware store busy
MHz
Mega Hertz
input/output
A
micro Amperes
nvSRAM
non-volatile static random access memory
mA
milli Amperes
OE
RoHS
output enable
F
micro Farads
restriction of hazardous substances
s
micro seconds
RTC
real time clock
ms
milli seconds
RWI
read and write inhibited
ns
nano seconds
SRAM
static random access memory

ohms
TSOP
thin small outline package
%
percent
WE
write enable
pF
pico Farads
ppm
parts per million
V
Volts
W
Watts
Document #: 001-07103 Rev. *U
Symbol
Unit of Measure
Page 29 of 35
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CY14B104K, CY14B104M
Document History Page
Document Title: CY14B104K/CY14B104M, 4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Orig. of
Submission
Rev.
ECN No.
Description of Change
Change
Date
**
431039
TUP
See ECN
New Data Sheet
*A
489096
TUP
See ECN
Removed 48 SSOP Package
Added 44 TSOPII and 54 TSOPII Packages
Updated Part Numbering Nomenclature and Ordering Information
Added Soft Sequence Processing Time Waveform
Added RTC Characteristics Table
Added RTC Recommended Component Configuration
*B
499597
PCI
See ECN
Removed 35ns speed bin
Added 55ns speed bin. Updated AC table for the same
Changed “Unlimited” read/write to “infinite” read/write
Features section: Changed typical ICC at 200-ns cycle time to 8 mA
Changed STORE cycles from 500K to 200K cycles.
Shaded Commercial grade in operating range table.
Modified Icc/Isb specs.
Changed VCAP value in DC table
Added 44 TSOP II in Thermal Resistance table
Modified part nomenclature table. Changes reflected in the ordering information table.
*C
517793
TUP
See ECN
Removed 55ns speed bin
Changed pinout for 44TSOPII and 54TSOPII packages
Changed ISB to 1mA
Changed ICC4 to 3mA
Changed VCAP min to 35F
Changed VIH max to VCC + 0.5V
Changed tSTORE to 15ns
Changed tPWE to 10ns
Changed tSCE to 15ns
Changed tSD to 5ns
Changed tAW to 10ns
Removed tHLBL
Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW
Removed min. specification for Vswitch
Changed tGLAX to 1ns
Added tDELAY max. of 70us
Changed tSS specification from 70us min. to 70us max.
*D
825240
UHA
See ECN
Changed the data sheet from Advance information to Preliminary
Changed tDBE to 10ns in 15ns part
Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns
Changed tBW in 15ns part to 15ns and in 25ns part to 20ns
Changed tGLAX to tGHAX
Changed the value of ICC3 to 25mA
Changed the value of tAW in 15ns part to 15ns
*E
914280
UHA
See ECN
Changed the figure-14 title from 54-Pb to 54 Pin
Included all the information for 45ns part in this data sheet
Document #: 001-07103 Rev. *U
Page 30 of 35
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CY14B104K, CY14B104M
Document History Page (continued)
Document Title: CY14B104K/CY14B104M, 4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Orig. of
Submission
Rev.
ECN No.
Description of Change
Change
Date
*F
1890926 vsutmp8 /
See ECN
Added Footnote 1, 2 and 3.
AESA
Updated Logic Block diagram
Updated Pin definition Table
Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II
(x8) package.
Corrected typo in VIL min spec
Changed the value of ICC3 from 25mA to 13mA
Changed ISB value from 1mA to 2mA
Updated ordering information table
Rearranging of Footnotes.
Changed Package diagrams title.
The pins X1 and X2 interchanged in 44TSOP II(x8) and 54TSOP II(x16) pinout
diagram.
*G
2267286
GVCH /
See ECN
Rearranging of “Features”
PYRS
Added BHE and BLE Information in Pin Definitions Table
Updated Figure 2 (Autostore mode)
Updated footnote 6
RTC Register Map:Register 0x1FFF6:Changed D4 from ABE to 0
Register Map Detail:0x1FFF6:Changed D4 from ABE to 0 and removed ABE
information
Changed ICC2 & ICC4 from 3mA to 6mA
Changed ICC3 from 13mA to 15mA
Changed ISB from 2mA to 3mA
Added input leakage current (IIX) for HSB in DC Electrical Characteristics table
Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF
max value
Corrected typo in tDBE value from 22ns to 20ns for 45ns part
Corrected typo in tHZBE value from 22ns to 15ns for 45ns part
Corrected typo in tAW value from 15ns to 10ns for 15ns part
Changed Vrtccap max from 2.7V to 3.6V
Changed tRECALL from 100 to 200us
Added footnote 10, 29
Reframed footnote 18, 25
Added footnote 18 to figure 8 (SRAM WRITE Cycle #1)
Added footnote 18, 26 and 27 to figure 9 (SRAM WRITE Cycle #2)
*H
2483627
GVCH /
See ECN
Removed 8 mA typical ICC at 200 ns cycle time in Feature section
PYRS
Referenced footnote 9 to ICC3 in DC Characteristics table
Changed ICC3 from 15 mA to 35 mA
Changed Vcap minimum value from 54 uF to 61 uF
Changed tAVAV to tRC
Changed VRTCcap minimum value from 1.2V to 1.5V
Figure 12:Changed tSA to tAS and tSCE to tCW
*I
2519319
GVCH /
06/20/08
Added 20 ns access speed in “Features”
PYRS
Added ICC1 for tRC=20 ns for both industrial and Commercial temperature
Grade
Updated Thermal resistance values for 44-TSOP II and 54-TSOP II packages
Added AC Switching Characteristics specs for 20 ns access speed
Added Software controlled STORE/RECALL cycle specs for 20 ns access
speed
Updated ordering information and Part numbering nomenclature
Document #: 001-07103 Rev. *U
Page 31 of 35
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CY14B104K, CY14B104M
Document History Page (continued)
Document Title: CY14B104K/CY14B104M, 4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Orig. of
Submission
Rev.
ECN No.
Description of Change
Change
Date
*J
2600941
GVCH /
11/04/08
Removed 15 ns access speed from “Features”
PYRS
Changed part number from CY14B104K/CY14B104M to
CY14B104KA/CY14B104MA
Updated Logic block diagram
Updated footnote 1
Added footnote 2
Pin definition: Updated WE, HSB and NC pin description
Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description
Page 4: Updated Hardware store operation and Hardware RECALL (power-up) description
Footnote 1 and 8 referenced for Mode selection Table
Updated footnote 6
Page 6: updated Data protection description
Page 6: Updated Starting and stopping the oscillator description
Page 7: Updated Calibrating the clock description
Page 7: Updated Alarm description
Page 8: Added Flags register
Added footnote 10 and 11
Updated Figure 4: Removed RF register and Changed C2 value from 56pF to
12pF
Updated Register Map Table 3
Updated Register map detail Table 4
Maximum Ratings: Added Max. Accumulated storage time
Changed Output short circuit current parameter name to DC output current
Changed ICC2 from 6mA to 10mA
Changed ICC4 from 6mA to 5mA
Changed ISB from 3mA to 5mA
Updated ICC1, ICC3, ISB and IOZ Test conditions
Changed VCAP voltage max value from 82uF to 180uF
Updated footnote 12 and 13
Added footnote 14
Added Data retention and Endurance Table
Updated Input Rise and Fall time in AC test Conditions
Changed tOCS value for minimum temperature from 10 to 2 sec
updated tOCS value for room temperature from 5 to 1sec
Referenced footnote 20 to tOHA parameter
Updated All switching waveforms
Updated footnote 20
Added Figure 11 (SRAM WRITE CYCLE:BHE and BLE controlled)
Updated tDELAY value
Added VHDIS, tHHHD and tLZHSB parameters
Updated footnote 27
Added footnote 29
Software controlled STORE/RECALL Table: Changed tAS to tSA
Changed tGHAX to tHA
Changed tHA value from 1ns to 1ns
Added tDHSB parameter
Changed tHLHX to tPHSB
Updated tSS from 70us to 100us
Added truth table for SRAM operations
Updated ordering information and part numbering nomenclature
Document #: 001-07103 Rev. *U
Page 32 of 35
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CY14B104K, CY14B104M
Document History Page (continued)
Document Title: CY14B104K/CY14B104M, 4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Orig. of
Submission
Rev.
ECN No.
Description of Change
Change
Date
*K
2653928
GVCH /
02/04/09
Changed Part number from CY14B104KA/CY14B104MA to
PYRS
CY14B104K/CY14B104M
Updated Real Time Clock operation description
Added factory default values to register map table 3
Added footnote 9
Updated Flag register description in Table 4
Updated C1, C2 values to 21pF, 21pF respectively
Changed IBAK value from 350 nA to 450 nA at hot temperature
Changed VRTCcap typical value from 2.4V to 3.0V
Referenced Note 15 to parameters tLZCE, tHZCE, tLZOE, tHZOE, tLZBE, tLZWE,
tHZWEand tHZBE
Added footnote 22
Updated Figure 13
*L
2710240
GVCH /
05/22/09
Moved data sheet status from Preliminary to Final
PYRS
Changed pin names X1, X2 to Xout, Xin respectively.
Updated AutoStore operation
Updated C1, C2 values to 12pF, 69pF from 21pF, 21pF respectively
Updated ISB test condition
Updated footnote 11
Updated IBAK and VRTCcap parameter values
Added RBKCHG parameter to RTC characteristics table
Added footnote 15
Referenced footnote 13 to VCCRISE, tHHHD and tLZHSB parameters
Updated VHDIS parameter description
*M
2738586
GVCH
07/15/09
Page 4: Updated Hardware STORE (HSB) operation description
page 4: Updated Software STORE description
Added best practices
Updated tDELAY parameter description
Updated footnote 25 and added footnote 32
Referenced footnote 32 to Figure 13 and Figure 14
*N
2758397
GVCH /
09/01/09
Removed commercial temperature related specifications
AESA
Removed 20 ns access speed related specs
Changed VRTCbat max value from 3.3V to 3.6V
Changed RBKCHG min value from 450to 350
Updated footnote 15
*O
2826364
GVCH /
12/11/09
Changed STORE cycles to QuantumTrap from 200K to 1 Million
PYRS
Updated IBAK RTC backup current spec unit from nA to A
*P
2858300
GVCH
01/19/2010 Added Contents.
*Q
2923475
GVCH /
04/27/2010 Table 1: Added more clarity on HSB pin operation
Hardware STORE (HSB) Operation: Added more clarity on HSB pin operation
AESA
Table 1: Added more clarity on BHE/BLE pin operation
Updated HSB pin operation in Figure 12
Updated footnote 27
Updated Package Diagrams
*R
3132368
GVCH
01/10/2011 Updated Setting the Clock description
Added footnote 12
Updated W bit description in Register Map Detail table
Updated Best Practices
Updated input capacitance for BHE and BLE pin
Updated input and output capacitance for HSB pin
Added tRTCp parameter to RTC Characteristics table
Figure 12: Typo error fixed
Added Acronyms table and Document Conventions table
*S
3150253
GVCH
01/21/2011 No technical updates
Document #: 001-07103 Rev. *U
Page 33 of 35
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CY14B104K, CY14B104M
Document History Page (continued)
Document Title: CY14B104K/CY14B104M, 4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Orig. of
Submission
Rev.
ECN No.
Description of Change
Change
Date
*T
3208661
GVCH
03/29/2011 Updated thermal resistance values for all packages
*U
3305495
GVCH
07/07/2011 Updated DC Electrical Characteristics (Added Note 15 and referred the same
note in VCAP parameter).
Updated AC Switching Characteristics (Added Note 20 and referred the same
note in Parameters).
Document #: 001-07103 Rev. *U
Page 34 of 35
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CY14B104K, CY14B104M
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-07103 Rev. *U
Revised July 12, 2011
Page 35 of 35
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