Revised January 1999 CD4007C Dual Complementary Pair Plus Inverter General Description The CD4007C consists of three complementary pairs of Nand P-channel enhancement mode MOS transistors suitable for series/shunt applications. All inputs are protected from static discharge by diode clamps to VDD and VSS. For proper operation the voltages at all pins must be constrained to be between VSS − 0.3V and VDD + 0.3V at all times. Features ■ Wide supply voltage range: ■ High noise immunity: 3.0V to 15V 0.45 VCC (typ.) Ordering Code: Order Number Package Number Package Description CD4007CM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4007CN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS–001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Note: All P-channel substrates are connected to VDD and all N-channel substrates are connected to VSS. Top View © 1999 Fairchild Semiconductor Corporation DS005943.prf www.fairchildsemi.com CD4007C Dual Complementary Pair Plus Inverter October 1987 CD4007C Absolute Maximum Ratings(Note 1) VSS −0.3V to VDD +0.3V Voltage at Any Pin Lead Temperature −65°C to +150°C Storage Temperature Range (Soldering, 10 seconds) Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW VSS +3.0V to VSS +15V Operating VDD Range −40°C to +85°C Operating Temperature Range 260°C Note 1: This device should not be connected to circuits with the power on because high transient voltages may cause permanent damage. DC Electrical Characteristics Limits Symbol Parameter −40°C Conditions Min IL PD VOL VOH VNL VNH IDN IDP II Typ +25°C Max Min +85°C Typ Max Min Typ Units Max Quiescent Device VDD = 5.0V 0.5 0.005 0.05 15 Current VDD = 10V 1.0 0.005 1.0 30 µA Quiescent Device VDD = 5.0V 2.5 0.025 2.5 75 µW Dissipation Package VDD = 10V 10 0.05 10 300 µW Output Voltage VDD = 5.0V 0.05 0 0.01 0.05 V LOW Level VDD = 10V 0.05 0 0.01 0.05 Output Voltage VDD = 5.0V 4.95 HIGH Level VDD = 10V 9.95 Noise Immunity VDD = 5.0V, VO = 3.6V 1.5 2.25 1.5 1.4 (All inputs) VDD = 10V, VO = 7.2V 3.0 4.5 3.0 2.9 Noise Immunity VDD = 5.0V, VO = 0.95V 4.95 9.95 5.0 µA V 4.95 10 V 9.95 3.6 3.5 2.25 V V V 3.5 V (All Inputs) VDD = 10V, VO = 2.9V 7.1 7.0 4.5 7.0 V Output Drive Current VDD = 5.0V, VO = 0.4V, VI = V DD 0.35 0.3 1.0 0.24 mA N-Channel VDD = 10V, VO = 0.5V, VI = VDD 1.2 1.0 2.5 0.8 mA Output Drive Current VDD = 5.0V, VO = 2.5V, VI = V SS −1.3 −1.1 −4.0 −0.9 mA P-Channel VDD = 10V, VO = 9.5V, VI = VSS −0.65 −0.55 −2.5 −0.45 mA Input Current 10 AC Electrical Characteristics pA (Note 2) TA = 25°C and CL = 15 pF and rise and fall times = 20 ns. Typical temperature coefficient for all values of VDD = 0.3%/°C Symbol Parameter Conditions Typ Max Units tPLH = tPHL Propagation Delay Time VDD = 5.0V 35 75 ns VDD = 10V 20 50 ns VDD = 5.0V 50 100 ns VDD = 10V 30 50 Any Input 5 tTLH = tTHL CI Transition Time Input Capacitance Note 2: AC Parameters are guaranteed by DC correlated testing. www.fairchildsemi.com 2 Min ns pF CD4007C AC Test Circuits Switching Time Waveforms 3 www.fairchildsemi.com CD4007C Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A www.fairchildsemi.com 4 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. CD4007C Dual Complementary Pair Plus Inverter Physical Dimensions inches (millimeters) unless otherwise noted (Continued)