Rohm BD9153MUV Output 1.5a or less high efficiency step-down switching regulator with built-in power mosfet Datasheet

Single-chip Type with Built-in FET Switching Regulator Series
Output 1.5A or Less High Efficiency
Step-down Switching Regulator
with Built-in Power MOSFET
BD9153MUV
No.09027EAT40
●Description
ROHM’s high efficiency dual step-down switching regulators and Linear Regulator Controller, BD9153MUV is a power supply
designed to produce a low voltage including 3.3,0.8 volts from 5.5/4.5 volts power supply line. Offers high efficiency with our
original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster
transient response to sudden change in load.
●Features
1) Offers fast transient response with current mode PWM control system.
2) Offers highly efficiency for all load range with synchronous rectifier (Pch/Nch FET) and SLLMTM (Simple Light Load Mode)
3) Incorporates Nch FET controller for Linear Regulator.
4) Incorporates reset function with 50ms counter.
5) Incorporates soft-start fanction, thermal protection and ULVO functions.
6) Incorporates short-current protection circuit with time delay function.
7) Incorporates shutdown function Icc=0µA(Typ.)
8) Employs small surface mount package : VQFN024V4040
●Applications
Power supply for LSI including DSP, Micro computer and ASIC
●Absolute Maximum Rating (Ta=25℃)
Parameter
Symbol
Vcc,PVcc Voltage
VCC,PVCC
FB1,FB2,FB3,VS Voltage
VFB1, VFB2, VFB3, VVS
SW1,SW2,ITH1,ITH2 Voltage
VSW1, VSW2, VITH1, V ITH2
EN,RST,DET,GATE Voltage
V EN, V RST, V DET, V GATE
Pd1
Pd2
Power Dissipation
Pd3
Pd4
Operating Temperature Range
Topr
Storage Temperature Range
Tstg
Maximum Junction Temperature
Tjmax
＊1
＊2
＊3
＊4
＊5
Unit
V
V
V
V
W
W
W
W
℃
℃
℃
Pd should not be exceeded.
IC only
1-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2
4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2 , in 1,4 layer, 5505mm2 in 2,3 layer
4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 5505mm2, in each layers
●Operating Conditions (Ta=-40～+85℃)
Parameter
Vcc Voltage
EN Voltage
Output Voltage range
SW Average Output Current
＊6
Limit
-0.3～+7*1
-0.3～+7
-0.3～+7
-0.3～+7
2
0.34*
0.69 *3
2.20 *4
3.56*5
-40～+85
-55～+150
+150
Symbol
VCC
VEN
VOUT1
VOUT2
VOUT3
ISW1
ISW2
Min.
4.5
0
1.8
0.8
0.8
-
Typ.
5.0
-
Max.
5.5
5.5
3.3
2.5
2.5
1.5*6
1.5*6
Unit
V
V
V
V
V
A
A
Pd should not be exceeded.
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1/18
2009.08 - Rev.A
Technical Note
BD9153MUV
●Electrical Characteristics
◎(Ta=25℃ VCC=5V, EN=VCC ,unless otherwise specified.)
Parameter
Standby Current
Bias Current
EN Low Voltage
EN High Voltage
EN Input Current
Oscillation Frequency
Pch FET ON Resistance
Nch FET ON Resistance
FB Reference Voltage
ITH sink curren1
ITH source current 1
ITH sink curren2
ITH source current 2
UVLO Threshold Voltage1
UVLO Release Voltage1
UVLO Threshold Voltage2
UVLO Release Voltage2
VS Discharge Resistance
Soft Start Time
Timer Latch Time
Output Short circuit
Threshold Voltage
RST Release Voltage
RST threshold Voltage
RST Delay
RST ON Reststance
GATE Source Current
GATE Sink Current
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Symbol
ISTB
ICC
VENL
VENH
IEN
FOSC
RONP1
RONP2
RONN1
RONN2
VFB1,2
VFB3
VFB3
ITHSI1
ITHSO1
ITHSI2
ITHSO2
VUVLOL1
VUVLOH1
VUVLOL2
VUVLOH2
RVS
TSS
TLATCH
VSCP1
VSCP2
VSCP3
VRST1
VRST2
TRST
RONRST
IGSO
IGSI
Min.
2
0.8
0.788
0.784
0.780
10
10
10
10
3.6
3.65
2.4
2.425
0.4
1.0
0.691
0.668
40
0.5
1.0
2/18
Limit
Typ.
0
600
GND
Vcc
2
1.0
0.17
0.17
0.13
0.13
0.8
0.8
0.8
18
18
18
18
3.8
3.9
2.5
2.55
40
0.8
2.0
0.4
0.4
0.4
0.720
0.696
50
140
1.5
5.0
Max.
10
1000
0.8
10
1.2
0.3
0.3
0.2
0.2
0.812
0.816
0.820
4.0
4.2
2.6
2.7
80
1.6
4.0
0.56
0.56
0.56
0.749
0.724
60
280
-
Unit
µA
µA
V
V
µA
MHz
Ω
Ω
Ω
Ω
V
V
V
µA
µA
µA
µA
V
V
V
V
Ω
ms
ms
V
V
V
V
V
ms
Ω
mA
mA
Condition
EN=0V
Standby Mode
Active Mode
EN=2V
Vcc=5V
Vcc=5V
Vcc=5V
Vcc=5V
±1.5%
±2.0%(Ta=25℃)
±2.5%(Ta=-40~+85℃)
VFB1=1.0V
VFB1=0.6V
VFB2=1.0V
VFB2=0.6V
Vcc=5→0V
Vcc=0→5V
Vcc=5→0V
Vcc=0→5V
Vcc=5V
SCP/TSD ON
FB1=0.8→0V
FB2=0.8→0V
FB3=0.8→0V
DET=0V→0.8V
DET=0.8V→0V
VFB3=0.6V , VGATE=2.5V
VFB3=1.0V , VGATE=2.5V
2009.08 - Rev.A
Technical Note
BD9153MUV
●Block Diagram, Application Circuit
4.0±0.1
PVCC
OUT1
Current
Comp
4.0±0.1
FB1
R
Gm Amp
D9153
Q
Sense/
Slope1
EN
SW1
Protect
S
Lot No.
Soft
Start1
Driver
1.0Max.
Logic
0.02 +0.03
-0.02
(0.22)
CLK1
VREF
24
12
13
18
0.75
0.5
UVLO2
CLK2
PVCC
SCP2
7
19
UVLO1
SCP/
TSD
OSC
6
2.4±0.1
1
PGND1
SCP1
S
C0.2 2.4±0.1
Current
Current
Comp
OUT2
R
Gm Amp
FB2
Sense/
Q
Protect
S
Soft
Start2
OUT2
SW2
+
Slope2
0.25 +0.05
-0.04
OUT1
+
ITH1
0.08 S
0.4±0.1
Current
Driver
CLK2
Logic
PGND2
ITH2
(Unit : mm)
Soft
Start1
Fig.1 BD9153MUV TOP View
OUT1
GATE
DET
FB3
SCP3
OUT3
VS
RST
SCP/TSD
UVLO1
ITH1
Timer
FB1
AGND
PGND1
Fig.2 BD9153MUV Block Diagram
●Pin No. & function table
Pin No. Pin name
Function
Pin No.
Pin name
1
PGND2
Nch FET Source pin (2CH)
13
GATE
2
PVCC2
Pch FET Source pin (2CH)
14
FB3
Function
Gate drive pin
Output Voltage3 detector pin
3
PVCC2
Pch FET Source pin (2CH)
15
AVCC
4
PVCC1
Pch FET Source pin (1CH)
16
DET
Voltage detector pin
5
PVCC1
Pch FET Source pin (1CH)
17
RST
RST signal output pin
6
PGND1
Nch FET Source pin (1CH)
18
AGND
7
PGND1
Nch FET Source pin (1CH)
19
ITH2
8
SW1
SW pin (1ch)
20
FB2
Output Voltage2 detector pin
9
SW1
SW pin (1ch)
21
EN
Enable pin (High Active)
10
VS
Discharge function pin
22
SW2
11
FB1
Output Voltage1 detector pin
23
SW2
12
ITH1
GmAmp1output pin
24
PGND2
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3/18
AVCC power supply input pin
Ground
GmAmp2 output pin
SW pin (2ch)
SW pin (2ch)
Nch FET Source pin (2ch)
2009.08 - Rev.A
Technical Note
BD9153MUV
●Characteristics data【BD9153MUV】
3.0
【VOUT1=3.3V】
2.5
2.0
【VOUT2=1.2V】
1.5
1.0
0.5
【VOUT1=3.3V】
3.5
3.0
2.5
2.0
1.5
VCC=5V
【VOUT2=1.2V】
Ta=25℃
Io=0A
1.0
0.5
0.0
0.0
0
1
2
3
4
INPUT VOLTAGE:VCC[V]
1
Fig.3 VCC – VOUT1,VOUT2
VCC=5V
Io=0A
-20
0
20
40
60
TEMPERATURE:Ta[℃]
1.0
0.5
90
80
1.20
1.18
VCC=5V
Io=0A
70
60
【VOUT1=3.3V】
50
40
【VOUT2=1.2V】
30
VCC=5V
Ta=25℃
20
10
-40
-20
0
20
40
60
TEMPERATURE:Ta[℃]
0
80
10
100
1000
OUTPUT CURRENT:IOUT[mA]
Fig. 7 Ta-VOUT2
250
225
0.6
0.4
VCC=5V
1.1
ON RESISTANCE:RON[mΩ]
FREQUENCY:FOSC[MHz]
0.8
10000
Fig.8 Efficiency
1.2
1.0
4
Fig.5 IOUT - VOUT
【VOUT2=1.2V設定】
【VOUT2=1.2V
】
Fig. 6 Ta-VOUT1
0.2
1
2
3
OUTPUT CURRENT:IOUT [A]
100
1.23
80
1.2
VCC=5V
Ta=25℃
【VOUT2=1.2V】
0
1.15
-40
1.5
5
EFFICIENCY:η[%]
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
3.25
3.20
FREQUENCY:FOSC[MHz]
2
3
4
EN VOLTAGE:VEN[V]
1.25
3.30
2.0
Fig.4 VEN - VOUT
3.40
3.35
2.5
0.0
0
5
【VOUT1=3.3V】
【VOUT1=3.3V】
3.0
OUTPUT VOLTAGE:VOUT[V]
Ta=25℃
Io=1.5A
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
3.5
4.0
3.5
1
0.9
Ta=25℃
VCC=5V
200
PMOS
175
150
125
NMOS
100
75
50
25
0.8
0.0
-40
-20
0
20
40
60
0
4.5
80
TEMPERATURE:Ta[℃]
4.75
5
5.25
INPUT VOLTAGE:VCC[V]
Fig.9 Ta- Fosc
5.5
-40
Fig.10 VCC-Fosc
0
20
40
60
80
TEMPERATURE:Ta[℃]
100
Fig.11 Ta – RONN, RONP
600
2.0
CIRCUIT CURRENT:ICC[μA]
1.8
1.6
EN VOLTAGE:VEN[V]
-20
1.4
1.2
1.0
0.8
0.6
VCC=5V
0.4
VCC=5V,Ta=25℃
500
EN
400
VOUT1
300
VOUT1
200
VOUT2
VCC=5V
100
0.2
VOUT3
0
0.0
-40
-20
0
20
40
60
TEMPERATURE:Ta[℃]
Fig.12 Ta－EN
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80
EN1=E2
-40
-20
0
20
40
60
VOUT2
VCC=5.0V
Ta=25℃
80
TEMPERATURE:Ta[℃]
Fig.13 Ta－Icc
4/18
Fig.14 Soft start wave form
(Io1=0mA, Io2=0mA, Io3=0mA)
2009.08 - Rev.A
Technical Note
BD9153MUV
EN
SW1
SW1
VOUT1
VOUT2
VOUT1
VCC=5.0V
Ta=25℃
VOUT3
VOUT1
VCC=5.0V,Vout1=3.3V
Ta=25℃
VCC=5.0V,Vout1=3.3V
Ta=25℃
Fig.16 SW1 wave form
(Io1=0mA)
Fig.15 Soft start wave form
(Io1=1.5A, Io2=1.5A, Io3=1.0A)
Fig.17 SW1 wave form
(Io1=1.5A)
SW2
SW2
VOUT1
VOUT2
VOUT2
IOUT1
VCC=5.0V,Vout2=1.2V
Ta=25℃
VCC=5.0V,Vout2=1.2V
Ta=25℃
VCC=5.0V,Vout1=3.3V
Ta=25℃
Fig.19 SW2 wave form
(Io2=1.5A)
Fig.18 SW2 wave form
(Io2=0mA)
Fig.20 VOUT1 transient responce
(Io10.5A→1.5A / 10usec)
VOUT1
VOUT2
VOUT2
IOUT1
IOUT2
IOUT2
VCC=5.0V,Vout1=3.3V
Ta=25℃
VCC=5.0V,Vout2=1.2V
Ta=25℃
Fig.21 VOUT1 transient responce
(Io11.5A→0.5A/ 10usec)
Fig.22 VOUT2 transient responce
(Io20.5A→1.5A/ 10usec)
VOUT3
VOUT3
IOUT3
IOUT3
VCC=5.0V,Vout3=2.5V
Ta=25℃
Fig.24 VOUT3 transient responce
(Io30.5A→1A/ 10usec)
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VCC=5.0V,Vout2=1.2V
Ta=25℃
Fig.23 VOUT2 transient responce
(Io21.5A→0.5A/ 10usec)
VCC=5.0V,Vout3=2.5V
Ta=25℃
Fig.25 VOUT3 transient responce
(Io3500mA→1A/ 10usec)
5/18
2009.08 - Rev.A
Technical Note
BD9153MUV
●Information on advantages
Advantage 1：Offers fast transient response with current mode control system.
BD9153MUV (Load response IO=1.5A→0.5A / usec)
BD9153MUV (Load response IO=0.5A→1.5A / usec)
VOUT1
VOUT1
Io1
Io1
Fig.26
Advantage 2： Offers high efficiency for all load range.
・For lighter load:
Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching
dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance
dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
・For heavier load:
Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor.
Achieves efficiency improvement for heavier load.
100
Efficiency η[%]
ON resistance of Highside MOS FET : 170mΩ(Typ.)
ON resistance of Lowside MOS FET : 130mΩ(Typ.)
SLLMTM
②
50
①
PWM
①inprovement by SLLM system
②improvement by synchronous rectifier
0
0.001
0.01
0.1
Output current Io[A]
1
Offers high efficiency for all load range with the improvements mentioned above.
Fig.27 Efficiency
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6/18
2009.08 - Rev.A
Technical Note
BD9153MUV
Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated.
・Output capacitor Co required for current mode control: 22μF ceramic capacitor
・Inductance L required for the operating frequency of 1 MHz: 2.2μH inductor
・Incorporates FET + Boot strap diode
Reduces a mounting area required.
R5
Cfb
R6
R9
CITH2
RITH2
L2
R4
CO2
AGND
ITH2
RST
COUT2
COUT1
M1
DET
AVCC
FB3 GATE
ITH1
FB2
FB1
EN
VS
SW2
SW
1
SW2
SW1
CIN1
50mm
R2
RITH2
RITH1
R1
L1
CO1
PGND1
R4
R3
R8
CITH1
R9
R2
R1
PGND2 PVCC2 PVCC2 PVCC1 PVCC1 PGND1
R5 C1 R6
COUT3
CIN2
CIN2
RITH1 CITH1
M1
PGND2
R3
50mm
CO3
R7
CIN1
R8
R7
Fig.28
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7/18
2009.08 - Rev.A
Technical Note
BD9153MUV
●Operation
BD9153MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing
current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load,
while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and
its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power
dissipation of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a highside MOS FET (while a lowside MOS
FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals,
a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and
issues a RESET signal if both input signals are identical to each other, and turns OFF the highside MOS FET (while a
lowside MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation.
TM
・SLLM (Simple Light Load Mode) control
When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is
designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without
voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa.
Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp,
it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned
OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching
dissipation and improves the efficiency.
SENSE
Current
Comp
RESET
VOUT
Level
Shift
R Q
FB
SET
Gm Amp.
ITH
S
IL
Driver
Logic
VOUT
SW
Load
OSC
Fig.29 Diagram of current mode PWM control
SENSE
PVCC
SENSE
PVCC
Current
Comp
SET
FB
GND
Current
Comp
SET
FB
GND
GND
RESET
GND
RESET
GND
SW
IL
SW
GND
IL(AVE)
IL
0A
VOUT(AVE)
VOUT
VOUT
VOUT(AVE)
Not switching
Fig.31 SLLM
Fig.30 PWM switching timing chart
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TM
switching timing chart
2009.08 - Rev.A
Technical Note
BD9153MUV
●Description of operations
・Soft-start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during
startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0µA (Typ.).
・RST function
If DET voltage over 0.72V(Typ.), RST terminal shifted to “High” after 50ms(Typ.) delay. And the hysteresis width of 24mV
(Typ.) is provided to prevent output chattering.
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of BU9153MUV is supplied. And the hysteresis
width of 100mV (UVLO1 Typ.) ,50mV(UVLO2 Typ.) is provided to prevent output chattering. Each the outputs have UVLO.
It is possible to set output sequence easy.
4.5V detect (RST Release voltage ×6.25)
3.9V detect (UVLO Release voltage 1)
2.55V detect (UVLO Release voltage2)
4.35V (RST Threshold Voltage ×6.25)
3.8V (UVLO Threshold Voltage 1)
VCC＝EN
2.5V (UVLO Threshold Voltage 2)
3.3V Output (DC/DC 1)
2.5V Output (LDO)
1.2V Output (DC/DC 2)
VS discharge ON
RST
Output
Natural discharge
0.8ms Soft-start
50ms
(RST Delay)
RST
Fig.32 Soft-start, Shutdown, RST Delay, UVLO, timing chart
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9/18
2009.08 - Rev.A
Technical Note
BD9153MUV
・Short-current protection circuit with time delay function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for
the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking
UVLO.
EN
Output Short circuit
Threshold Voltage
OUT1
Output OFF
Latch
OUT2
OUT3
IL Limit
Io1
Io2
Io3
t2<TLATCH
t1<TLATCH
Standby
mode
t3=TLATCH
Standby
mode
Operating mode
Timer latch
EN
Operating mode
EN
Fig.33 Short-current protection circuit with time delay timing chart
●Switching regulator efficiency
Efficiency ŋ may be expressed by the equation shown below:
η=
VOUT×IOUT
Vin×Iin
×100[%]=
POUT
Pin
×100[%]=
POUT
POUT+PDα
×100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
2
1) ON resistance dissipation of inductor and FET：PD(I R)
2) Gate charge/discharge dissipation：PD(Gate)
3) Switching dissipation：PD(SW)
4) ESR dissipation of capacitor：PD(ESR)
5) Operating current dissipation of IC：PD(IC)
2
2
1)PD(I R)=IOUT ×(RCOIL+RON)
(RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET)
3)PD(SW)=
Vin2×CRSS×IOUT×f
IDRIVE
(CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.)
2
4)PD(ESR)=IRMS ×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)
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10/18
2009.08 - Rev.A
Technical Note
BD9153MUV
●Consideration on permissible dissipation and heat generation
As BU9153MUV functions with high efficiency without significant heat generation in most applications, no special
consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including
lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat
generation must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
4.0
2
①3.56W
Power dissipation : Pd [W]
3.0
① 4 layers (copper foil area : 5505mm )
(Copper foil in each layers)
θj-a=35.1℃/W
2
② 4 layers (copper foil area : 10.29mm )
(Copper foil in 2nd and 3rd layers)
θj-a=56.8℃/W
2
③ 1 layer (Copper foil area : 0mm )
θj-a=181.2℃/W
④IC only
θj-a=367.6℃/W
P=IOUT2×RON
RON=D×RONP+(1-D)RONN
D：ON duty (=VOUT/VCC)
RONH：ON resistance of Highside MOS FET
RONL：ON resistance of Lowside MOS FET
IOUT：Output current
②2.2W
2.0
1.0
③0.69W
④0.34W
0
0
25
SW1
75
100 105 125
Ambient temperature :Ta [℃]
150
Fig.34 Thermal derating curve
(VQFN024V4040)
(Example) VCC=5V, VOUT1=3.3V, VOUT2=1.2V, RONH=170mΩ, RONL=130mΩ
IOUT=1.5A, for example,
D1=VOUT1/VCC=3.3/5=0.66
D2=VOUT2/VCC=1.2/5=0.24
RON1=0.66×0.170+(1-0.66)×0.130
=0.1122+0.0442
=0.1564[Ω]
RON2=0.24×0.170+(1-0.24)×0.130
=0.0408+0.0988
=0.1397[Ω]
2
2
P=1.5 ×0.1564+1.5 ×0.1397=0.666[W]
As RONH is greater than RONL in BU9153MUV, the dissipation increases as the ON duty becomes greater. With the
consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
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11/18
2009.08 - Rev.A
Technical Note
BD9153MUV
●Selection of components externally connected
1. Selection of inductor (L)
The inductance significantly depends on output ripple current.
As seen in the equation (1), the ripple current decreases as the
inductor and/or switching frequency increases.
IL
ΔIL
VCC
ΔIL=
IL
(VCC-VOUT)×VOUT
L×VCC×f
[A]・・・(1)
Appropriate ripple current at output should be 20% more or less of
the maximum output current.
VOUT
L
ΔIL=0.2×IOUTmax. [A]・・・(2)
Co
L=
Fig.35 Output ripple current
(VCC-VOUT)×VOUT
ΔIL×VCC×f
[H]・・・(3)
(ΔIL: Output ripple current, and f: Switching frequency)
※Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency.
The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating.
If VCC=5.0V, VOUT=1.2V, f=1.0MHz, ΔIL=0.3×1.5A=0.45A, for example,(BD9153MUV)
L=
(5-1.2)×1.2
0.45×5×1.0M
=2.02μ → 2.2[μH]
※Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for
better efficiency.
2. Selection of output capacitor (CO)
VCC
Output capacitor should be selected with the consideration on the stability region
and the equivalent series resistance required to smooth ripple voltage.
VOUT
L
Output ripple voltage is determined by the equation (4)：
ESR
ΔVOUT=ΔIL×ESR [V]・・・(4)
Co
(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
Fig.36 Output capacitor
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※Rating of the capacitor should be determined allowing sufficient margin against
output voltage. A 22µF to 100μF ceramic capacitor is recommended.
Less ESR allows reduction in output ripple voltage.
12/18
2009.08 - Rev.A
Technical Note
BD9153MUV
3. Selection of input capacitor (Cin)
VCC
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage.
ripple current IRMS is given by the equation (5):
Cin
VOUT
L
Co
IRMS=IOUT×
√VOUT(VCC-VOUT)
VCC
The
[A]・・・(5)
< Worst case > IRMS(max.)
When Vcc=2×VOUT, IRMS =
IOUT
2
If VCC=5.0V, VOUT=1.8V, and IOUTmax.=1.5A, (BD9153MUV)
Fig.37 Input capacitor
IRMS=2×
√1.8(5.0-1.8)
5.0
= 0.48[ARMS]
A low ESR 22µF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.)
A
fp=
fp(Max.)
Gain
[dB]
0
fz(ESR)
IOUTMin.
Phase
[deg]
IOUTMax.
0
1
2π×RO×CO
1
2π×ESR×CO
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
fz(ESR)=
-90
fp(Min.)=
1
[Hz]←with lighter load
2π×ROMax.×CO
fp(Max.)=
1
2π×ROMin.×CO
Fig.38 Open loop gain characteristics
A
fz(Amp.)
Gain
[dB]
[Hz] ←with heavier load
Zero at power amplifier
Increasing capacitance of the output capacitor lowers
the pole frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the
capacitor ESR reduces to half.)
0
0
Phase
[deg]
-90
fz(Amp.)=
1
2π×RITH×CITH
Fig.39 Error amp phase compensation characteristics
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13/18
2009.08 - Rev.A
Technical Note
BD9153MUV
R5
Cfb
R6
CO3
R9
CITH2
RITH2
AGND
M1
RST
DET
AVCC
FB3
GATE
ITH2
ITH1
FB2
FB1
EN
VS
RITH1
CITH1
SW1
SW2
L2
R4
L1
SW2
CO2
SW1
PGND2
R3
CO1
R2
PGND1
PGND2
PVCC2
PVCC2
R1
PVCC1 PVCC1 PGND1
CIN2
CIN1
R8
R7
Fig.40 Typical application
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz(Amp.)= fp(Min.)
1
2π×RITH×CITH
=
1
2π×ROMax.×CO
5. Determination of VOUT1~3 output voltage
The output voltage VOUT1~3 is determined by the equation (6)~(8):
VOUT1=(R2/R1+1)×VFB1・・・(6) VFB1: Voltage at FB terminal (0.8V Typ.)
VOUT2=(R4/R3+1)×VFB2・・・(7) VFB2: Voltage at FB terminal (0.8V Typ.)
VOUT3=(R6/R5+1)×VFB3・・・(8) VFB3: Voltage at FB terminal (0.8V Typ.)
With R1~R6 adjusted, the output voltage may be determined as required.
L1
VOUT1
SW1
FB1
Cout1
R2
R1
Fig.41 Determination of output voltage
Use 1 kΩ～100 kΩ resistor for R1. If a resistor of the resistance higher than 100 kΩ is used, check the assembled set
carefully for ripple voltage etc.
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14/18
2009.08 - Rev.A
Technical Note
BD9153MUV
●BD9153MUV
Cautions on PC Board layout
Top Layer
Silk screen
Bottom Layer
Fig.42 Layout diagram
Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to
the pin PGND.
Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
①
②
※ VQFN024V4040 (BD9153MUV) has thermal PAD on the reverse of the package.
The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of PCB.
●Recommended components Lists on above application
Symbol
Value
Manufacturer
Coil
2.2µH
TDK
CIN1,CIN2
Ceramic capacitor
22µF
Murata
GRM32EB11A226KE20
Cout1,Cout2
Ceramic capacitor
Murata
GRM31CB30J226KE18
CITH1
Ceramic capacitor
VOUT1=3.3V
680pF
Murata
GRM18 Series
RITH1
Resistance
VOUT1=3.3V
39kΩ
Rohm
MCR03 Series
CITH2
Ceramic capacitor
VOUT2=1.2V
680pF
Murata
GRM18 Series
RITH2
Resistance
VOUT2=1.2V
12kΩ
Rohm
MCR03 Series
56pF
Murata
GRM18 Series
-
Rohm
RTF015N03
L1,2
Part
Cfb
Ceramic capacitor
M1
Nch MOS FET
22µF
Series
LTF5022-2R2N3R2
※The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit
characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to
accommodate variations between external devices and BU9153MUV when employing the depicted circuit with other
circuit constants modified. Both static and transient characteristics should be considered in establishing these margins.
When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and
PVCC pins, and a schottky barrier diode or snubber established between the SW and PGND pins.
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15/18
2009.08 - Rev.A
Technical Note
BD9153MUV
●I/O equivalence circuit
・EN pin
・SW1,SW2 pin
PVCC
PVCC
PVCC
EN
SW1,SW2
・FB1,FB2,FB3,DET pin
・ITH1,ITH2 pin
AVCC
FB1,FB2,FB3,DET
ITH1,ITH2
・RST, VS pin
・GATE pin
AVCC
RST,VS
GATE
Fig.43 I/O equivalence circuit
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16/18
2009.08 - Rev.A
Technical Note
BD9153MUV
●Notes for use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the
absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be
used thereafter for any operation originally intended.
5. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
6. Input to IC terminals
+
This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the
N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 44.
○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or
GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in
activation of parasitic elements.
Resistor
Transistor (NPN)
Pin A
EN
C
B
Pin B
E
Pin A
N
P
+
N
P
P
N
+
N
P substrate
P+
Parasitic
element
P
P
C
+
N
E
P substrate
GND
Parasitic element
B
N
GND
Parasitic element
GND
GND
Parasitic
element
Other adjacent elements
Fig.44 Simplified structure of monorisic IC
7. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
8 . Selection of inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.15Ω or less. Note that use of a high DCR
inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified
period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF.
When using an inductor over 0.15Ω, be careful to ensure adequate margins for variation between external devices and
BU9153MUV, including transient as well as static characteristics.
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17/18
2009.08 - Rev.A
Technical Note
BD9153MUV
●Ordering part number
B
D
9
Part No.
1
5
3
M
Part No.
U
V
-
E
2
Packaging and forming specification
Package
MUV: VQFN24V4040
E2: Embossed tape and reel
(VQFN24V4040)
VQFN024V4040
<Tape and Reel information>
4.0±0.1
4.0±0.1
1.0MAX
2.4±0.1
0.4±0.1
7
12
19
18
0.5
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
6
24
0.75
E2
2.4±0.1
1
2500pcs
(0.22)
+0.03
0.02 -0.02
S
C0.2
Embossed carrier tape
Quantity
Direction
of feed
1PIN MARK
0.08 S
Tape
13
+0.05
0.25 -0.04
1pin
(Unit : mm)
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Reel
18/18
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.08 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
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R0039A