AD ADM8690 Microprocessor supervisory circuit Datasheet

Microprocessor
Supervisory Circuits
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
VBATT
VOUT
VCC
WATCHDOG
TRANSITION DETECTOR
(1.6s)
ADM8690/
ADM8692
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
1.3V
1VOLTAGE
2RESET
DETECTOR = 4.65V (ADM8690)
4.40V (ADM8692)
PULSE WIDTH = 50ms (AD8690, ADM8692)
Figure 1. ADM8690/ADM8692
BATT ON
ADM8691/
ADM8693/
ADM8695
VBATT
PRODUCT HIGHLIGHTS
The ADM8690 and ADM8692 are available in 8-lead, PDIP
packages and provide:
1.
2.
3.
4.
Power-on reset output during power-up, power-down, and
brownout conditions. The RESET output remains
operational with VCC as low as 1 V.
Battery backup switching for CMOS RAM, CMOS
microprocessor, or other low power logic.
A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
A 1.3 V threshold detector for power-fail warning, low battery
detection, or to monitor a power supply other than 5 V.
The ADM8691, ADM8693, and ADM8695 are available in 16-lead
PDIP and small outline packages (including TSSOP) and
provide three additional functions:
1.
2.
3.
RESET
00093-001
WATCHDOG
INPUT (WDI)
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Automotive systems
RESET
GENERATOR2
4.65V1
VOUT
VCC
CEIN
CEOUT
LOW LINE
4.65V1
RESET
OSC IN
OSC SEL
WATCHDOG
INPUT (WDI)
RESET AND
WATCHDOG
TIME BASE
RESET
GENERATOR
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
TIMER
POWER FAIL
INPUT (PFI)
RESET
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO)
1.3V
1VOLTAGE DETECTOR = 4.65V (ADM8691, ADM8695)
4.40V (ADM8693)
00093-002
Upgrade for ADM690 to ADM695, MAX690 to MAX695
Specified over temperature
Low power consumption (0.7 mW)
Precision voltage monitor
Reset assertion down to 1 V VCC
Low switch on resistance 0.7 Ω normal, 7 Ω in backup
High current drive (100 mA)
Watchdog timer: 100 ms, 1.6 s, or adjustable
400 nA standby current
Automatic battery backup power switching
Extremely fast gating of chip enable signals (3 ns)
Voltage monitor for power fail
Available in TSSOP package
Figure 2. ADM8691/ADM8693/ADM8695
Write protection of CMOS RAM or EEPROM.
Adjustable reset and watchdog timeout periods.
Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
Rev. B
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
Fax: 781.461.3113 ©2006-2011 Analog Devices, Inc. All rights reserved.
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
TABLE OF CONTENTS
Features .............................................................................................. 1
Power-Fail Warning Comparator ............................................. 13
Applications ....................................................................................... 1
Application Information ................................................................ 14
Product Highlights ........................................................................... 1
Increasing the Drive Current .................................................... 14
Functional Block Diagrams ............................................................. 1
Using a Rechargeable Battery for Backup ............................... 14
Revision History ............................................................................... 2
Adding Hysteresis to the Power-Fail Comparator ................. 14
General Description ......................................................................... 3
Monitoring the Status of the Battery ....................................... 14
Specifications..................................................................................... 4
Alternate Watchdog Input Drive Circuits ............................... 15
Absolute Maximum Ratings ............................................................ 6
Typical Applications ....................................................................... 16
ESD Caution .................................................................................. 6
ADM8690 and ADM8692 ......................................................... 16
Pin Configurations and Function Descriptions ........................... 7
ADM8691, ADM8693, and ADM8695 ................................... 16
Typical Performance Characteristics ............................................. 8
RESET Output ............................................................................ 16
Circuit Information ........................................................................ 10
Power-Fail Detector ................................................................... 17
Battery Switchover Section........................................................ 10
RAM Write Protection............................................................... 17
Power-Fail RESET Output......................................................... 10
Watchdog Timer ......................................................................... 17
Watchdog Timer RESET............................................................ 11
Outline Dimensions ....................................................................... 18
Watchdog Output (WDO) ........................................................ 12
Ordering Guide .......................................................................... 19
CE Gating and RAM Write Protection
(ADM8691/ADM8693/ADM8695) ......................................... 12
REVISION HISTORY
6/11—Rev. A to Rev. B
Deleted ADM8694......................................................... Throughout
Updated Figure 11, Figure 12, and Figure 13................................ 9
Updated Outline Dimensions ....................................................... 18
9/06—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Absolute Maximum Ratings ....................................... 6
Updated Ordering Guide ............................................................... 20
2/97—Revision 0: Initial Version
Rev. B | Page 2 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
GENERAL DESCRIPTION
The ADM869x family of supervisory circuits offers complete
single- chip solutions for power supply monitoring and battery
control functions in microprocessor systems. These functions
include microprocessor reset, backup battery switchover,
watchdog timer, CMOS RAM write protection, and power
failure warning. The complete family provides a variety of
configurations to satisfy most microprocessor system
requirements.
The ADM869x family is fabricated using an advanced epitaxial
CMOS process combining low power consumption (0.7 mW),
extremely fast chip enable gating (3 ns), and high reliability.
RESET assertion is guaranteed with VCC as low as 1 V. In
addition, the power switching circuitry is designed for minimal
voltage drop thereby permitting increased output current drive
of up to 100 mA without the need of an external pass transistor.
See Table 1 for a product selection guide listing the characteristics
of each device in the ADM869x family. To place an order, use
the Ordering Guide provided as the last section of this data sheet.
Table 1. Product Selection Guide
Part
Number
ADM8690
ADM8691
ADM8692
ADM8693
ADM8695
Nominal
Reset Time
50 ms
50 ms or ADJ
50 ms
50 ms or ADJ
200 ms or ADJ
Nominal VCC Reset
Threshold
4.65 V
4.65 V
4.4 V
4.4 V
4.65 V
Nominal Watchdog
Timeout Period
1.6 s
100 ms, 1.6 s, ADJ
1.6 s
100 ms, 1.6 s, ADJ
100 ms, 1.6 s, ADJ
Rev. B | Page 3 of 20
Battery Backup
Switching
Yes
Yes
Yes
Yes
Yes
Base Drive
Ext PNP
No
Yes
No
Yes
Yes
Chip Enable
Signals
No
Yes
No
Yes
Yes
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
SPECIFICATIONS
VCC = full operating range, VBATT = 2.8 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
BATTERY BACKUP SWITCHING
VCC Operating Voltage Range
ADM8690, ADM8691, ADM8695
ADM8692, ADM8693
VBATT Operating Voltage Range
ADM8690, ADM8691, ADM8695
ADM8692, ADM8693
VOUT Output Voltage
VOUT in Battery Backup Mode
Supply Current (Excludes IOUT)
Supply Current in Battery Backup Mode
Battery Standby Current
+ = Discharge, − = Charge
Battery Switchover Threshold
VCC – VBATT
Battery Switchover Hysteresis
BATT ON Output Voltage
BATT ON Output Short-Circuit Current
Min
Max
Unit
4.75
4.5
5.5
5.5
V
V
2.0
2.0
VCC − 0.005
VCC − 0.2
VBATT − 0.005
4.25
4.0
V
V
V
V
V
µA
µA
Watchdog Timeout Period, External Clock
Minimum WDI Input Pulse Width
RESET Output Voltage @ VCC = 1 V
RESET, LOW LINE Output Voltage
VCC − 0.0025
VCC − 0.125
VBATT − 0.002
140
0.4
−0.1
200
1
+0.02
70
50
20
0.3
0.5
RESET AND WATCHDOG TIMER
Reset Voltage Threshold
ADM8690, ADM8691, ADM8695
ADM8692, ADM8693
Reset Threshold Hysteresis
Reset Timeout Delay
ADM8690, ADM8691, ADM8692,
ADM8693,
ADM8695
Watchdog Timeout Period, Internal Oscillator
Typ
55
2.5
25
IOUT = 1 mA
IOUT ≤ 100 mA
IOUT = 250 µA, VCC < VBATT − 0.2 V
IOUT = 100 µA
VCC = 0 V, VBATT = 2.8 V
5.5 V > VCC > VBATT + 0.2 V
TA = 25°C
Power-up
Power-down
ISINK = 3.2 mA
BATT ON = VOUT = 4.5 V sink current
BATT ON = 0 V source current
4.5
4.25
4.65
4.4
40
4.73
4.48
V
V
mV
35
50
70
ms
OSC SEL = high
140
1.0
70
3840
768
50
200
1.6
100
4064
1011
280
2.25
140
4097
1025
4
0.05
20
0.4
ms
s
ms
cycles
cycles
ns
mV
V
V
V
V
µA
mA
OSC SEL = high
Long period
Short period
Long period
Short period
VIL = 0.4, VIH = 3.5 V
ISINK = 10 µA, VCC = 1 V
ISINK = 1.6 mA, VCC = 4.25 V
ISOURCE = 1 µA
ISINK = 1.6 mA
ISOURCE = 1 µA
3.5
RESET, WDO Output Voltage
Output Short-Circuit Source Current
Output Short-Circuit Sink Current
WDI Input Threshold 1
Logic Low
Logic High
WDI Input Current
µA
mV
mV
mV
V
mA
µA
Test Conditions/Comments
0.4
3.5
1
10
25
25
0.8
3.5
−10
1
−1
Rev. B | Page 4 of 20
10
V
V
µA
µA
WDI = VOUT
WDI = 0 V
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
Parameter
POWER-FAIL DETECTOR
PFI Input Threshold
PFI Input Current
PFO Output Voltage
PFO Short-Circuit Source Current
PFO Short-Circuit Sink Current
Min
Typ
Max
Unit
Test Conditions/Comments
1.25
−25
1.3
±0.01
1.35
+25
0.4
V
nA
V
V
μA
mA
VCC = 5 V
3.5
1
3
25
CHIP ENABLE GATING
CEIN Threshold
25
0.8
3.0
3
CEIN Pull-Up Current
CEOUT Output Voltage
0.4
VOUT − 1.5
VOUT − 0.05
3
CE Propagation Delay
OSCILLATOR
OSC IN Input Current
OSC SEL Input Pull-Up Current
OSC IN Frequency Range
OSC IN Frequency with External Capacitor
1
7
±2
5
0
500
4
V
V
μA
V
V
V
ns
μA
μA
kHz
kHz
WDI is a three-level input that is internally biased to 38% of VCC and has an input impedance of approximately 5 MΩ.
Rev. B | Page 5 of 20
ISINK = 3.2 mA
ISOURCE = 1 μA
PFI = low, PFO = 0 V
PFI = high, PFO = VOUT
VIL
VIH
ISINK = 3.2 mA
ISOURCE = 3.0 mA
ISOURCE = 1 μA, VCC = 0 V
OSC SEL = 0 V
OSC SEL = 0 V, COSC = 47 pF
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VCC
VBATT
All Other Inputs
Input Current
VCC
VBATT
GND
Digital Output Current
Power Dissipation, N-8 PDIP
θJA Thermal Impedance
Power Dissipation, R-8 SOIC
θJA Thermal Impedance
Power Dissipation, N-16 PDIP
θJA Thermal Impedance
Power Dissipation, RU-16 TSSOP
θJA Thermal Impedance
Power Dissipation, R-16 SOIC_N
θJA Thermal Impedance
Power Dissipation, RW-16 SOIC_W
θJA Thermal Impedance
Operating Temperature Range
Industrial (A Version)
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VOUT + 0.5 V
200 mA
50 mA
20 mA
20 mA
400 mW
120°C/W
400 mW
120°C/W
600 mW
135°C/W
600 mW
158°C/W
600 mW
110°C/W
600 mW
73°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +85°C
300°C
−65°C to +150°C
Rev. B | Page 6 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VBATT 1
16 RESET
VOUT 2
VCC 3
GND 4
ADM8690/
ADM8692
GND 3
TOP VIEW
(Not to Scale)
PFI 4
7 RESET
6 WDI
5 PFO
13 CEIN
TOP VIEW 12 CEOUT
(Not to Scale)
11 WDI
LOW LINE 6
OSC IN 7
OSC SEL 8
Figure 3. ADM8690 and ADM8692,
Pin Configuration
10 PFO
9 PFI
00093-004
VCC 2
14 WDO
BATT ON 5
8 VBATT
00093-003
VOUT 1
15 RESET
ADM8691/
ADM8693/
ADM8695
Figure 4. ADM8691, ADM8693, and ADM8695
Pin Configuration
Table 4. Pin Function Descriptions
Mnemonic
VCC
VBATT
VOUT
GND
RESET
WDI
PFI
PFO
CEIN
CEOUT
BATT ON
LOW LINE
RESET
OSC SEL
OSC IN
WDO
Function
Power Supply Input. 5 V nominal.
Backup Battery Input.
Output Voltage. VCC or VBATT is internally switched to VOUT, depending on which is at the highest potential. VOUT can supply up to
100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBATT are not used.
Ground. This is the 0 V ground reference for all signals.
Logic Output. RESET goes low if VCC falls below the reset threshold, or the watchdog timer is not serviced within its timeout
period. The reset threshold is typically 4.65 V for the ADM8690/ADM8691/ADM8695 and 4.4 V for the ADM8692 and
ADM8693. RESET remains low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8695) after VCC returns
above the threshold. RESET also goes low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8695) if the
watchdog timer is enabled but not serviced within its timeout period. The RESET pulse width can be adjusted on the
ADM8691/ADM8693/ADM8695, as shown in Table 5. The RESET output has an internal 3 µA pull-up, and can either connect to
an open collector reset bus or directly drive a CMOS gate without an external pull-up resistor.
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period,
RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog timer can be
disabled if WDI is left floating or is driven to midsupply.
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than 1.3 V, PFO goes low.
Connect PFI to GND or VOUT when not used.
Power-Fail Output. PFO is the output of the power-fail comparator. It goes low when PFI is less than 1.3 V. The comparator is
turned off and PFO goes low when VCC is below VBATT.
Logic Input. The input to the CE gating circuit. When not in use, connect this pin to GND or VOUT.
Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset threshold. If VCC is below
the reset threshold, CEOUT is forced high. See Figure 21 and Figure 22.
Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT is internally
switched to VCC. The output typically sinks 35 mA and can directly drive the base of an external PNP transistor to increase the
output current above the 100 mA rating of VOUT.
Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset
threshold.
Logic Output. RESET is an active high output. It is the inverse of RESET.
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets the reset
active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has
a 3 µA internal pull-up (see Table 5).
Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be
connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period (see
Table 5 and Figure 17, Figure 18, Figure 19, and Figure 20). With OSC SEL high or floating, the internal oscillator is enabled and
the reset active time is fixed at 50 ms typical (ADM8691/ADM8693) or 200 ms typical (ADM8695). In this mode, the OSC IN pin
selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout period immediately
after a reset is 1.6 s typical.
Logic Output. The watchdog output, WDO, goes low if WDI remains either high or low for longer than the watchdog timeout
period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply, the watchdog timer is disabled
and WDO remains high. WDO also goes high when LOW LINE goes low.
Rev. B | Page 7 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
TYPICAL PERFORMANCE CHARACTERISTICS
1.315
5.00
1.310
PFI INPUT THRESHOLD (V)
4.99
4.97
4.96
4.95
1.300
1.295
1.290
1.285
20
30
40
50
60
IOUT (mA)
70
80
90
100
1.280
–60
00093-015
4.94
10
1.305
Figure 5. VOUT vs. IOUT Normal Operation
–30
0
30
60
TEMPERATURE (°C)
90
00093-018
VOUT (V)
4.98
120
Figure 8. PFI Input Threshold vs. Temperature
2.800
53
VCC = 5V
2.794
2.792
2.790
52
51
ADM8690/
ADM8691/
ADM8692/
ADM8693
50
2.788
250
350
450
550
650
IOUT (µA)
750
850
950
1050
49
20
00093-016
2.786
150
40
Figure 6. VOUT vs. IOUT Battery Backup
60
80
TEMPERATURE (°C)
100
120
Figure 9. Reset Active Time vs. Temperature
4.69
VCC = 5V
3.36V
100
90
10
0%
1V
1V
500ms
4.67
4.65
4.63
4.61
4.59
4.57
4.55
–60
–30
0
30
60
TEMPERATURE (°C)
90
Figure 10. Reset Voltage Threshold vs. Temperature
Figure 7. Reset Output Voltage vs. Supply Voltage
Rev. B | Page 8 of 20
120
00093-020
RESET VOLTAGE THRESHOLD (V)
A4
00093-017
VOUT (V)
2.796
00093-019
RESET ACTIVE TIME (ms)
2.798
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
6
6
5
4
4
3
3
VPFI
5V
PFO
2
2
1.3V
30pF
1
1
0
0
1.35
PFI
1.25
0.1
0.2
0.3
0.4
0.5
TIME (µs)
0.6
0.7
00093-021
0
0.8
Figure 11. Power-Fail Comparator Response Time Falling
1.3V
PFO
30pF
VCC = 5V
TA = 25°C
3
2
VPFI
PFO
1
1.3V
30pF
PFO
1.35
10
20
30
40
50
TIME (µs)
60
70
80
90
00093-022
PFI
0
PFI
0.2
0.4
0.6
0.8
1.0
TIME (µs)
1.2
1.4
1.6
1.8
Figure 13. Power-Fail Comparator Response Time with Pull-Up Resistor
4
1.25
PFO
0
6
0
10kΩ
VPFI
1.35
1.25
5
VCC = 5V
TA = 25°C
00093-023
5
VCC = 5V
TA = 25°C
PFO
Figure 12. Power-Fail Comparator Response Time Rising
Rev. B | Page 9 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
CIRCUIT INFORMATION
BATTERY SWITCHOVER SECTION
The battery switchover circuit compares VCC to the VBATT input,
and connects VOUT to whichever is higher. Switchover occurs
when VCC is 50 mV higher than VBATT as VCC falls, and when VCC
is 70 mV greater than VBATT as VCC rises. This 20 mV of
hysteresis prevents repeated rapid switching if VCC falls very
slowly or remains nearly equal to the battery voltage.
VOUT
RESET is an active low output that provides a RESET signal to
the microprocessor whenever VCC is at an invalid level. When
VCC falls below the reset threshold, the RESET output is forced
low. The nominal reset voltage threshold is 4.65 V (ADM8690/
ADM8691/ADM8695) or 4.4 V (ADM8692/ADM8693).
GATE DRIVE
VCC
00093-005
700
mV
BATT ON
(ADM8690,
ADM8695)
Figure 14. Battery Switchover Schematic
During normal operation, with VCC higher than VBATT, VCC
is internally switched to VOUT through an internal PMOS transistor switch. This switch has a typical on resistance of 0.7 Ω
and can supply up to 100 mA at the VOUT terminal. VOUT is
normally used to drive a RAM memory bank, requiring
instantaneous currents of greater than 100 mA. If this is the
case, a bypass capacitor should be connected to VOUT. The
capacitor provides the peak current transients to the RAM.
A capacitance value of 0.1 μF or greater can be used.
If the continuous output current requirement at VOUT exceeds
100 mA, or if a lower VCC − VOUT voltage differential is desired,
an external PNP pass transistor can be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the
external transistor.
A 7 Ω MOSFET switch connects the VBATT input to VOUT during
battery backup. This MOSFET has very low input-to-output
differential (dropout voltage) at the low current levels required
for battery back up of CMOS RAM or other low power CMOS
circuitry. The supply current in battery back up is typically 0.4 μA.
The ADM8690/ADM8691/ADM8695 operate with battery
voltages from 2.0 V to 4.25 V, and the ADM8692/
ADM8693 operate with battery voltages from 2.0 V to 4.0 V.
High value capacitors, either standard electrolytic or the faradsize, double-layer capacitors, can also be used for short-term
memory backup. A small charging current of typically 10 nA
(0.1 μA maximum) flows out of the VBATT terminal. This current
is useful for maintaining rechargeable batteries in a fully
RESET
V2
V1
t1
V2
V1
t1
LOW LINE
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
00093-006
VBATT
INTERNAL
SHUTDOWN SIGNAL
WHEN
VBATT > (VCC + 0.7V)
If the battery switchover section is not used, VBATT should be
connected to GND and VOUT should be connected to VCC.
POWER-FAIL RESET OUTPUT
VCC
100
mV
charged condition. This extends the life of the backup battery by
compensating for its self-discharge current. Also note that this
current poses no problem when lithium batteries are used for
backup because the maximum charging current (0.1 μA) is safe
for even the smallest lithium cells.
Figure 15. Power-Fail Reset Timing
On power-up, RESET remains low for 50 ms (200 ms for
ADM8695) after VCC rises above the appropriate reset threshold.
This allows time for the power supply and microprocessor to
stabilize. On power-down, the RESET output remains low with
VCC as low as 1 V. This ensures that the microprocessor is held
in a stable shutdown condition.
This RESET active time is adjustable on the ADM8691/ADM8693/
ADM8695 by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. Refer to Table 5 and
Figure 17, Figure 18, Figure 19, and Figure 20.
The guaranteed minimum and maximum thresholds of the
ADM8690/ADM8691/ADM8695 are 4.5 V and 4.73 V, and the
guaranteed thresholds of the ADM8692/ADM8693 are 4.25 V and
4.48 V. The ADM8690/ADM8691/ADM8695 are, therefore,
compatible with 5 V supplies with a +10%, −5% tolerance and
the ADM8692/ADM8693 are compatible with 5 V ± 10%
supplies. The reset threshold comparator has approximately
50 mV of hysteresis. The response time of the reset voltage
comparator is less than1 μs. If glitches are present on the VCC line
that could cause spurious reset pulses, VCC should be decoupled
close to the device.
Rev. B | Page 10 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
WATCHDOG TIMER RESET
The watchdog timer circuit monitors the activity of the microprocessor to check that it is not stalled in an indefinite loop. An
output line on the processor is used to toggle the watchdog input
(WDI) line. If this line is not toggled within the selected timeout
period, a RESET pulse is generated. The nominal watchdog
timeout period is preset at 1.6 seconds on the ADM8690 and
ADM8692. The ADM8691/ADM8693/ADM8695 can be
configured for either a fixed short 100 ms, or a long 1.6 second
timeout period, or for an adjustable timeout period. If the short
period is selected, some systems are unable to service the
watchdog timer immediately after a reset, so the ADM8691/
ADM8693/ADM8695 automatically select the long timeout
period directly after a reset is issued. The watchdog timer is
restarted at the end of reset, whether the reset was caused by
lack of activity on WDI or by VCC falling below the reset
threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at, or less than, the minimum timeout period. If
WDI remains permanently either high or low, reset pulses are
issued after each long (1.6 s) timeout period. The watchdog
monitor can be deactivated by floating the watchdog input
(WDI) or by connecting it to midsupply.
WDI
WDO
t2
t3
RESET
t1
t1
t1
t1 = RESET TIME
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
00093-007
In addition to RESET, the ADM8691/ADM8693/ADM8695
contain an active high RESET output. This is the complement of
RESET and is intended for processors requiring an active high
reset signal.
Figure 16. Watchdog Timeout Period and Reset Active Time
Table 5. ADM8691, ADM8693, ADM8695 Reset Pulse Width and Watchdog Timeout Selections
OSC SEL
Low1
Low1
Floating or high
Floating or high
1
OSC IN
External clock input
External capacitor
Low
Floating or high
Watchdog Timeout Period
Normal
Immediately After Reset
1024 CLKs
4096 CLKs
400 ms × C/47 pF
1.6 s × C/47 pF
100 ms
1.6 s
1.6 s
1.6 s
Reset Active Period
ADM8691/ADM8693
ADM8695
512 CLKs
2048 CLKs
200 ms × C/47 pF
520 ms × C/47 pF
50 ms
200 ms
50 ms
200 ms
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor (C) can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: FOSC (Hz) = 184,000/C (pF).
Rev. B | Page 11 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; and
with it connected low, the 100 ms timeout period is selected. In
either case, the timeout period is 1.6 seconds immediately after
a reset. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, the 100 ms watchdog period becomes
effective after the first transition of WDI. The software should
be written such that the input/output port driving WDI is left in
its power-up reset state until the initialization routines are
completed and the microprocessor is able to toggle WDI at the
minimum watchdog timeout period of 70 ms.
WATCHDOG OUTPUT (WDO)
The Watchdog Output WDO (ADM8691/ADM8693/ADM8695)
provides a status output that goes low if the watchdog timer
times out and remains low until set high by the next transition
on the watchdog input. WDO is also set high when VCC goes
below the reset threshold.
7
OSC IN
Figure 20. Internal Oscillator (100 ms Watchdog)
CE GATING AND RAM WRITE PROTECTION
(ADM8691/ADM8693/ADM8695)
The ADM8691/ADM8693/ADM8695 products include
memory protection circuitry that ensures the integrity of data
in memory by preventing write operations when VCC is at an
invalid level. There are two additional pins (CEIN and CEOUT)
that can be used to control the chip enable or write inputs of
CMOS RAM. When VCC is present, CEOUT is a buffered replica
of CEIN, with a 3 ns propagation delay. When VCC falls below the
reset voltage threshold or VBATT, an internal gate forces CEOUT
high, independent of CEIN.
CEOUT typically drives the CE, CS, or write input of battery
backed up CMOS RAM. This ensures the integrity of the data in
memory by preventing write operations when VCC is at an
invalid level. Similar protection of EEPROMs can be achieved
using the CEOUT to drive the store or write inputs.
ADM8691
ADM8693
ADM8695
CEIN
CEOUT
VCC LOW = 0
VCC OK = 1
ADM8691/
ADM8693/
ADM8695
7
OSC SEL
ADM8691/
ADM8693/
ADM8695
OSC SEL
CLOCK
0 TO 500kHz
8
00093-012
8
NC
00093-011
On the ADM8690/ADM8692 the watchdog timeout period is
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.
The ADM8691/ADM8693/ADM8695 allow these times to be
adjusted, as shown in Table 5. Figure 17, Figure 18, Figure 19,
and Figure 20 show the various oscillator configurations that
can be used to adjust the reset pulse width and watchdog
timeout period.
Figure 21. Chip Enable Gating
00093-008
OSC IN
VCC
V2
V1
V2
V1
Figure 17. External Clock Source
RESET
8
t1
OSC SEL
ADM8691/
ADM8693/
ADM8695
LOW LINE
OSC IN
00093-009
7
t1
COSC
Figure 18. External Capacitor
CEIN
OSC SEL
NC
7
OSC IN
CEOUT
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 19. Internal Oscillator (1.6 Second Watchdog)
Figure 22. Chip Enable Timing
Rev. B | Page 12 of 20
00093-013
ADM8691/
ADM8693/
ADM8695
00093-010
NC
8
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
POWER-FAIL WARNING COMPARATOR
An additional comparator is provided for early warning of
failure in the microprocessor power supply. The power-fail
input (PFI) is compared to an internal 1.3 V reference. The
power-fail output (PFO) goes low when the voltage at PFI is less
than 1.3 V. Typically, PFI is driven by an external voltage divider
that senses either the unregulated dc input to the system 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V
several milliseconds before the 5 V power supply falls below the
reset threshold. PFO is normally used to interrupt the
microprocessor so that data can be stored in RAM and the shutdown procedure executed before power is lost.
R2
PFO
POWER
FAIL
INPUT
POWER
FAIL
OUTPUT
00093-014
1.3V
R1
Signal
VOUT
RESET
RESET
LOW LINE
BATT ON
WDI
WDO
PFI
ADM869x
INPUT
POWER
Table 6. Input and Output Status in Battery Backup Mode
PFO
CEIN
Figure 23. Power-Fail Comparator
CEOUT
OSC IN
OSC SEL
Rev. B | Page 13 of 20
Status
VOUT is connected to VBATT via an internal PMOS
switch.
Logic low.
Logic high. The open-circuit output voltage is equal
to VOUT.
Logic low.
Logic high. The open-circuit voltage is equal to VOUT.
WDI is ignored. It is internally disconnected from the
internal pull-up resistor and does not source or sink
current as long as its input voltage is between GND
and VOUT. The input voltage does not affect supply
current.
Logic high. The open circuit voltage is equal to VOUT.
The power-fail comparator is turned off and has no
effect on the power-fail output.
Logic low.
CEIN is ignored. It is internally disconnected from its
internal pull-up and does not source or sink current
as long as its input voltage is between GND and
VOUT. The input voltage does not affect supply
current.
Logic high. The open circuit voltage is equal to VOUT.
OSC IN is ignored.
OSC SEL is ignored.
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
APPLICATION INFORMATION
INCREASING THE DRIVE CURRENT
If the continuous output current requirements at VOUT exceed
100 mA, or if a lower VCC – VOUT voltage differential is desired,
an external PNP pass transistor can be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the
external transistor.
0.1µF
BATTERY
(
R1 R1
VH = 1.3V 1+ R + R
3
2
(
0V
VL
VIN
HYSTERESIS VH – VL = 5V
VH
( RR12 )
Figure 26. Adding Hysteresis to the Power-Fail Comparator
0.1µF
VOUT
The power-fail comparator can be used to monitor the status of
the backup battery instead of the power supply, if desired. This
is shown in Figure 27. The PFI input samples the battery voltage
and generates an active low PFO signal when the battery voltage
drops below a chosen threshold. It can be necessary to apply a
test load to determine the loaded battery voltage. This is done
under processor control using CEOUT. Because CEOUT is forced
high during the battery backup mode, the test load is not
applied to the battery while it is in use, even if the
microprocessor is not powered.
ADM869x
VBATT
5V INPUT
POWER
00093-025
RECHARGEABLE
BATTERY
)
MONITORING THE STATUS OF THE BATTERY
VOUT – VBATT
R
R
)
R1
R1 (5V – 1.3V)
–
VL = 1.3V 1+
R2 R3 (1.3V (R3 + R4))
ASSUMING R4 < < R3 THEN
If a capacitor or a rechargeable battery is used for backup then
the charging resistor should be connected to VOUT because this
eliminates the discharge path that would exist during powerdown if the resistor is connected to VCC.
VCC
R3
0V
ADM8691/
ADM8693/
ADM8695
0.1µF
TO
MICROPROCESSOR
NMI
ADM869x
R2
PFO
USING A RECHARGEABLE BATTERY FOR BACKUP
I=
PFO
PFI
VOUT
Figure 24. Increasing the Drive Current
5V INPUT
POWER
R4
1.3V
00093-024
VBATT
BATT
ON
VCC
R1
00093-026
VCC
5V
VBATT
Figure 25. Rechargeable Battery
BATTERY
ADDING HYSTERESIS TO THE POWER-FAIL
COMPARATOR
R1
PFI
For increased noise immunity, hysteresis can be added to the
power-fail comparator. Because the comparator circuit is
noninverting, hysteresis can be added simply by connecting a
resistor between the PFO output and the PFI input as shown in
Figure 26. When PFO is low, Resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, the series
combination of R3 and R4 sources current into the PFI
summing junction. This results in differing trip levels for the
comparator.
20kΩ
OPTIONAL
TEST LOAD
Rev. B | Page 14 of 20
R2
VCC
PFO
LOW BATTERY
SIGNAL TO
MICROPROCESSOR
I/O PIN
10MΩ
ADM869x
10MΩ
CEIN
CEOUT
FROM
MICROPROCESSOR
I/O PIN APPLIES
TEST LOAD
TO BATTERY
Figure 27. Monitoring the Battery Status
00093-027
0.1µF
7805
5V
PNP TRANSISTOR
5V INPUT
POWER
7V TO 15V
INPUT
POWER
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
The watchdog feature can be enabled and disabled under
program control by driving WDI with a three-state buffer (see
Figure 28). When three-stated, the WDI input floats, thereby
disabling the watchdog timer.
CONTROL
INPUT
WDI
ADM869x
00093-028
WATCHDOG
STROBE
Figure 28. Programming the Watchdog Input
This can be done under program control using the circuit
shown in Figure 29. When the control input is high, the
OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01 µF capacitor sets a watchdog timeout delay of 100 seconds. When the control input is low, the
OSC SEL pin is driven high, selecting the internal oscillator.
The 100 ms or the 1.6 s period is chosen, depending on which
diode is used, as shown in Figure 29. With D1 inserted, the
internal timeout is set at 100 ms; with D2 inserted, the timeout
is set at 1.6 seconds.
This circuit is not entirely foolproof, and it is possible for a
software fault to erroneously three-state the buffer preventing
the ADM869x from detecting that the microprocessor is no
longer operating correctly. In most cases, a better method is to
extend the watchdog period rather than disable the watchdog.
Rev. B | Page 15 of 20
CONTROL
INPUT1
OSC SEL
D1
ADM869x
D2
OSC IN
1LOW
= INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 29. Programming the Watchdog Input
00093-029
ALTERNATE WATCHDOG INPUT DRIVE CIRCUITS
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
TYPICAL APPLICATIONS
The watchdog timer input (WDI) monitors an input/output line
from the microprocessor system. This line must be toggled once
every 1.6 seconds to verify correct software execution. Failure to
toggle the line indicates that the microprocessor system is not
correctly executing its program and can be tied up in an endless
loop. If this happens, a reset pulse is generated to initialize the
microprocessor.
If the watchdog timer is not needed, the WDI input should be
left floating.
The power-fail input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is
compared with a precision 1.3 V internal reference. If the input
voltage drops below 1.3 V, a power-fail output (PFO) signal is
generated. This warns of an impending power failure and can
be used to interrupt the processor so that the system can be shut
down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power-fail threshold
voltage (VT).
VT = (1.3 R1/R2) + 1.3 V
5V
7805
0.1µF
R1
VCC
POWER
0.1µF
ADM8690/
ADM8692
R2
BATTERY
+
VBATT
MICROPROCESSOR
SYSTEM
PFO
A typical connection for the ADM8691/ADM8693/ADM8695
is shown in Figure 32. CMOS RAM is powered from VOUT.
When 5 V power is present, this is routed to VOUT. If VCC fails,
VBATT is routed to VOUT. VOUT can supply up to 100 mA from
VCC, but if more current is required, an external PNP transistor
can be added. When VCC is higher than VBATT, the BATT ON
output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1 µF capacitor is connected to VOUT to
supply the transient currents for CMOS RAM. When VCC is
lower than VBATT, an internal 20 Ω MOSFET connects the
backup battery to VOUT.
INPUT POWER
5V
0.1µF
0.1µF
VCC
3V
BATTERY
VBATT
R1
PFI
GND
R2
NC
VOUT
BATT
ON
CEOUT
ADM8691/
ADM8693/
ADM8695
OSC IN
OSC SEL
CEIN
RESET
PFO
GND WDI
0.1µF
ADDRESS
DECODE
A0 TO 15
WDI
I/O LINE
PFO
NMI
RESET
RESET
RESET
0.1µF MICROPROCESSOR
SYSTEM
SYSTEM STATUS
INDICATORS
CMOS RAM
POWER
Figure 32. ADM8691/ADM8693/ADM8695 Typical Application
MICROPROCESSOR
SYSTEM
RESET OUTPUT
RESET
NMI
I/O LINE
00093-030
BATTERY
VOUT
ADM8690/
ADM8692
VBATT
CMOS
RAM
POWER
VCC
+
I/O LINE
ADM8691, ADM8693, AND ADM8695
LOW LINE WDO
R2
NMI
Figure 31. ADM8690/ADM8692 Typical Application Circuit B
5V
PFI
RESET
RESET
GND WDI
R1/R2 = (VT/1.3) − 1
R1
CMOS RAM
POWER
VOUT
PFI
00093-031
Figure 30 shows the ADM8690/ADM8692 in a typical power
monitoring, battery backup application. VOUT powers the CMOS
RAM. Under normal operating conditions with VCC present,
VOUT is internally connected to VCC. If a power failure occurs,
VCC decays and VOUT is switched to VBATT, thereby maintaining
power for the CMOS RAM. A RESET pulse is also generated
when VCC falls below 4.65 V for the ADM8690 or 4.4 V for the
ADM8692. RESET remains low for 50 ms after VCC returns to 5 V.
INPUT
POWER
V > 8V
Figure 30. ADM8690/ADM8692 Typical Application Circuit A
Figure 31 shows a similar application, but in this case the PFI
input monitors the unregulated input to the 7805 voltage
regulator. This gives an earlier warning of an impending power
failure. It is useful with processors operating at low speeds or
where there are a significant number of housekeeping tasks to
be completed before the power is lost.
The internal voltage detector monitors VCC and generates a
RESET output to hold the microprocessor reset line low when
VCC is below 4.65 V (4.4 V for ADM8693). An internal timer
holds RESET low for 50 ms (200 ms for the ADM8695) after
VCC rises above 4.65 V (4.4 V for the ADM8693). This prevents
repeated toggling of RESET, even if the 5 V power drops out
and recovers with each power line cycle.
The crystal oscillator normally used to generate the clock for
microprocessors can take several milliseconds to stabilize.
Because most microprocessors need several clock cycles to
reset, RESET must be held low until the microprocessor clock
oscillator has started. The power-up RESET pulse lasts 50 ms
Rev. B | Page 16 of 20
00093-032
ADM8690 AND ADM8692
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
(200 ms for the ADM8695) to allow for this oscillator start-up
time. If a different reset pulse width is required, a capacitor
should be connected to OSC IN, or an external clock can be
used. Refer to Table 5 and Figure 17, Figure 18, Figure 19, and
Figure 20. The manual reset switch and the 0.1 µF capacitor
connected to the reset line can be omitted if a manual reset is
not needed. An inverted, active high, RESET output is also
available.
POWER-FAIL DETECTOR
The 5 V VCC power line is monitored via a resistive potential
divider connected to the power-fail input (PFI). When the
voltage at PFI falls below 1.3 V, the power-fail output (PFO)
drives the processor’s NMI input low. If, for example, a powerfail threshold of 4.8 V is set with Resistor R1 and Resistor R2, the
microprocessor has the time when VCC falls from 4.8 V to 4.65 V
to save data into RAM. An earlier power-fail warning can be
generated if the unregulated dc input to the 5 V regulator is
available for monitoring. This allows more time for microprocessor
housekeeping tasks to be completed before power is lost.
RAM WRITE PROTECTION
The ADM8691/ADM8693/ADM8695 CEOUT line drives the
chip select inputs of the CMOS RAM. CEOUT follows CEIN as
long as VCC is above the 4.65 V (4.4 V for the ADM8693) reset
threshold.
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts, and momentary power
interruptions.
WATCHDOG TIMER
The microprocessor drives the watchdog input (WDI) with an
input/output line. When OSC IN and OSC SEL are unconnected,
the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware
or software failure occurs such that WDI is not toggled, the
ADM8691/ADM8693 issues a 50 ms (200 ms for the ADM8695)
RESET pulse after 1.6 seconds. This typically restarts the microprocessor power-up routine. A new RESET pulse is issued every
1.6 seconds until WDI is again strobed. If a different watchdog
timeout period is required, a capacitor should be connected to
OSC IN or an external clock can be used. Refer to Table 5 and
Figure 17, Figure 18, Figure 19, and Figure 20.
The watchdog output (WDO) goes low if the watchdog timer is
not serviced within its timeout period. Once WDO goes low, it
remains low until a transition occurs at WDI. The watchdog
timer feature can be disabled by leaving WDI unconnected.
The RESET output has an internal 3 µA pull-up and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.
If VCC falls below the reset threshold, CEOUT goes high,
independent of the logic level at CEIN. This prevents the
Rev. B | Page 17 of 20
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
8
4.00 (0.1574)
3.80 (0.1497)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
070606-A
10.50 (0.4134)
10.10 (0.3976)
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
9
8
9
16
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
7.60 (0.2992)
7.40 (0.2913)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.005 (0.13)
MIN
1
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.430 (10.92)
MAX
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
0.75 (0.0295)
45°
0.25 (0.0098)
8°
0°
0.33 (0.0130)
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
073106-B
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
8
1.27 (0.0500)
BSC
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.50 (0.0196)
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
Figure 35. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
6.20 (0.2441)
5.80 (0.2284)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
1
4
0.25 (0.0098)
0.10 (0.0040)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
16
5
1.27 (0.0500)
BSC
0.430 (10.92)
MAX
0.005 (0.13)
MIN
1
Figure 34. 16-Lead Plastic Dual In-Line Package [PDIP]
(N-16)
Dimensions shown in inches and (millimeters)
Figure 36. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
Rev. B | Page 18 of 20
03-27-2007-B
8
1
012407-A
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
10.00 (0.3937)
9.80 (0.3858)
4.00 (0.1575)
3.80 (0.1496)
5.10
5.00
4.90
9
16
1
8
6.20 (0.2441)
5.80 (0.2283)
16
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.50 (0.0197)
0.25 (0.0098)
4.50
4.40
4.30
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
9
6.40
BSC
1
1.27 (0.0500)
0.40 (0.0157)
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 37. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
Figure 38. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADM8690AN
ADM8690ANZ
ADM8690ARN
ADM8690ARN-REEL
ADM8690ARNZ
ADM8691ANZ
ADM8691ARN
ADM8691ARN-REEL
ADM8691ARNZ
ADM8691ARW
ADM8691ARW-REEL
ADM8691ARWZ
ADM8691ARU
ADM8691ARU-REEL
ADM8691ARUZ
ADM8692ARNZ
ADM8693AN
ADM8693ANZ
ADM8693ARN
ADM8693ARN-REEL
ADM8693ARNZ
ADM8693ARW
ADM8693ARW-REEL
ADM8693ARWZ
ADM8693ARU-REEL
ADM8693ARUZ
ADM8695ARW
ADM8695ARW-REEL
ADM8695ARWZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
8-Lead Standard Small Outline Package [SOIC_N]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
Z = RoHS Compliant Part.
Rev. B | Page 19 of 20
Package Option
N-8
N-8
R-8
R-8
R-8
N-16
R-16
R-16
R-16
RW-16
RW-16
RW-16
RU-16
RU-16
RU-16
R-8
N-16
N-16
R-16
R-16
R-16
RW-16
RW-16
RW-16
RU-16
RU-16
RW-16
RW-16
RW-16
0.75
0.60
0.45
ADM8690/ADM8691/ADM8692/ADM8693/ADM8695
NOTES
©2006-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00093-0-6/11(B)
Rev. B | Page 20 of 20