Cypress CY62128EV30 1-mbit (128 k ã 8) static ram typical standby current: 1 î¼a Datasheet

CY62128EV30 MoBL®
1-Mbit (128 K × 8) Static RAM
1-Mbit (128 K × 8) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
■
Temperature ranges:
❐ Industrial: –40 °C to +85 °C
■
Wide voltage range: 2.2 V to 3.6 V
■
Pin compatible with CY62128DV30
■
Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 4 µA
■
Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE features
■
Automatic power-down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Offered in Pb-free 32-pin SOIC, 32-pin thin small outline
package (TSOP) I, and 32-pin shrunk thin small outline
package (STSOP) packages
The CY62128EV30[1] is a high performance CMOS static RAM
module organized as 128 K words by 8-bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE1 HIGH or CE2 LOW). The
eight input and output pins (I/O0 through I/O7) are placed in a
high impedance state when the device is deselected (CE1 HIGH
or CE2 LOW), the outputs are disabled (OE HIGH), or a write
operation is in progress (CE1 LOW and CE2 HIGH and WE
LOW).
To write to the device, take chip enable (CE1 LOW and CE2
HIGH) and write enable (WE) inputs LOW. Data on the eight I/O
pins is then written into the location specified on the address pin
(A0 through A16).
To read from the device, take chip enable (CE1 LOW and CE2
HIGH) and output enable (OE) LOW while forcing write enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
Logic Block Diagram
I/O 2
SENSE AMPS
ROW DECODER
I/O 1
128K x 8
ARRAY
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
POWER
DOWN
A16
A12
A13
OE
A14
COLUMN DECODER
WE
A15
CE1
CE2
I/O 0
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05579 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 6, 2011
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CY62128EV30 MoBL®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
Data Retention Characteristics ....................................... 5
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 7
Truth Table .................................................................. 8
Document #: 38-05579 Rev. *I
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Package Diagrams .......................................................... 10
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
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CY62128EV30 MoBL®
Pin Configuration
Figure 1. 32-pin STSOP [2]
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
25
26
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
Figure 2. 32-pin TSOP I [2]
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Top View
(not to scale)
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Top View
(not to scale)
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Figure 3. 32-pin SOIC [2]
Top View
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Product Portfolio
Power Dissipation
Product
Range
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1 MHz
CY62128EV30LL
Industrial
Min
Typ[3]
Max
2.2
3.0
3.6
45
f = fmax
Standby ISB2 (µA)
Typ[3]
Max
Typ[3]
Max
Typ[3]
Max
1.3
2.0
11
16
1
4
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document #: 38-05579 Rev. *I
Page 3 of 15
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CY62128EV30 MoBL®
Maximum Ratings
DC input voltage[4, 5] ......................–0.3 V to VCC(max) + 0.3 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Supply voltage to ground
potential ........................................–0.3 V to VCC(max) + 0.3 V
DC voltage applied to outputs
in high Z State[4, 5] ..........................–0.3 V to VCC(max) + 0.3 V
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage.......................................... > 2001 V
(MIL-STD-883, method 3015)
Latch-up current ..................................................... > 200 mA
Operating Range
Device
Range
CY62128EV30LL
Industrial
Ambient
Temperature
VCC[6]
–40 °C to +85 °C 2.2 V to
3.6 V
Electrical Characteristics
(Over the Operating Range)
Parameter
VOH
VOL
VIH
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Test Conditions
45 ns (Industrial)
Min
Typ[7]
Max
Unit
IOH = –0.1 mA
2.0
–
–
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
–
–
V
IOL = 0.1 mA
–
–
0.4
V
IOL = 2.1 mA, VCC > 2.70 V
–
–
0.4
V
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3 V
V
VCC= 2.7 V to 3.6 V
2.2
–
VCC + 0.3 V
V
–
0.6
V
VIL
Input LOW voltage
VCC = 2.2 V to 2.7 V
–0.3
VCC= 2.7 V to 3.6 V
–0.3
–
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
µA
IOZ
Output leakage current
GND < VO < VCC, output disabled
–1
–
+1
µA
ICC
VCC operating supply current
f = fmax = 1/tRC
–
11
16
mA
–
1.3
2.0
mA
f = 1 MHz
VCC = VCCmax IOUT =
0 mA CMOS levels
ISB1
Automatic CE
power-down
current — CMOS inputs
CE1 > VCC0.2 V, CE2 < 0.2 V
VIN > VCC – 0.2 V, VIN < 0.2 V
f = fmax (address and data Only),
f = 0 (OE and WE), VCC = 3.60 V
–
1
4
µA
ISB2[8]
Automatic CE
power-down
current — CMOS inputs
CE1 > VCC – 0.2 V, CE2 < 0.2 V
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–
1
4
µA
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 38-05579 Rev. *I
Page 4 of 15
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CY62128EV30 MoBL®
Capacitance
Parameter[9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
TA = 25 °C, f = 1 MHz,
VCC = VCC(typ)
Unit
10
pF
10
pF
Thermal Resistance
Parameter[9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
TSOP I
SOIC
STSOP
Unit
Still air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
33.01
48.67
32.56
°C/W
3.42
25.86
3.59
°C/W
Figure 4. AC Test Loads and Waveforms
R1
VCC
OUTPUT
ALL INPUT PULSES
VCC
R2
30 pF
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
GND
Rise Time = 1 V/ns
Equivalent to:
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
RTH
OUTPUT
Parameters
2.50V
R1
R2
RTH
VTH
V
3.0V
Unit
16667
1103

15385
1554

8000
645

1.20
1.75
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
Description
Conditions
Min
Typ[10]
Max Unit
1.5
–
–
V
–
–
3
µA
VDR
VCC for data retention
ICCDR[11]
Data retention current
tCDR[9]
Chip deselect to data retention time
0
–
–
ns
tR
Operation recovery time
45
–
–
ns
[12]
VCC = 1.5 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
Industrial
Note
9. Tested initially and after any design or process changes that may affect these parameters.
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
12. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min)  100 µs.
Document #: 38-05579 Rev. *I
Page 5 of 15
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CY62128EV30 MoBL®
Figure 5. Data Retention Waveform [13]
DATA RETENTION MODE
VCC(min)
VCC
VCC(min)
VDR > 1.5 V
tR
tCDR
CE
Switching Characteristics
(Over the Operating Range)[13, 14]
Parameter
Description
45 ns (Industrial)
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to low Z
5
–
ns
tHZOE
OE HIGH to high Z
–
18
ns
tLZCE
CE LOW to low Z
10
–
ns
tHZCE
CE HIGH to high Z
–
18
ns
tPU
CE LOW to power-up
0
–
ns
CE HIGH to power-down
–
45
ns
tWC
Write cycle time
45
–
ns
tSCE
CE LOW to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to high Z
18
ns
tLZWE
WE HIGH to low Z
–
ns
[15, 16]
[15]
[15, 16]
tPD
Write Cycle
[15]
[17]
[15, 16]
[15]
10
Notes
13. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
14. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5.
15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
16. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.
17. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05579 Rev. *I
Page 6 of 15
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CY62128EV30 MoBL®
Switching Waveforms
Figure 6. Read Cycle 1 Address transition controlled [19, 20]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 7. Read Cycle No. 2 OE controlled [20, 21, 22]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
HIGH IMPEDANCE
DATA OUT
DATA VALID
tLZCE
tPD
tPU
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
50%
50%
ICC
ISB
Figure 8. Write Cycle No. 1 WE controlled
[18, 21, 23, 24]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
NOTE
25
tHD
DATA VALID
tHZOE
Notes
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
19. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
20. WE is HIGH for read cycle.
21. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
22. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
23. Data I/O is high impedance if OE = VIH.
24. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
25. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 38-05579 Rev. *I
Page 7 of 15
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CY62128EV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 2 CE1 or CE2 controlled [26, 27, 28, 29]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Figure 10. Write Cycle No. 3 WE controlled, OE LOW [26, 29]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 30
DATA I/O
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE1
CE2
WE
OE
Inputs/Outputs
Mode
Power
H
X[31]
X
X
High Z
Deselect/power-down
Standby (ISB)
X[31]
L
X
X
High Z
Deselect/power-down
Standby (ISB)
L
H
H
L
Data out
Read
Active (ICC)
L
H
L
X
Data in
Write
Active (ICC)
L
H
H
H
High Z
Selected, outputs disabled
Active (ICC)
Notes
26. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
27. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
28. Data I/O is high impedance if OE = VIH.
29. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
30. During this period, the I/Os are in output state. Do not apply input signals.
31. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document #: 38-05579 Rev. *I
Page 8 of 15
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CY62128EV30 MoBL®
Ordering Information
Speed
(ns)
45
Ordering Code
Package
Diagram
Package Type
CY62128EV30LL-45SXI
51-85081 32-pin 450-Mil SOIC (Pb-free)
CY62128EV30LL-45ZXI
51-85056 32-pin TSOP Type I (Pb-free)
CY62128EV30LL-45ZAXI
51-85094 32-pin STSOP (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 2
8
E V30 LL 45 XX
I
Temperature Grade
Package Type: XX = SX or ZX or ZAX
(SX = 32-pin 450-Mil SOIC (Pb-free))
(ZX = 32-pin TSOP I (Pb-free))
(ZAX = 32-pin STSOP (Pb-free))
Speed Grade
LL = Low Power
Voltage Range = 3 V typical
E = Process Technology 90 nm
Buswidth = × 8
Density = 1-Mbit
Family Code: MoBL SRAM family
Company Id: CY=Cypress
Document #: 38-05579 Rev. *I
Page 9 of 15
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CY62128EV30 MoBL®
Package Diagrams
Figure 11. 32-pin (450 Mil) Molded SOIC, 51-85081
51-85081 *C
Document #: 38-05579 Rev. *I
Page 10 of 15
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CY62128EV30 MoBL®
Package Diagrams (continued)
Figure 12. 32-pin Thin Small Outline Package Type I (8 x 20 mm), 51-85056
51-85056 *E
Document #: 38-05579 Rev. *I
Page 11 of 15
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CY62128EV30 MoBL®
Package Diagrams (continued)
Figure 13. 32-pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094
51-85094 *E
Document #: 38-05579 Rev. *I
Page 12 of 15
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CY62128EV30 MoBL®
Acronyms
Acronym
Description
CMOS
complementary metal oxide semiconductor
CE
chip enable
I/O
input/output
OE
output enable
SRAM
static random access memory
TSOP
thin small outline package
STSOP
shrunk thin small outline package
SOIC
small outline integrated circuit
WE
write enable
Document Conventions
Units of Measure
Symbol
MHz
Unit of Measure
Mega Hertz
ns
nano seconds
V
volts
µA
micro amperes
mA
milli amperes
pF
pico Farad
°C
degree Celsius
W
watts
Document #: 38-05579 Rev. *I
Page 13 of 15
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CY62128EV30 MoBL®
Document History Page
Document Title: CY62128EV30 MoBL® 1-Mbit (128 K × 8) Static RAM
Document Number: 38-05579
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
**
285473
See ECN
PCI
New Data Sheet
*A
461631
See ECN
NXR
Converted from Preliminary to Final
Removed 35 ns Speed Bin
Removed “L” version of CY62128EV30
Removed Reverse TSOP I package from Product offering.
Changed ICC (Typ) from 8 mA to 11 mA and ICC (Max) from 12 mA to 16 mA for f
= fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz
Changed ISB2 (max) from 1 A to 4 A
Changed ISB2 (Typ) from 0.5 A to 1 A
Changed ICCDR (max) from 1 A to 3 A
Changed the AC Test load Capacitance value from 50 pF to 30 pF
Changed tLZOE from 3 to 5 ns
Changed tLZCE from 6 to 10 ns
Changed tHZCE from 22 to 18 ns
Changed tPWE from 30 to 35 ns
Changed tSD from 22 to 25 ns
Changed tLZWE from 6 to 10 ns
Updated the Ordering Information table.
*B
464721
See ECN
NXR
Updated the Block Diagram on page # 1
*C
1024520
See ECN
VKN
Added final Automotive-A and Automotive-E information
Added footnote #9 related to ISB2 and ICCDR
Updated Ordering Information table
*D
2257446
See ECN
NXR
Changed the Maximum rating of Ambient Temperature with Power Applied from
55°C to +125°C to –55°C to +125°C.
*E
2702841
05/06/2009
VKN/PYRS Added -45SXA part in the Ordering Information table
Corrected “tPD” spec description in the “Switching Characteristics” table.
*F
2781490
10/08/2009
VKN
Included “CY62128EV30LL-45ZAXA” part in the Ordering Information table
*G
2934428
06/03/10
VKN
Added footnote #21 related to chip enable
Updated package diagrams
Updated template
*H
3026548
09/12/2010
AJU
Updated Pin Configuration
Added Ordering Code Definitions
Added Acronyms and Units of Measure
Minor edits
*I
3115909
01/06/2011
RAME
Document #: 38-05579 Rev. *I
Separated Automotive and Industrial parts from this datasheet.
Removed Automotive info completely
Page 14 of 15
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CY62128EV30 MoBL®
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05579 Rev. *I
Revised January 6, 2011
Page 15 of 15
All products and company names mentioned in this document may be the trademarks of their respective holders.
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