AVAGO ACPM-7312-TR1 Excellent linearity Datasheet

ACPM-7312
UMTS Band5 (824-849MHz) 4x4 Power Amplifier Module
Data Sheet
Description
Features
The ACPM-7312 is
��� a�� fully
������ matched
�������� �������
10-pin ��������
surface ������
mount
module developed for UMTS Band5. This power amplifier
module operates in the 824-849MHz bandwidth. The
ACPM-7312 meets
������ stringent
���������������
UMTS�
����� linearity
���������� requirements
�������������
up to
������������
28�������
.25����
dBm �������
output �������������������
power. The 4�������
��������
mmx����
4���
mm �����
form �������
factor
pa������
ckage is
��� self
����� contained,
����������� incorporating
��������������������
50ohm input
����������
and
output matching networks
•�����
Thin ��������
Package �������
(0.9mm ����
typ)
The ACPM-7312 features 5
�th generation of ��������
CoolPAM ��������
circuit
technology ���������������
which ���������
supports���
��
3 ������
power ������
modes ��–���������
��������
bypass, ����
mid
and high power modes. The CoolPAM is
��� stage
�������������
bypass
technology���������������
enhancing PAE �������������
(power added efficiency)
������������ at
���
low and medium power range. Active bypass feature is
added to 5th generation to enhance PAE further at low
output� range.
������������
This helps
������ to
����������
extend talk
����� time.
�����
The power ����������
amplifier� is
��� manufactured
������������� on
��� an
��� advanced
���������
InGaP HBT (hetero-junction Bipolar Transistor) MMIC
(microwave monolithic integrated circuit) technology
offering state-of-the-art reliability��
�������������, temperature
����������������������
stability
and ruggedness�.
•����������
Excellent ����������
Linearity
•�������
3-mode ������
power �������������
control with ��������
Vbp and �����
Vmode
– Bypass / Mid Power Mode / High Power Mode
•����������������
High Efficiency ���
at ����
max �������
output �����
power
•�������
10-pin ��������
surface ���������
mounting �������
package
•���������������
Internal 50ohm ������������������
matching networks ���������
for both ���
RF ������
input
and output
•Lead-free, RoHS compliant, Green
Applications
•����������
UMTS Band5
Ordering Information�
Part Number
Number of Devices Container
ACPM-7312-TR1
1,000
178mm (7”) Tape/Reel
ACPM-7312-BLK
100
BULK
Block Diagram
Ven(1)
Vcc1(5)
Bias Circuit & Control Logic
Vmode(2)
Vbp(3)
Vcc2(6)
RF In(4)
Inter-Stage
Match
Input Match &
Power Divider
Bypass
Circuit
Output
Match
Impedence
Transformer
RF Out(8)
Absolute Maximum Ratings
No damage assuming only one parameter is set at limit at a time with all other parameters��������
set
�������
at or
�����������������������
below nominal value.
Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal
values may result in permanent damage.
Description
Min.
RF Input Power (Pin)
Typ.
Max.
Unit
0
10*
dBm
DC Supply Voltage (Vcc1, Vcc2)
0
3.4
5.0
V
Enable Voltage (Ven)
0
2.6
3.3
V
Mode Control Voltage (Vmode)
0
2.6
3.3
V
Bypass Control (Vbp)
0
2.6
3.3
V
Storage Temperature (Tstg)
-55
25
+125
°C
* High Power Mode (5dBm for Bypass and Mid Power Mode)
Recommended Operating Condition
Description
Min.
Typ.
Max.
Unit
DC Supply Voltage (Vcc1, Vcc2)
3.2
3.4
4.2
V
Low
High
0
1.35
0
2.6
0.5
3.1
V
V
Low
High
0
1.35
0
2.6
0.5
3.1
V
V
Low
High
0
1.35
0
2.6
0.5
3.1
V
V
849
MHz
85
°C
Enable Voltage (Ven)
Mode Control Voltage (Vmode)
Bypass Control Voltage (Vbp)
Operating Frequency (fo)
824
Ambient Temperature (Ta)
-20
25
Operating Logic Table
Power Mode
Ven
Vmode
Vbp
Pout (Rel99)
Pout (HSDPA, HSUPA MPR=0dB)
High Power Mode
High
Low
Low
~ 28.25 dBm
~ 27.25 dBm
Mid Power Mode
High
High
Low
~ 17 dBm
~ 16 dBm
Bypass Mode
High
High
High
~ 8 dBm
~ 7 dBm
Shut Down Mode
Low
Low
Low
–
–
Electrical Characteristics for WCDMA Mode
– Conditions: Vcc = 3.4V, Ven = 2.6V��, ����������
T = 25°C, ����������������
Zin/Zout = 50ohm
– Signal Configuration:������
3GPP (����������������
�����������������
DPCCH + 1DPDCH��)���������
Up-Link
�������� unless
������� specified
���������� otherwise.
����������
Characteristics
Condition
Min.
Typ.
Max.
Unit
824
–
849
MHz
High Power Mode, Pout=28.25dBm
24
27
dB
Mid Power Mode, Pout=17dBm
15
19
dB
Bypass Mode, Pout=8dBm
10
15
18
dB
Operating Frequency Range
Gain
GPS Band Gain relative to Tx Gain, HPM
Ggps@Pin=-15dBm – Gtx@Pout=28.25dBm
-20
-3
dB
Rx Band Gain relative to Tx Gain, HPM
Grx@Pin=-15dBm – Gtx@Pout=28.25dBm
-1.4
-0.5
dB
ISM Band Gain relative to Tx Gain, HPM
Gism@Pin=-15dBm – Gtx@Pout=28.25dBm
-75
-6
dB
Power Added Efficiency
High Power Mode, Pout=28.25dBm
36.7
40.4
%
Mid Power Mode, Pout=17dBm
14.6
20.8
%
Bypass Mode, Pout=8dBm
9
13.8
%
Total Supply Current
High Power Mode, Pout=28.25dBm
485
535
mA
Mid Power Mode, Pout=17dBm
70
100
mA
Bypass Mode, Pout=8dBm
Quiescent Current
Enable Current
Mode Control Current
Bypass Control Current
13
20
mA
High Power Mode
70
90
110
mA
Mid Power Mode
10
20
30
mA
Bypass Mode
2.3
3.3
4.3
mA
High Power Mode
10
25
µA
Mid Power Mode
10
25
µA
Bypass Mode
10
25
µA
Mid Power Mode
5
25
µA
Bypass Mode
5
25
µA
Bypass
5
25
µA
Total Current in Power-down mode
Ven=0V, Vmode=0V, Vbp=0V
5
µA
Adjacent Channel
Leakage Ratio
5 MHz offset
10 MHz offset
High Power Mode, Pout=28.25dBm
-40
-56
-37
-47
dBc
dBc
5 MHz offset
10 MHz offset
High Power Mode, Pout=27.25dBm
(HSDPA, HSUPA MPR=0dB)
-39
-56
-36
-47
dBc
dBc
5 MHz offset
10 MHz offset
Mid Power Mode, Pout=17dBm
-47
-62
-37
-47
dBc
dBc
5 MHz offset
10 MHz offset
Mid Power Mode, Pout=16dBm
(HSDPA, HSUPA MPR=0dB)
-46
-60
-37
-47
dBc
dBc
5 MHz offset
10 MHz offset
Bypass Mode, Pout=8dBm
-49
-57
-37
-47
dBc
dBc
5 MHz offset
10 MHz offset
Bypass Mode, Pout=7dBm
(HSDPA, HSUPA MPR=0dB)
-46
-61
-37
-47
dBc
dBc
Electrical Characteristics for WCDMA Mode
– Conditions: Vcc = 3.4V, Ven = 2.6V��, ����������
T = 25°C, ����������������
Zin/Zout = 50ohm
– Signal Configuration:������
3GPP (����������������
�����������������
DPCCH + 1DPDCH��)���������
Up-Link
�������� unless
������� specified
���������� otherwise.
����������
Characteristics
Condition
Harmonic Suppression
Second
Third
Gain at Harmonics
Second and Third
High Power Mode, Pout=28.25dBm
Input VSWR
Min.
Typ.
Max.
Unit
-37
-64
-35
-40
dBc
dBc
0
dB
1.5
Stability (Spurious Output)
Load VSWR 5:1, All phase
Rx Band Noise Power (Vcc=4.2V)
High Power Mode, Pout=28.25dBm
GPS Band Noise (Vcc=4.2V)
High Power Mode, Pout=28.25dBm
ISM Band Noise (Vcc=4.2V)
Phase Discontinuity
Ruggedness
Pout<28.25dBm & Pin<5dBm, All phase,
High Power Mode
2.5:1
-60
dBc
-135.5
-134
dBm/Hz
-155
-140
dBm/Hz
High Power Mode, Pout=28.25dBm
-159
-144
HPM↔MPM, Pout=17dBm
MPM↔BPM, Pout=8dBm
4
20
45
45
deg
deg
8:1
VSWR
1. HSDPA
- 3GPP TS 34.121-1
- User Equipment (UE) conformance specification; Radio transmission and reception (FDD); Part 1: Conformance specification
- Annex C (normative): Measurement channels
- C.10.1 UL reference measurement channel for HSDPA tests
- Table C.10.1.4: β values for transmitter characteristics tests with HS-DPCCH
- Sub-test 2 (CM=1.0dB, MPR=0.0dB)
2. HSUPA
- 3GPP TS 34.121-1
- User Equipment (UE) conformance specification; Radio transmission and reception (FDD); Part 1: Conformance specification
- Annex C (normative): Measurement channels
- C.11.1 UL reference measurement channel for E-DCH tests
- Table C.11.1.3: β values for transmitter characteristics tests with HS-DPCCH and E-DCH
- Sub-test 1 (CM=1.0dB, MPR=0.0dB)
Footprint
All dimensions are in millimeter
PIN Description
0.40
1.90 1.70
0.40
0.10
0.85
Pin #
Name
Description
1
Ven
PA Enable
2
Vmode
Mode Control
3
Vbp
Bypass Control
4
RFin
RF Input
5
Vcc1
DC Supply Voltage
6
Vcc2
DC Supply Voltage
7
GND
Ground
8
RFout
RF Output
9
GND
Ground
10
GND
Ground
1.90
1.20
X-Ray Top View
Package Dimensions
All dimensions are in millimeter
0.6
Pin 1 Mark
1
10
2
9
3
8
4
7
5
6
4 ± 0.1
4 ± 0.1
0.9 ± 0.1
Marking Specification
Pin 1 Mark
AVAGO
ACPM-7312
Manufacturing Part Number
PYYWW
Lot Number
P
Manufacturing info
YY
Manufacturing Year
WW
Work Week
AAAAA Assembly Lot Number
AAAAA
CoolPAM
Mode control p���
����
ins
Avago Technologies��’���������
��������
CoolPAM ���
is �������������
stage-bypass ���
PA �����
technology�������������
which saves more
����� power
������ compared
��������� with
����� �������
conventional����������
PA. With this
����� technology,
������������ the
������������������
ACPM-7312 has �����
very
low quiescent current, and efficiencies at low and medium
output power ranges are high.
Vmode and Vbp are digitally controlled by baseband and
they control the operating mode of the PA. The operating
logic table is summarized on the page 2. These pins do not
require constant voltage for interface.
Incorporation of bias circuit
T�����������������
he ACPM-7312 has ��������������
internal bias ���������
circuit, which
������ removes
��������
the need for external constant ���������������
voltage source ����������
(LDO)�����
.����
���
PA
on/off is controlled by Ven. This is digitally�
���������� control
�������� pin.
����
UMTS PA performance comparison
– CoolPAM 4 and CoolPAM 5
450
400
350
The ACPM-��������������
7312����������
supports
��������� three
������ ������
power ������
modes ��������
(bypass�
power mode/mid power mode/high power mode��)
with ����
two �����
mode ��������
control �����
pins� �����������
(Vmode and �����������
Vbp). This
control scheme enables the ����������
ACPM-7312 ��������
to �����
save ������
power
consumption more, which accordingly ������
gives ���������
extended
talk time.
Current (mA)
3-mode p���������������������������������������
����������������������������������������
ower c���������������������������������
����������������������������������
ontrol with two mode control pins
Talk time is extended�
��������� more
��������
as ��������
average ��������
current consump��������
tion� is
��� lowered.
��������
250
200
150
50
0
-10
Current (mA)
Average current & Talk time
Average current = ƒ (PDF x Current)dp
300
100
PDF (probability density function) showing distribution
of output power of mobile in real field gives motivation
for stage-bypass PA. Output power is less than 16dBm for
most of operating time (during talking), so it is important
to save power consumption at low and medium output
power ranges.
Average current consumed by PA can be calculated by
summing up current at each output power weighted with
probability. So it is expressed with integration of multiplication of current and probability at each output power.
CP5
CP4
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-10 -8
0
10
Pout(dBm)
20
30
CP5
CP4
-6
-4
-2
0
2 4 6
Pout(dBm)
8
10 12 14 16
Icc Comparison of CP5 to CP4 (Avago CoolPAM)
The 5th generation of CoolPAM technology, ACPM-7312
can dramatically reduce Icc down to 3mA at bypass mode,
which improves overall talk time and battery usage time
of handset more compared with the CP4.
Figure 1. PDF and Current
Application on mobile phone board
PCB layout and part placement on phone board
Application example in mobile is shown below. C4 and C5
should be placed close to pin1 and pin10. Bypass cap C1,
C2 and C3 should be also placed nearby from pin5, pin4
and pin3, respectively. The length of post-PA transmission
line should be minimized to reduce line loss.
Peripheral Circuits
BB
PA_ON
C1
C2
C3
ACPM-7312
C9
Ven
Vmode
Vbp
IN
Vc1
output matching circuit
C8
GND
GND
OUT
GND
Vcc2
C7
C4
C5
C6
VBATT
Via hole
PCB guideline on phone board
PA_R1
TX filter
1
2
4
PA_R0
RF In
3
Coupler
L1
RF Out
Note
1. To prevent ��������������
voltage ������
drop, �����
make ���������
the bias ������
lines ���
as ��������
wide as ���������
p��������
ossible ������
(�����
P����
ink
line).
2. Use many via�������
hole��s ���
to ������
fence �������
off PA ���
RF ����������
in��������
put and �������
out����
put �������
traces ����
for
better i������������������������
solation. ��������������
O�������������
utput signal� ���
of ��������������
the PA��������
should ���
be ���������
isolated �����
from
input �����������
signal and ����
the �������������������������������������
receive signal�����������������������
. Output signal should �������
not be ����
fed
into PA input. (Green line)
3. Use via�������
hole��s ���
to ��������
connect ������
outer ground
������� plates�
������� to
��� internal
��������� ground
�������
plane��������
s�������
. �����
They �����������������
help ������������
heat spread ����
out more
������������
easily and
���� accordingly
������������ the
����
board temperature can be lowered. �����
T����
hey ����������
also �����
help� ���
to ��������
improve ���
RF
stability (���������������
Y��������������
ellow square).
4. PA which has a ground slug requires many via holes which go through
all the layers (Red square).
Metallization
0.6
PCB Design Guidelines
The recommended PCB l����
�����
and ��������
pattern ���
is ������
shown� in
��� ��������
figures
on the left side����������������
. The substrate is
��� coated
������� with
������������
solder mask
�����
between the I/O and conductive paddle to protect the
gold pads from short circuit that is caused by solder
bleeding/bridging.
0.1
0.4
Stencil Design Guidelines
A properly designed solder screen or stencil is required
to ensure optimum amount of solder paste is deposited
onto the PCB pads.
0.85
0.25
The recommended stencil layout is shown here��
������. Reducing
���������
the stencil opening can potentially generate more voids.
On the other hand, stencil openings larger than 100% will
lead to �����������������
e����������������
xcessive solder ������������
paste smear �������������������
or bridging across
the I/O pads or conductive paddle to adjacent I/O pads.
Considering the fact that solder paste thickness will
directly affect the quality of the solder joint, a good choice
is to use laser cut stencil composed of 0.100mm(4mils) or
0.127mm(5mils)� ����������������
thick stainless steel
������������
which is
��� capable
�������� of
���
producing the required fine stencil outline.
0.5
Ø0.3mm
on 0.6mm pitch
Solder Mask Opening
0.7
0.55
0.5
1.8
0.85
2.4
Solder Paste Stencil Aperture
0.6
0.5
0.4
1.6
0.85
2.0
Evaluation Board Schematic
Ven
Vbp
C1
100pF
C2
100pF
RF in
C3
100pF
Vmode
1 Ven
2 Vmode
Vcc1
C4
680pF
C5
2.2uF
GND 10
3 Vbp
RF out 8
4 RF in
GND 7
5 Vcc1
Vcc2 6
Evaluation Board Description
C1
C2
C5
C4
AVAGO
ACPM-7312
PYYWW
AAAAA
C5
C6
C7
C5
GND 9
C7
RF out
Vcc2
C6
680pF
C7
2.2uF
Tape and Reel Information
AVAGO
ACPM-7312
PYYWW
AAAAA
Dimension List
Annote
Millimeter
Annote
Millimeter
A0
4.40±0.10
P2
2.00±0.05
B0
4.40±0.10
P10
40.00±0.20
K0
1.70±0.10
E
1.75±0.10
D0
1.55±0.05
F
5.50±0.05
D1
1.60±0.10
W
12.00±0.30
P0
4.00±0.10
T
0.30±0.05
P1
8.00±0.10
Tape and Reel Format – 4 mm x 4 mm.
10
Reel Drawing
BACK VIEW
Shading indicates
thru slots
18.4 max.
178 +0.4
-0.2
50 min.
25
min wide (ref)
Slot for carrier tape
insertion for attachment
to reel hub (2 places 180° apart)
12.4 +2.0
-0.0
FRONT VIEW
1.5 min.
13.0 ± 0.2
21.0 ± 0.8
Plastic Reel Format (all dimensions are in millimeters)
11
NOT��S:
1. �ee� ��h���� be ���be�e�� w��h �he �����w����
�������������� ����� �� ����������.
��. �������������e��� �����e �� �����b��
b. Av���� Te�h�������e�� ����� ����be�
�. ����h����e ����e� ����be�
��. �����e ����e
e. ����������� �� �������
2. A �e��� ����e �� �����������e �� �� ��� ��h����
be ������e�� ������ ������������� e���h ��h���e���
�� ��������.
3. �ee� ����� ���� be �����e w��h �� ����������
�z���e ��e��e����� ����e�������.
4. A�� ����e���������� ��� ������e�e��� �����
Handling and Storage
ESD (Electrostatic Discharge)
Electrostatic discharge occurs naturally in the environment. With the increase in voltage potential, the outlet of
neutralization or discharge will be sought. If the acquired
discharge route is through a semiconductor device, destructive damage will result.
The out of bag exposure time maximum limits are determined by the classification test describe below which
corresponds to a MSL classification level 6 to 1 according
to the JEDEC standard IPC/JEDEC J-STD-020B and J-STD033.
ESD countermeasure methods should be developed and
used to control potential ESD damage during handling in
a factory environment at each manufacturing site.
ACPM-7312 is MSL3. Thus, according to the J-STD-033
p.11 the maximum Manufacturers Exposure Time (MET)
for this part is 168 hours. After this time period, the part
would need to be removed from the reel, de-taped and
then re-baked. MSL classification reflow temperature for
the ACPM-7312 is targeted at 260°C +0/-5°C. Figure and
table on next page show typical SMT profile for maximum
temperature of 260 +0/-5°C.
MSL (Moisture Sensitivity Level)
Plastic encapsulated surface mount package is sensitive to
damage induced by absorbed moisture and temperature.
Avago Technologies follows JEDEC Standard J-STD 020B.
Each component and package type is classified for
moisture sensitivity by soaking a known dry package at
various temperatures and relative humidity, and times.
After soak, the components are subjected to three consecutive simulated reflows.
Moisture Classification Level and Floor Life
MSL Level
Floor Life (out of bag) at factory ambient = < 30°C/60% RH or as stated
1
Unlimited at = < 30°C/85% RH
2
1 year
2a
4 weeks
3
168 hours
4
72 hours
5
48 hours
5a
24 hours
6
Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label
Note :
1. The MSL Level is marked on the MSL Label on each shipping bag.
12
Reflow Profile Recommendations
tp
Tp
Critical Zone
TL to Tp
Ramp-up
Temperature
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5°C.
Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5°C
Profile Feature
Sn-Pb Solder
Pb-Free Solder
Average ramp-up rate (TL to TP)
3°C/sec max
3°C/sec max
Preheat
– Temperature Min (Tsmin)
– Temperature Max (Tsmax)
– Time (min to max) (ts)
100°C
150°C
60-120 sec
150°C
200°C
60-180 sec
Tsmax to TL
– Ramp-up Rate
3°C/sec max
Time maintained above:
– Temperature (TL)
– Time (TL)
183°C
60-150 sec
217°C
60-150 sec
Peak temperature (Tp)
240 +0/-5°C
260 +0/-5°C
Time within 5°C of actual Peak Temperature (tp)
10-30 sec
20-40 sec
Ramp-down Rate
6°C/sec max
6°C/sec max
Time 25°C to Peak Temperature
6 min max.
8 min max.
13
Storage Condition
Baking of Populated Boards
Packages described in this document must be stored
in sealed moisture barrier, antistatic bags. Shelf life in a
sealed moisture barrier bag is 12 months at <40°C and
90% relative humidity (RH) J-STD-033 p.7.
Some SMD packages and board materials are not able to
withstand long duration bakes at 125°C. Examples of this
are some FR-4 materials, which cannot withstand a 24 hr
bake at 125°C. Batteries and electrolytic capacitors are
also temperature sensitive. With component and board
temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the
appropriate bake duration based on the component to
be removed. For additional considerations see IPC-7711
andIPC-7721.
Out-of-Bag Time Duration�
After unpacking the device must be soldered to the PCB
within 168 hours as listed in the J-STD-020B p.11 with
factory conditions <30°C and 60% RH.
Baking
It is not necessary to re-bake the part if both conditions
(storage conditions and out-of bag conditions) have been
satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are 125°C for 12 hours J-STD-033 p.8.
CAUTION
Tape and reel materials typically cannot be baked at the
temperature described above. If out-of-bag exposure
time is exceeded, parts must be baked for a longer time
at low temperatures, or the parts must be de-reeled, detaped, re-baked and then put back on tape and reel. (See
moisture sensitive warning label on each shipping bag for
information of baking).
Board Rework
Component Removal, Rework and Remount
If a component is to be removed from the board, it is
recommended that localized heating be used and the
maximum body temperatures of any surface mount
component on the board not exceed 200°C. This method
will minimize moisture related component damage. If any
component temperature exceeds 200°C, the board must
be baked dry per 4-2 prior to rework and/or component
removal. Component temperatures shall be measured at
the top center of the package body. Any SMD packages
that have not exceeded their floor life can be exposed to
a maximum body temperature as high as their specified
maximum reflow temperature.
Removal for Failure Analysis
Not following the above requirements��������������������
�������������������
may cause moisture/
reflow��������
�������
damage �����
that ������
could �������
hinder ���
or� �����������
completely ��������
prevent
the d�������������
��������������
etermination of
��� the
���� original
��������� failure�
�������� mechanism.
����������
14
Derating due to Factory Environmental Conditions
Factory floor life exposures for SMD packages removed
from the dry bags will be a function of the ambient environmental conditions. A safe, yet conservative, handling
approach is to expose the SMD packages only up to the
maximum time limits for each moisture sensitivity level
as shown in next table. This approach, however, does not
work if the factory humidity or temperature is greater
than the testing conditions of 30°C/60% RH. A solution
for addressing this problem is to derate the exposure
times based on the knowledge of moisture diffusion in
the component package materials ref. JESD22-A120).
Recommended equivalent total floor life exposures can
be estimated for a range of humidities and temperatures
based on the nominal plastic thickness for each device.
Table on next page lists equivalent derated floor lives for
humidities ranging from 20-90% RH for three temperature, 20°C, 25°C, and 30°C.
Table on next page is applicable to SMDs molded
with novolac, biphenyl or multifunctional epoxy mold
compounds. The following assumptions were used in calculating this table:
1. Activation Energy for diffusion = 0.35eV (smallest
known value).
2. For ≤60% RH, use Diffusivity = 0.121exp (-0.35eV/kT)
mm2/s (this used smallest known Diffusivity @ 30°C).
3. For >60% RH, use Diffusivity = 1.320exp (-0.35eV/kT)
mm2/s (this used largest known�������������
Diffusivity
������������ @
��������
30°C).
Recommended Equivalent Total Floor Life (days) @ 20°C, 25°C & 30°C, 35°C
For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was
classified) Maximum Percent Relative Humidity
Maximum Percent Relative Humidity
Package Type and
Moisture Sensitivity
Body Thickness
Level
Body Thickness ≥3.1 mm
Including PQFPs >84 pin,
PLCCs (square)
All MQFPs
or
All BGAs ≥1 mm
Level 2a
Level 3
Level 4
Level 5
Level 5a
Body 2.1 mm
≤ Thickness
<3.1 mm including
PLCCs (rectangular)
18-32 pin
SOICs (wide body)
SOICs ≥20 pins,
PQFPs ≤80 pins
Level 2a
Level 3
Level 4
Level 5
Level 5a
Body Thickness <2.1 mm
including SOICs <18 pin
All TQFPs, TSOPs
or
All BGAs <1 mm body
thickness
Level 2a
Level 3
Level 4
Level 5
Level 5a
15
5%
10%
20%
30%
40%
50%
60%
70%
80%
90%
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
3
5
6
8
2
4
5
7
1
2
3
5
∞
∞
∞
∞
∞
∞
∞
∞
5
7
9
11
3
4
5
6
1
2
2
3
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
7
10
13
18
94
124
167
231
8
10
13
17
3
4
5
7
2
3
5
7
1
1
2
4
∞
∞
∞
∞
12
19
25
32
4
5
7
9
2
3
4
5
1
1
2
2
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
7
13
18
26
2
3
5
6
44
60
78
103
7
9
11
14
3
4
5
7
2
3
4
6
1
1
2
3
∞
∞
∞
∞
9
12
15
19
3
4
5
7
2
3
3
5
1
1
2
2
∞
∞
∞
∞
∞
∞
∞
∞
7
9
12
17
3
5
6
8
1
2
3
4
32
41
53
69
6
8
10
13
2
4
5
7
2
2
4
5
1
1
2
3
58
86
148
∞
7
9
12
15
3
4
5
6
2
2
3
4
1
1
2
2
∞
∞
∞
∞
∞
∞
∞
∞
4
5
7
9
2
3
4
6
1
1
2
3
26
33
42
57
6
7
9
12
2
3
5
7
1
2
3
5
1
1
2
3
30
39
51
69
6
8
10
13
2
3
4
6
2
2
3
4
1
1
2
2
∞
∞
∞
∞
8
11
14
20
3
4
5
7
2
2
3
5
1
1
2
2
16
28
36
47
6
7
9
12
2
3
4
6
1
2
3
4
1
1
2
2
22
28
37
49
5
7
9
12
2
3
4
5
1
2
3
4
1
1
2
2
17
28
∞
∞
5
7
10
13
2
3
4
6
1
2
3
4
1
1
2
2
7
10
14
19
4
5
7
10
2
3
3
5
1
2
2
3
1
1
1
2
3
4
6
8
2
3
5
7
1
2
3
4
1
1
2
3
1
1
1
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
1
2
5
7
10
13
3
4
6
8
1
2
3
4
1
1
2
3
1
1
1
2
2
3
4
5
2
2
3
5
1
2
2
3
1
1
1
3
0.5
0.5
1
2
0.5
1
1
2
0.5
1
1
2
0.5
1
1
2
0.5
1
1
2
0.5
1
1
2
4
6
8
10
3
4
5
7
1
2
3
4
1
1
2
3
1
1
1
2
1
2
3
4
1
2
3
4
1
1
2
3
1
1
1
2
0.5
0.5
1
1
0.5
1
1
1
0.5
1
1
1
0.5
1
1
1
0.5
1
1
1
0.5
0.5
1
1
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
35°C
30°C
25°C
20°C
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved.
AV02-1945EN - May 29, 2009
Similar pages