AD ADA4530-1ARZ-RL Femtoampere input bias current electrometer amplifier Datasheet

Femtoampere Input Bias Current
Electrometer Amplifier
ADA4530-1
Data Sheet
FEATURES
PIN CONNECTION DIAGRAM
+IN 1
8
–IN
GRD 2
7
GRD
IC 3
6
OUT
V– 4
5
V+
NOTES
1. IC = INTERNAL CONNECTION. THIS
PIN MUST BE CONNECTED TO V–
OR LEFT UNCONNECTED.
13405-001
ADA4530-1
Low input bias current
±20 fA maximum at TA = 25°C (guaranteed at production test)
± 20 fA maximum at −40°C < TA < +85°C
± 250 fA maximum at −40°C < TA < +125°C (guaranteed at
production test)
Low offset voltage: 50 μV maximum over specified CMRR range
Offset drift: 0.13 μV/°C typical, 0.5 μV/°C maximum
Integrated guard buffer with 100 μV maximum offset
Low voltage noise density: 14 nV/√Hz at 10 kHz
Wide bandwidth: 2 MHz unity-gain crossover
Supply voltage: 4.5 V to 16 V (±2.25 V to ±8 V)
Operating temperature: −40°C to +125°C
Figure 1.
APPLICATIONS
Laboratory and analytical instrumentation:
spectrophotometers, chromatographs, mass
spectrometers, and potentiostatic and amperostatic
coulometry
Instrumentation: picoammeters and coulombmeters
Transimpedance amplifier (TIA) for photodiodes, ion
chambers, and working electrode measurements
High impedance buffering for chemical sensors and
capacitive sensors
GENERAL DESCRIPTION
The ADA4530-1 also offers low offset voltage, low offset drift,
and low voltage and current noise needed for the types of
applications that require such low leakages. To maximize the
dynamic range of the system, the ADA4530-1 has a rail-to-rail
Rev. A
The ADA4530-1 operates over the −40°C to +125°C industrial
temperature range and is available in an 8-lead SOIC package.
1000
–40°C TO +125°C LIMIT
VSY = 10V
VCM = VSY/2
RH < 10%
100
–40°C TO +85°C LIMIT
10
1
0.1
IB+
IB–
0.01
0.001
0
10
20
30
40
50
60
70
80
90 100 110 120 130
TEMPERATURE (°C)
13405-202
It provides ultralow input bias currents that are production
tested at temperature to ensure the device meets its performance goals in user systems. The integrated guard buffer is
provided to isolate the input pins from leakage in the printed
circuit board (PCB), minimize board component count, and
enable ease of system design. The ADA4530-1 is available in an
industry-standard surface-mount 8-lead SOIC package with a
unique pinout optimized to prevent signals from coupling
between the sensitive input pins, the power supplies, and the
output pin while enabling easy routing of the guard ring traces.
output stage that can typically drive to within 30 mV of the
supply rails under a 10 kΩ load.
IB (fA)
The ADA4530-1 is a femtoampere (10−15 A) level input bias
current operational amplifier suitable for use as an electrometer
that also includes an integrated guard buffer. It has an operating
voltage range of 4.5 V to 16 V enabling it to operate in conventional 5 V and 10 V single supply systems as well as ±2.5 V and
±5 V dual supply systems.
Figure 2. Input Bias Current (IB) vs. Temperature, VSY = 10 V
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADA4530-1* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
Reference Materials
View a parametric search of comparable parts
Press
• Electrometer-Grade Amplifier Improves Accuracy While
Reducing Size of Chemical Analysis Instruments
Evaluation Kits
• ADA4530-1 Evaluation Board
Documentation
Application Notes
• AN-1373: ADA4530-1 Femtoampere Level Input Bias
Current Measurement
User Guides
• UG-865: ADA4530-1 8-Lead SOIC Package Evaluation
Board
Design Resources
•
•
•
•
ADA4530-1 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
Discussions
View all ADA4530-1 EngineerZone Discussions
Tools and Simulations
Sample and Buy
• ADA4530 SPICE Macro-Model
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
ADA4530-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Bias Current ...................................................................... 32
Applications ....................................................................................... 1
Input Resistance.......................................................................... 33
Pin Connection Diagram ................................................................ 1
Input Offset Voltage ................................................................... 33
General Description ......................................................................... 1
Insulation Resistance ................................................................. 33
Revision History ............................................................................... 2
Guarding ...................................................................................... 34
Specifications..................................................................................... 3
Dielectric Relaxation.................................................................. 34
5 V Nominal Electrical Characteristics ..................................... 3
Humidity Effects......................................................................... 36
10 V Nominal Electrical Characteristics ................................... 5
Contamination............................................................................ 37
15 V Nominal Electrical Characteristics ................................... 7
Cleaning and Handling ............................................................. 38
Absolute Maximum Ratings............................................................ 9
Solder Paste Selection ................................................................ 38
Thermal Resistance ...................................................................... 9
Current Noise Considerations ...................................................... 39
ESD Caution .................................................................................. 9
Layout Guidelines ........................................................................... 42
Pin Configuration and Function Descriptions ........................... 10
Physical Implementation of Guarding Techniques................ 42
Typical Performance Characteristics ........................................... 11
Guard Ring .................................................................................. 42
Main Amplifier, DC Performance ............................................ 11
Guard Plane................................................................................. 42
Main Amplifier, AC Performance ............................................ 20
Via Fence ..................................................................................... 43
Guard Amplifier ......................................................................... 26
Cables and Connectors .............................................................. 43
Theory of Operation ...................................................................... 28
Electrostatic Interferance .......................................................... 43
ESD Structure.............................................................................. 28
Photodiode Interface...................................................................... 44
Input Stage ................................................................................... 28
DC Error Analysis ...................................................................... 44
Gain Stage .................................................................................... 29
AC Error Analysis ...................................................................... 44
Output Stage ................................................................................ 29
Noise Analysis ............................................................................. 45
Guard Buffer ............................................................................... 29
Design Recommendations ........................................................ 46
Applications Information .............................................................. 30
Design Example .......................................................................... 46
Input Protection.......................................................................... 30
Power Supply Recommendations ................................................. 49
Single-Supply and Rail-to-Rail Output ................................... 30
Power Supply Considerations ................................................... 49
Capacitive Load Stability ........................................................... 30
Outline Dimensions ....................................................................... 50
EMI Rejection Ratio ................................................................... 31
Ordering Guide .......................................................................... 50
High Impedance Measurements ................................................... 32
REVISION HISTORY
3/16—Rev. 0 to Rev. A
Changed DNC Pin to IC Pin ........................................ Throughout
Changes to Figure 1 .......................................................................... 1
Changes to Figure 3 and Table 6 ................................................... 10
Changes to Figure 29 ...................................................................... 15
Changes to Theory of Operation Section .................................... 28
Changes to Humidity Effects Section and Figure 112 ............... 36
Added Power Supply Recommendations Section, Power
Supply Considerations Section, Table 16, and Figure 133 to
Figure 135 ........................................................................................ 49
10/15—Revision 0: Initial Version
Rev. A | Page 2 of 50
Data Sheet
ADA4530-1
SPECIFICATIONS
5 V NOMINAL ELECTRICAL CHARACTERISTICS
VSY = 4.5 V, VCM = VSY/2, TA = 25°C, unless otherwise specified. Typical specifications are equal to the average of the distribution from
characterization, unless otherwise noted. Minimum and maximum specifications are tested in production, unless otherwise noted.
Table 1.
Parameter1
INPUT CHARACTERISTICS
Input Bias Current2, 3
Symbol
Test Conditions/Comments
IB
RH < 50%
−40°C < TA < +85°C, RH < 50%
−40°C < TA < +125°C, RH < 50%
RH < 50%
−40°C < TA < +125°C, RH < 50%
Input Offset Current3
IOS
Offset Voltage2, 4
VOS
Offset Voltage Drift2, 4
ΔVOS/ΔT
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
Large Signal Voltage Gain
AVO
Input Resistance
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage High
RIN
CIN
Output Voltage Low
Short-Circuit Current
Source
Sink
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current
VOH
VOL
Min
RL = 10 kΩ to VCM
−40°C < TA < +125°C
RL = 2 kΩ to VCM
−40°C < TA < +125°C
RL = 10 kΩ to VCM
−40°C < TA < +125°C
RL = 2 kΩ to VCM
−40°C < TA < +125°C
Max
Unit
<1
±20
±20
±250
±20
±150
±40
±50
±70
±150
±300
±0.5
±2.8
3
fA
fA
fA
fA
fA
μV
μV
μV
μV
μV
μV/°C
μV/°C
V
dB
dB
dB
dB
dB
TΩ
pF
<1
+8
+9
VCM = 1.5 V to 3 V
VCM = 1.5 V to 3 V, 0°C < TA < 125°C
VCM = 1.5 V to 3 V, −40°C < TA < 0°C
VCM = 0 V to 3 V
0°C < TA < 125°C
−40°C < TA < 0°C
VCM = 1.5 V to 3 V
−40°C < TA < +125°C
VCM = 0 V to 3 V
RL = 2 kΩ to VCM, VOUT = 0.2 V to 4.3 V
−40°C < TA < +125°C
−40°C < TA < +125°C
Typ
+0.13
−0.7
0
92
90
73
120
120
114
143
>100
8
4.47
4.46
4.4
4.38
4.49
4.45
10
30
30
40
100
120
V
V
V
V
mV
mV
mV
mV
ISC
ZOUT
f = 1 MHz, AV = 1
PSRR
VSY = 4.5 V to 16 V
−40°C < TA < +125°C
IOUT = 0 mA
−40°C < TA < +125°C
ISY
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
SR
GBP
Unity-Gain Crossover
UGC
−3 dB Closed-Loop Bandwidth
f−3dB
RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 100
VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
VIN=10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 1
Rev. A | Page 3 of 50
130
130
15
−30
20
mA
mA
Ω
150
dB
dB
mA
mA
0.9
1.3
1.5
1.4
2
V/μs
MHz
2
MHz
6
MHz
ADA4530-1
Parameter1
Phase Margin
Data Sheet
Symbol
ΦM
Settling Time to 0.1%
tS
EMI Rejection Ratio of +IN
EMIRR
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise
Voltage Noise Density
eN p-p
eN
Current Noise Density
Total Harmonic Distortion + Noise
Bandwidth = 90 kHz
Bandwidth = 500 kHz
GUARD BUFFER
Guard Offset Voltage2, 4, 5
IN
THD + N
VGOS
Guard Offset Voltage Drift2, 4
ΔVGOS/ΔT
Output Impedance
Output Voltage Range
−3 dB Bandwidth
ZGOUT
f−3dBGUARD
Test Conditions/Comments
VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
VIN = 0.5 V step, RL = 10 kΩ, CL= 10 pF,
AV = −1
VIN = 100 mV peak, f = 400 MHz
VIN = 100 mV peak, f = 900 MHz
VIN = 100 mV peak, f = 1800 MHz
VIN = 100 mV peak, f = 2400 MHz
Min
f = 0.1 Hz to 10 Hz
f = 10 Hz
f = 1 kHz
f = 10 kHz
f = 0.1 Hz
AV = 1, f = 1 kHz, VIN = 0.5 V rms
VCM = 1.5 V to 3 V
VCM = 1.5 V to 3 V, 0°C < TA < 125°C
VCM = 1.5 V to 3 V, −40°C < TA < 0°C
VCM = 0.1 V to 3 V
0°C < TA < +125°C
−40°C < TA < 0°C
VGOS < 150 μV
VIN = 10 mV rms, CL = 10 pF
1
Typ
62
Max
5
μs
50
60
80
90
dB
dB
dB
dB
4
80
16
14
0.07
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
0.003
0.0045
%
%
15
0.18
1.4
1
0.1
100
120
250
150
1
7
3
5.5
These specifications represent the performance for 5 V ± 10% power supplies. All specifications are measured at the worst case 4.5 V supply voltage.
The maximum specifications at −40°C < TA < +85°C and −40°C < TA < 0°C are guaranteed from characterization.
3
RH is relative humidity (see the Humidity Effects section for more information).
4
The typical specifications are equal to the average plus the standard deviation of the distribution from characterization.
5
The guard offset voltage is the voltage difference between the guard output and the noninverting input.
2
Rev. A | Page 4 of 50
Unit
Degrees
μV
μV
μV
μV
μV/°C
μV/°C
kΩ
V
MHz
Data Sheet
ADA4530-1
10 V NOMINAL ELECTRICAL CHARACTERISTICS
VSY = 10 V, VCM = VSY/2, TA = 25°C, unless otherwise noted. Typical specifications are equal to the average of the distribution from
characterization, unless otherwise noted. Minimum and maximum specifications are tested in production, unless otherwise noted.
Table 2.
Parameter1
INPUT CHARACTERISTICS
Input Bias Current2, 3
Symbol
Test Conditions/Comments
IB
RH < 50%
−40°C < TA < +85°C, RH < 50%
−40°C < TA < +125°C, RH < 50%
RH < 50%
−40°C < TA < +125°C, RH < 50%
Input Offset Current3
IOS
Offset Voltage2, 4
VOS
Offset Voltage Drift2, 4
ΔVOS/ΔT
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
Large Signal Voltage Gain
AVO
Input Resistance
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage High
RIN
CIN
Output Voltage Low
Short-Circuit Current
Source
Sink
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current
VOH
VOL
Min
RL = 10 kΩ to VCM
−40°C < TA < +125°C
RL = 2 kΩ to VCM
−40°C < TA < +125°C
RL = 10 kΩ to VCM
−40°C < TA < +125°C
RL = 2 kΩ to VCM
−40°C < TA < +125°C
Max
Unit
<1
±20
±20
±250
±20
±150
±40
±50
±70
±150
±300
±0.5
±2.8
8.5
fA
fA
fA
fA
fA
μV
μV
μV
μV
μV
μV/°C
μV/°C
V
dB
dB
dB
dB
dB
TΩ
pF
<1
+8
+9
VCM = 1.5 V to 8.5 V
VCM = 1.5 V to 8.5 V, 0°C < TA < 125°C
VCM = 1.5 V to 8.5 V, −40°C < TA < 0°C
VCM = 0 V to 8.5 V
0°C < TA < 125°C
−40°C < TA < 0°C
VCM = 1.5 V to 8.5 V
−40°C < TA < +125°C
VCM = 0 V to 8.5 V
RL = 2 kΩ to VCM, VOUT = 0.5 V to 9.5 V
−40°C < TA < +125°C
−40°C < TA < +125°C
Typ
+0.13
−0.7
0
105
100
87
125
125
114
150
>100
8
9.96
9.94
9.93
9.75
9.97
9.87
15
70
40
60
170
250
V
V
V
V
mV
mV
mV
mV
ISC
ZOUT
f = 1 MHz, AV = 1
PSRR
VSY = 4.5 V to 16 V
−40°C < TA < +125°C
IOUT = 0 mA
−40°C < TA < +125°C
ISY
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
SR
GBP
Unity-Gain Crossover
UGC
−3 dB Closed-Loop Bandwidth
f−3dB
Phase Margin
ΦM
RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 100
VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 1
VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
Rev. A | Page 5 of 50
130
130
15
−30
20
mA
mA
Ω
150
dB
dB
mA
mA
0.9
1.3
1.5
1.4
2
V/μs
MHz
2
MHz
6
MHz
62
Degrees
ADA4530-1
Parameter1
Settling Time to 0.1%
Data Sheet
Symbol
tS
EMI Rejection Ratio of +IN
EMIRR
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise
Voltage Noise Density
eN p-p
eN
Current Noise Density
Total Harmonic Distortion + Noise
Bandwidth = 90 kHz
Bandwidth = 500 kHz
GUARD BUFFER
Guard Offset Voltage2, 4, 5
IN
THD + N
VGOS
Guard Offset Voltage Drift2, 4
ΔVGOS/ΔT
Output Impedance
Output Voltage Range
−3 dB Bandwidth
ZGOUT
f−3dBGUARD
Test Conditions/Comments
VIN = 1 V step, RL = 10 kΩ, CL = 10 pF,
AV = −1
VIN = 100 mV peak, f = 400 MHz
VIN = 100 mV peak, f = 900 MHz
VIN = 100 mV peak, f = 1800 MHz
VIN = 100 mV peak, f = 2400 MHz
Min
f = 0.1 Hz to 10 Hz
f = 10 Hz
f = 1 kHz
f = 10 kHz
f = 0.1 Hz
AV = 1, f = 1 kHz, VIN = 2 V rms
VCM = 1.5 V to 8.5 V
VCM = 1.5 V to 8.5 V, 0°C < TA < 125°C
VCM = 1.5 V to 8.5 V, −40°C < TA < 0°C
VCM = 0.1 V to 8.5 V
0°C < TA < 125°C
−40°C < TA < 0°C
VGOS < 150 μV
VIN = 10 mV rms, CL = 10 pF
1
Typ
6
Rev. A | Page 6 of 50
Unit
μs
50
60
80
90
dB
dB
dB
dB
4
80
16
14
0.07
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
0.0015
0.0025
%
%
15
0.18
1.4
1
0.1
100
120
250
150
1
7
8.5
5.5
These specifications represent the performance for 10 V ± 10% power supplies. All specifications are measured at the 10 V supply voltage.
The maximum specifications at −40°C < TA < +85°C and −40°C < TA < 0°C are guaranteed from characterization.
3
RH is relative humidity (see the Humidity Effects section for more information).
4
These typical specifications are equal to the average plus the standard deviation of the distribution from characterization.
5
The guard offset voltage is the voltage difference between the guard output and the noninverting input.
2
Max
μV
μV
μV
μV
μV/°C
μV/°C
kΩ
V
MHz
Data Sheet
ADA4530-1
15 V NOMINAL ELECTRICAL CHARACTERISTICS
VSY = 16 V, VCM = VSY/2, TA = 25°C, unless otherwise noted. Typical specifications are equal to the average of the distribution from
characterization, unless otherwise noted. Minimum and maximum specifications are tested in production, unless otherwise noted.
Table 3.
Parameter1
INPUT CHARACTERISTICS
Input Bias Current2, 3
Symbol
Test Conditions/Comments
IB
RH < 50%
−40°C < TA < +85°C, RH < 50%
−40°C < TA < +125°C, RH < 50%
RH < 50%
−40°C < TA < +125°C, RH < 50%
Input Offset Current
IOS
Offset Voltage2, 4
VOS
Offset Voltage Drift2, 4
ΔVOS/ΔT
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
Large Signal Voltage Gain
AVO
Input Resistance
Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage High
RIN
CIN
Output Voltage Low
Short-Circuit Current
Source
Sink
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current
VOH
VOL
Min
RL = 10 kΩ to VCM
−40°C < TA < +125°C
RL = 2 kΩ to VCM
−40°C < TA < +125°C
RL = 10 kΩ to VCM
−40°C < TA < +125°C
RL = 2 kΩ to VCM
−40°C < TA < +125°C
Max
Unit
<1
±20
±20
±250
±20
±150
±40
±50
±70
±150
±300
±0.5
±2.8
14.5
fA
fA
fA
fA
fA
μV
μV
μV
μV
μV
μV/°C
μV/°C
V
dB
dB
dB
dB
dB
TΩ
pF
<1
+8
+9
VCM = 1.5 V to 14.5 V
VCM = 1.5 V to 14.5 V, 0°C < TA < 125°C
VCM = 1.5 V to 14.5 V, −40°C < TA < 0°C
VCM = 0 V to 14.5 V
0°C < TA < 125°C
−40°C < TA < 0°C
VCM = 1.5 V to 14.5 V
−40°C < TA < +125°C
VCM = 0 V to 14.5 V
RL = 2 kΩ to VCM, VOUT = 0.5 V to 15.5 V
−40°C < TA < +125°C
−40°C < TA < +125°C
Typ
+0.13
−0.7
0
110
105
93
130
125
114
155
>100
8
15.93
15.9
15.72
15.58
15.95
15.78
25
115
70
100
280
420
V
V
V
V
mV
mV
mV
mV
ISC
ZOUT
f = 1 MHz, AV = 1
PSRR
VSY = 4.5 V to 16 V
−40°C < TA < +125°C
IOUT = 0 mA
−40°C < TA < +125°C
ISY
DYNAMIC PERFORMANCE
Slew Rate
Gain bandwidth Product
SR
GBP
Unity-Gain Crossover
UGC
−3 dB Closed-Loop Bandwidth
f−3 dB
Phase Margin
ΦM
RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 100
VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 1
VIN =10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
Rev. A | Page 7 of 50
130
130
15
−30
20
mA
mA
Ω
150
dB
dB
mA
mA
0.9
1.3
1.5
1.4
2
V/μs
MHz
2
MHz
6
MHz
62
Degrees
ADA4530-1
Parameter1
Settling Time to 0.1%
EMI Rejection Ratio of +IN
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion + Noise
Bandwidth = 90 kHz
Bandwidth = 500 kHz
GUARD BUFFER
Guard Offset Voltage4, 5
Data Sheet
Symbol
tS
EMIRR
Test Conditions/Comments
VIN = 1 V step, RL = 10 kΩ, CL = 10 pF,
AV = −1
VIN = 100 mV peak, f = 400 MHz
VIN = 100 mV peak, f = 900 MHz
VIN = 100 mV peak, f = 1800 MHz
VIN = 100 mV peak, f = 2400 MHz
eN p-p
eN
eN
eN
IN
THD + N
f = 0.1 Hz to 10 Hz
f = 10 Hz
f = 1 kHz
f = 10 kHz
f = 0.1 Hz
AV = 1, f = 1 kHz, VIN = 4.5 V rms
VGOS
Guard Offset Voltage Drift2, 4
ΔVGOS/ΔT
Output Impedance
Output Voltage Range
−3 dB Bandwidth
ZGOUT
f−3 dB GUARD
Min
VCM = 1.5 V to 14.5 V
VCM = 1.5 V to 14.5 V, 0°C < TA < 125°C
VCM = 1.5 V to 14.5 V, −40°C < TA < 0°C
VCM = 0.1 V to 14.5 V
0°C < TA < +125°C
−40°C < TA < 0°C
VGOS < 150 μV
VIN = 10 mV rms, CL = 10 pF
1
Typ
6
Max
50
60
80
90
dB
dB
dB
dB
4
80
16
14
0.07
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
0.0012
0.003
%
%
15
0.18
1.4
1
0.1
100
120
250
150
1
7
14.5
5.5
These specifications represent the performance for 15 V ± 1 V power supplies. All specifications are measured at the worst case 16 V supply voltage.
The maximum specifications at −40°C < TA < +85°C and −40°C < TA < 0°C are guaranteed from characterization.
3
RH is relative humidity (see the Humidity Effects section for more information).
4
These typical specifications are equal to the average plus the standard deviation of the distribution from characterization.
5
The guard offset voltage is the voltage difference between the guard output and the noninverting input.
2
Rev. A | Page 8 of 50
Unit
μs
μV
μV
μV
μV
μV/°C
μV/°C
kΩ
V
MHz
Data Sheet
ADA4530-1
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
ESD
Human Body Model2
Field Induced Charged Device
Model (FICDM)3
Rating
17 V
(V−) − 0.3 V to (V+) + 0.3 V
10 mA
±0.7 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages using a
standard 4-layer JEDEC board.
Table 5. Thermal Resistance
4 kV
1.25 kV
Package Type
8-Lead SOIC
1
The input pins have clamp diodes to the power supply pins. Limit the input
current to 10 mA or less whenever input signals exceed the power supply
rail by 0.3 V.
2
Applicable Standard ESDA/JEDEC JS-001-2012.
3
Applicable Standard JESD22-C101-E (ESD FICDM standard of JEDEC).
ESD CAUTION
Rev. A | Page 9 of 50
θJA
122
θJC
41
Unit
°C/W
ADA4530-1
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
+IN 1
8
–IN
GRD 2
7
GRD
IC 3
6
OUT
V– 4
5
V+
NOTES
1. IC = INTERNAL CONNECTION. THIS
PIN MUST BE CONNECTED TO V–
OR LEFT UNCONNECTED.
13405-003
ADA4530-1
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
+IN
GRD
IC
V−
V+
OUT
GRD
−IN
Description
Noninverting Input.
Guard.
Internal Connection. This pin must be connected to V− or left unconnected.
Negative Supply Voltage.
Positive Supply Voltage.
Output.
Guard.
Inverting Input.
Rev. A | Page 10 of 50
Data Sheet
ADA4530-1
TYPICAL PERFORMANCE CHARACTERISTICS
MAIN AMPLIFIER, DC PERFORMANCE
TA = 25°C, unless otherwise noted.
100
80
VSY = 4.5V
VCM = VSY/2
590 CHANNELS
x = 2.31µV
σ = 5.48µV
90
70
40
60
VOS (µV)
NUMBER OF AMPLIFIERS
80
VSY = 4.5V
VCM = VSY/2
574 CHANNELS
60
50
40
30
20
0
–20
20
VOS (µV)
–60
–50
13405-004
36
40
24
28
32
12
16
20
0
4
8
–12
–8
–4
–24
–20
–16
–36
–32
–28
–40
0
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 7. Input Offset Voltage (VOS) vs. Temperature, VSY = 4.5 V
Figure 4. Input Offset Voltage Distribution, VSY = 4.5 V
80
100
VSY = 10V
VCM = VSY/2
590 CHANNELS
x = 2.27µV
σ = 5.45µV
90
80
70
VSY = 10V
VCM = VSY/2
574 CHANNELS
60
40
60
VOS (µV)
NUMBER OF AMPLIFIERS
–25
13405-007
–40
10
50
40
30
20
0
–20
20
VOS (µV)
–60
–50
13405-005
40
36
32
24
28
20
16
8
12
4
0
–8
–4
–12
–16
–20
–28
–24
–32
–36
–40
0
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 8. Input Offset Voltage (VOS) vs. Temperature, VSY = 10 V
Figure 5. Input Offset Voltage Distribution, VSY = 10 V
80
100
VSY = 16V
VCM = VSY/2
590 CHANNELS
x = 2.15µV
σ = 5.47µV
90
80
70
VSY = 16V
VCM = VSY/2
574 CHANNELS
60
40
VOS (µV)
60
50
40
30
20
0
–20
20
40
13405-006
VOS (µV)
36
32
24
28
20
16
8
12
4
0
–8
–4
–12
–16
–20
–28
–24
–32
–36
0
–60
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 9. Input Offset Voltage (VOS) vs. Temperature, VSY = 16 V
Figure 6. Input Offset Voltage Distribution, VSY = 16 V
Rev. A | Page 11 of 50
13405-009
–40
10
–40
NUMBER OF AMPLIFIERS
–25
13405-008
–40
10
ADA4530-1
Data Sheet
120
120
60
40
20
80
0.1
0.2
0.3
0.4
0.5
VSY = 10V
VCM = VSY/2
574 CHANNELS
0°C ≤ TA ≤ 125°C
x = –0.025µV/°C
σ = 0.107µV/°C
60
40
–0.4
–0.3
–0.2
–1.0
0
0.1
0.2
0.3
0.4
0.5
TCVOS (µV/°C)
13405-011
0
–0.5
13405-014
2.8
2.4
1.6
2.0
1.2
0.8
0
0.4
–0.4
–0.8
–1.2
–1.6
–2.0
–2.4
–2.8
Figure 11. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 10 V
Figure 14. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 10 V
120
120
VSY = 16V
VCM = VSY/2
574 CHANNELS
–40°C ≤ TA ≤ 0°C
x = –0.29µV/°C
σ = 0.41µV/°C
NUMBER OF AMPLIFIERS
100
60
40
80
VSY = 16V
VCM = VSY/2
574 CHANNELS
0°C ≤ TA ≤ 125°C
x = –0.024µV/°C
σ = 0.107µV/°C
60
40
20
2.4
2.0
1.6
0.8
0
–0.5
13405-015
TCVOS (µV/°C)
1.2
0
0.4
–0.4
–0.8
–1.2
–1.6
–2.0
–2.4
0
2.8
20
–2.8
0
13405-010
2.8
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
TCVOS (µV/°C)
NUMBER OF AMPLIFIERS
–1.0
20
20
80
–0.2
Figure 13. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 4.5 V
100
40
100
–0.3
120
VSY = 10V
VCM = VSY/2
574 CHANNELS
–40°C ≤ TA ≤ 0°C
x = –0.29µV/°C
σ = 0.42µV/°C
60
0
–0.4
TCVOS (µV/°C)
120
80
40
0
–0.5
13405-013
2.4
2.0
1.6
1.2
0.8
0
0.4
–0.4
–0.8
–1.2
–1.6
–2.0
TCVOS (µV/°C)
Figure 10. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 4.5 V
100
60
20
–2.4
–2.8
0
80
VSY = 4.5V
VCM = VSY/2
574 CHANNELS
0°C ≤ TA ≤ 125°C
x = –0.025µV/°C
σ = 0.107µV/°C
Figure 12. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 16 V
–0.4
–0.3
–0.2
–1.0
0
0.1
TCVOS (µV/°C)
0.2
0.3
0.4
0.5
13405-012
80
100
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
100
VSY = 4.5V
VCM = VSY/2
574 CHANNELS
–40°C ≤ TA ≤ 0°C
x = –0.29µV/°C
σ = 0.42µV/°C
Figure 15. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 16 V
Rev. A | Page 12 of 50
Data Sheet
ADA4530-1
60
10
8
–20
–40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VCM (V)
0
–2
–4
–6
VSY = 10V
–8 27 CHANNELS
TA = 25°C
–10
0
500 1000
13405-016
–60
2
2.5
INPUT OFFSET VOLTAGE (µV)
VOS (µV)
20
0
–20
–40
VSY = 10V
590 CHANNELS
TA = 25°C
0
1
2
3
4
5
6
7
8
9
10
VCM (V)
4500
1.5
1.0
0.5
0
1
2
3
4
5
10
Figure 20. VOS Warm-Up Time
0
VSY = 10V
∆VCM = 400mV
–20
PREFERRED
COMMON-MODE
RANGE
SMALL SIGNAL CMRR (dB)
–40
20
VOS (µV)
4000
TIME AFTER POWER-ON (Minutes)
60
0
–20
–60
PREFERRED COMMON-MODE RANGE
–80
–100
–120
–140
–160
–40
VSY = 16V
590 CHANNELS
TA = 25°C
0
1
2
3
4
5
6
–180
7
8
9
VCM (V)
10 11 12 13 14 15 16
13405-018
–60
3500
VSY = 10V
TA = 25°C
Figure 17. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VSY = 10 V
40
3000
2.0
0
13405-017
–60
2500
Figure 19. VOS Long-Term Drift
60
PREFERRED
COMMON-MODE
RANGE
2000
TIME (Hours)
Figure 16. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 4.5 V
40
1500
13405-219
0
4
13405-220
VOS (µV)
20
6
13405-221
PREFERRED
COMMON-MODE
RANGE
INPUT OFFSET VOLTAGE (µV)
40
VSY = 4.5V
590 CHANNELS
TA = 25°C
Figure 18. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VSY = 16 V
Rev. A | Page 13 of 50
–200
0
1
2
3
4
5
6
7
8
9
VCM (V)
Figure 21. Small Signal CMRR vs. Common-Mode Voltage
ADA4530-1
Data Sheet
20
VSY = 4.5V
27 CHANNELS
TA = 85°C
15
10
IB+ (fA)
0
–5
–10
–10
–15
–15
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VCM (V)
Figure 22. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 4.5 V, TA = 85°C
–20
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VSY = 10V
27 CHANNELS
TA = 85°C
15
10
IB+ (fA)
0
0
–5
–5
–10
–10
–15
–15
1
2
3
4
5
6
7
8
9
10
VCM (V)
–20
13405-023
0
PREFERRED
COMMON-MODE RANGE
5
Figure 23. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 10 V, TA = 85°C
0
1
2
3
4
5
6
7
8
9
10
VCM (V)
13405-026
PREFERRED
COMMON-MODE RANGE
5
Figure 26. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 10 V, TA = 85°C
20
20
VSY = 16V
27 CHANNELS
TA = 85°C
15
VSY = 16V
27 CHANNELS
TA = 85°C
15
10
10
PREFERRED
COMMON-MODE RANGE
0
0
–5
–5
–10
–10
–15
–15
2
4
6
8
VCM (V)
10
12
14
16
–20
13405-024
0
PREFERRED
COMMON-MODE RANGE
5
IB+ (fA)
5
Figure 24. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 16 V, TA = 85°C
0
2
4
6
8
VCM (V)
10
12
14
16
13405-027
IB– (fA)
1.0
20
10
–20
0.5
Figure 25. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 4.5 V, TA = 85°C
VSY = 10V
27 CHANNELS
TA = 85°C
15
–20
0
VCM (V)
20
IB– (fA)
0
–5
–20
PREFERRED
COMMON-MODE
RANGE
5
13405-022
IB– (fA)
10
PREFERRED
COMMON-MODE
RANGE
5
VSY = 4.5V
27 CHANNELS
TA = 85°C
15
13405-025
20
Figure 27. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 16 V, TA = 85°C
Rev. A | Page 14 of 50
Data Sheet
ADA4530-1
300
VSY = 4.5V
27 CHANNELS
TA = 125°C
PREFERRED
COMMON-MODE
RANGE
IB+ (fA)
0
–100
–200
–200
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VCM (V)
Figure 28. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 4.5 V, TA = 125°C
300
–300
IB+ (fA)
–100
–200
–300
–400
–400
–500
–500
4
5
6
7
8
9
10
VCM (V)
–600
13405-029
3
2.5
3.0
3.5
Figure 29. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 10 V, TA = 125°C
4.0
4.5
PREFERRED
COMMON-MODE RANGE
–200
–300
2
2.0
VSY = 10V
27 CHANNELS
TA = 125°C
100
–100
1
1.5
200
0
0
1.0
300
0
–600
0.5
Figure 31. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 4.5 V, TA = 125°C
PREFERRED
COMMON-MODE RANGE
100
0
VCM (V)
VSY = 10V
27 CHANNELS
TA = 125°C
200
IB– (fA)
0
–100
–300
PREFERRED
COMMON-MODE
RANGE
100
13405-028
IB– (fA)
100
VSY = 4.5V
27 CHANNELS
TA = 125°C
200
0
1
2
3
4
5
6
7
8
9
10
VCM (V)
13405-032
200
13405-031
300
Figure 32. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 10 V, TA = 125°C
300
300
VSY = 16V
27 CHANNELS
TA = 125°C
200
VSY = 16V
27 CHANNELS
TA = 125°C
200
100
PREFERRED
COMMON-MODE RANGE
PREFERRED
COMMON-MODE RANGE
0
IB+ (fA)
IB– (fA)
100
0
–100
–100
–200
–300
–400
–200
0
2
4
6
8
VCM (V)
10
12
14
16
–600
13405-030
–300
Figure 30. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 16 V, TA = 125°C
0
2
4
6
8
VCM (V)
10
12
14
16
13405-033
–500
Figure 33. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 16 V, TA = 125°C
Rev. A | Page 15 of 50
ADA4530-1
Data Sheet
1000
120
–40°C TO +125°C LIMIT
VSY = 4.5V
VCM = VSY/2
RH < 10%
100
100
NUMBER OF AMPLIFIERS
–40°C TO +85°C LIMIT
1
0.1
IB+
IB–
20
30
40
50
60
70
80
90 100 110 120 130
Figure 34. Input Bias Current (IB) vs. Temperature, VSY = 4.5 V
0
–250 –200 –150 –100
50
100
150
200
250
Figure 37. Inverting Input Bias Current Histogram, TA = 125C, VSY = 10 V
120
VSY = 10V
VCM = VSY/2
590 CHANNELS
TA = 125°C
x = –74.59fA
σ = 23.66fA
100
NUMBER OF AMPLIFIERS
–40°C TO +85°C LIMIT
10
1
0.1
IB+
IB–
80
60
40
20
0.01
10
20
30
40
50
60
70
80
90 100 110 120 130
TEMPERATURE (°C)
0
50
100
150
200
250
IB+ (fA)
160
VSY = 16V
VCM = VSY/2
RH < 10%
100
–50
Figure 38. Noninverting Input Bias Current Histogram, TA = 125°C, VSY = 10 V
Figure 35. Input Bias Current (IB) vs. Temperature, VSY = 10 V
1000
0
–250 –200 –150 –100
13405-235
0
13405-020
IB (fA)
0
–40°C TO +125°C LIMIT
VSY = 10V
VCM = VSY/2
RH < 10%
100
VSY = 10V
VCM = VSY/2
590 CHANNELS
TA = 125°C
x = 33.9fA
σ = 17.9fA
–40°C TO +125°C LIMIT
140
NUMBER OF AMPLIFIERS
–40°C TO +85°C LIMIT
10
1
0.1
IB+
IB–
0.01
120
100
80
60
40
20
0
10
20
30
40
50
60
70
80
90 100 110 120 130
TEMPERATURE (°C)
13405-236
IB (fA)
–50
IB– (fA)
1000
0.001
40
13405-019
10
13405-234
0
TEMPERATURE (°C)
0.001
60
20
0.01
0.001
80
0
–150 –120
–90
–60
–30
0
30
60
90
IOS (fA)
Figure 39. Input Offset Current Histogram
Figure 36. Input Bias Current (IB) vs. Temperature, VSY = 16 V
Rev. A | Page 16 of 50
120
150
13405-239
IB (fA)
10
VSY = 10V
VCM = VSY/2
590 CHANNELS
TA = 125°C
x = –40.69fA
σ = 24.54fA
0.0001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
10
1
–40°C
+25°C
+85°C
+125°C
VSY = 10V
0.1
0.01
0.001
0.0001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
13405-038
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (V)
Figure 40. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD),
VSY = 4.5 V
10
1
–40°C
+25°C
+85°C
+125°C
VSY = 16V
0.1
0.01
0.001
0.0001
0.01
0.1
1
LOAD CURRENT (mA)
10
100
13405-039
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (V)
Figure 41 Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD),
VSY = 10 V
Figure 42. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD),
VSY = 16 V
VSY = 4.5V
0.1
0.01
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
13405-040
0.001
1
–40°C
+25°C
+85°C
+125°C
Figure 43. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD),
VSY = 4.5 V
10
1
–40°C
+25°C
+85°C
+125°C
VSY = 10V
0.1
0.01
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
13405-041
0.01
10
Figure 44. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD),
VSY = 10 V
10
1
–40°C
+25°C
+85°C
+125°C
VSY = 16V
0.1
0.01
0.001
0.01
0.1
1
LOAD CURRENT (mA)
10
100
13405-042
0.1
OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (V)
VSY = 4.5V
OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (V)
1
–40°C
+25°C
+85°C
+125°C
OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (V)
10
ADA4530-1
13405-037
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (V)
Data Sheet
Figure 45. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD),
VSY = 16 V
Rev. A | Page 17 of 50
80
70
60
50
RL = 2kΩ
30
RL = 10kΩ
10
–25
0
25
50
75
100
125
TEMPERATURE (°C)
225
200
VSY = 10V
175
150
125
100
RL = 2kΩ
75
50
RL = 10kΩ
25
0
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
360
VSY = 16V
300
270
240
210
180
150
RL = 2kΩ
120
90
60
RL = 10kΩ
30
0
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 48. Output Voltage Low (VOL) to Supply Rail vs. Temperature,
VSY = 16 V
80
70
RL = 2kΩ
60
50
40
30
20
RL = 10kΩ
10
0
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
225
200
VSY = 10V
175
RL = 2kΩ
150
125
100
75
50
RL = 10kΩ
25
0
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 50. Output Voltage High (VOH) to Supply Rail vs. Temperature,
VSY = 10 V
13405-045
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (mV)
Figure 47. Output Voltage Low (VOL) to Supply Rail vs. Temperature,
VSY = 10 V
330
VSY = 4.5V
Figure 49. Output Voltage High (VOH) to Supply Rail vs. Temperature,
VSY = 4.5 V
13405-044
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (mV)
Figure 46. Output Voltage Low (VOL) to Supply Rail vs. Temperature,
VSY = 4.5 V
90
13405-047
0
–50
100
360
330
VSY = 16V
300
270
RL = 2kΩ
240
210
180
150
120
90
RL = 10kΩ
60
30
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
125
13405-048
20
OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (mV)
40
OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (mV)
90
VSY = 4.5V
13405-046
100
OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (mV)
Data Sheet
13405-043
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (mV)
ADA4530-1
Figure 51. Output Voltage High (VOH) to Supply Rail vs. Temperature,
VSY = 16 V
Rev. A | Page 18 of 50
Data Sheet
ADA4530-1
0
–40°C
+25°C
+85°C
1.2
+125°C
VCM = VSY/2
VSY = 10V
∆VCM = 400mV
–20
PSRR–
PSRR+
–40
SMALL SIGNAL PSRR (dB)
ISY PER AMPLIFIER (mA)
1.4
1.0
0.8
0.6
0.4
–60
PREFERRED INPUT VOLTAGE
RANGE
–80
–100
–120
–140
–160
0.2
2
4
6
8
10
11
14
16
SUPPLY VOLTAGE (V)
VCM = VSY/2
1.0
0.8
0.6
0.4
0
–50
4.5V
10V
16V
–25
0
25
50
75
100
125
TEMPERATURE (°C)
13405-050
ISY PER AMPLIFIER (mA)
1.2
0.2
0
1
2
3
4
5
6
7
8
9
10
VCM (V)
Figure 54. Small Signal PSRR vs. Common-Mode Voltage (VCM)
Figure 52. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY)
1.4
–200
Figure 53. Supply Current (ISY) per Amplifier vs. Temperature
Rev. A | Page 19 of 50
13405-254
0
13405-049
0
–180
ADA4530-1
Data Sheet
MAIN AMPLIFIER, AC PERFORMANCE
VSY = 4.5 V to 16 V, data taken at VSY = 10 V, TA = 25°C, unless otherwise noted.
120
60
100
100
50
80
80
60
60
40
40
–20
–40
–60
10k
–20
–40
VSY = 10V
RL = 10kΩ
100k
AV = +10
20
10
AV = +1
0
–10
–60
10M
1M
30
–20
1k
FREQUENCY (Hz)
10k
10k
80
CLOSED-LOOP OUTPUT IMPEDANCE (Ω)
VSY = 10V
VCM = VSY/2
RL = 10kΩ
CL = 10pF
90
60
50
40
30
20
1M
10M
FREQUENCY (Hz)
13405-056
10
100k
100
AV = +10
10
1
AV = +100
AV = +1
0.1
0.01
0.001
10k
100k
1M
10M
Figure 59. Closed-Loop Output Impedance vs. Frequency
60
PSSR+
PSSR–
VSY = 10V
VCM = VSY/2
RL = 10kΩ
CL = 10pF
VSY = 10V
VIN = 100mV p-p
AV = +1
RL = 10kΩ
50
OVERSHOOT (%)
40
1k
FREQUENCY (Hz)
60
30
20
40
OS–
30
20
OS+
10
10
0
10k
100k
1M
FREQUENCY (Hz)
10M
13405-057
PSRR (dB)
VSY = 10V
VCM = VSY/2
1k
0.0001
100
Figure 56. CMRR vs. Frequency
50
10M
0
0
30
60
90
120
150
180
210
240
LOAD CAPACITANCE (pF)
Figure 60. Small Signal Overshoot vs. Load Capacitance
Figure 57. PSRR vs. Frequency
Rev. A | Page 20 of 50
270
13405-060
CMRR (dB)
70
0
10k
1M
Figure 58. Closed-Loop Gain vs. Frequency
Figure 55. Open-Loop Gain and Phase Margin vs. Frequency
100
100k
FREQUENCY (Hz)
13405-058
0
10pF
10pF
100pF
100pF
40
13405-059
0
CLOSED-LOOP GAIN (dB)
20
PHASE MARGIN (Degrees)
20
VSY = 10V
RL = 10kΩ
CL = 10pF
AV = +100
13405-055
OPEN-LOOP GAIN (dB)
120
Data Sheet
ADA4530-1
80
1.0
60
0.5
0
–20
0
VSY = 4.5V
VIN = 100mV p-p
AV = +1
RL = 10kΩ
CL = 10pF
RS = 1kΩ
–1.0
–1.5
–40
–2.0
–80
TIME (2µs/DIV)
13405-061
–60
–2.5
TIME (2µs/DIV)
Figure 61. Small Signal Transient Response, VSY = 4.5 V
Figure 64. Large Signal Transient Response, VSY = 4.5 V
80
6
60
4
2
20
–20
VOLTAGE (V)
VOLTAGE (mV)
40
0
VSY = 4.5V
VIN = 2.75V p-p
AV = +1
RL = 10kΩ
CL = 10pF
RS = 1kΩ
–0.5
13405-064
20
VOLTAGE (V)
VOLTAGE (mV)
40
VSY = 10V
VIN = 100mV p-p
AV = +1
RL = 10kΩ
CL = 10pF
RS = 1kΩ
VSY = 10V
VIN = 8.25V p-p
AV = +1
RL = 10kΩ
CL = 10pF
RS = 1kΩ
0
–2
–40
TIME (2µs/DIV)
13405-062
–80
–6
TIME (5µs/DIV)
Figure 62. Small Signal Transient Response, VSY = 10 V
Figure 65. Large Signal Transient Response, VSY = 10 V
80
10
8
60
6
40
VOLTAGE (V)
–20
VSY = 16V
VIN = 100mV p-p
AV = +1
RL = 10kΩ
CL = 10pF
RS = 1kΩ
VSY = 16V
VIN = 14.25V p-p
AV = +1
RL = 10kΩ
CL = 10pF
RS = 1kΩ
2
0
–2
–4
–40
–6
–60
TIME (2µs/DIV)
–10
TIME (20µs/DIV)
Figure 66. Large Signal Transient Response, VSY = 16 V
Figure 63. Small Signal Transient Response, VSY = 16 V
Rev. A | Page 21 of 50
13405-066
–8
–80
13405-063
VOLTAGE (mV)
4
20
0
13405-065
–4
–60
ADA4530-1
Data Sheet
6
VSY = 4.5V
VIN = 450mV
AV = –10
RL = 10kΩ
CL = 10pF
2
VOUT
1
–1.0
–1.2
1.0
–0.2
0.5
–0.4
0
–0.6
–0.5
–0.8
–1.2
–1
TIME (2µs/DIV)
7
1.0
0.8
5
VIN
0.6
0.4
3
0.2
0
1
–0.2
–0.4
–1
–0.6
–0.8
–1.2
–1.4
–1.6
–7
Figure 71. Negative Overload Recovery, VSY = 10 V
2
12
12
9
–5
6
–6
3
–7
0
INPUT VOLTAGE (V)
VOUT
15
OUTPUT VOLTAGE (V)
VIN
1
VIN
8
18
0
4
–1
0
–2
–4
VSY = 16V
VIN = 1.5V
AV = –10
RL = 10kΩ
CL = 10pF
VOUT
–3
–3
–8
TIME (2µs/DIV)
13405-069
INPUT VOLTAGE (V)
–5
21
VSY = 16V
VIN = 1.5V
AV = –10
RL = 10kΩ
CL = 10pF
–3
–4
–3
TIME (2µs/DIV)
24
–1
–2
VSY = 10V
VIN = 900mV
AV = –10
RL = 10kΩ
CL = 10pF
VOUT
–1.0
Figure 68. Positive Overload Recovery, VSY = 10 V
0
–2.5
1.2
TIME (2µs/DIV)
1
–2.0
OUTPUT VOLTAGE (V)
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
–1
INPUT VOLTAGE (V)
VOUT
–1.5
Figure 70. Negative Overload Recovery, VSY = 4.5 V
OUTPUT VOLTAGE (V)
VIN
–1.0
TIME (2µs/DIV)
13405-068
INPUT VOLTAGE (V)
VSY = 10V
VIN = 900mV
AV = –10
RL = 10kΩ
CL = 10pF
VOUT
–1.4
Figure 67. Positive Overload Recovery, VSY = 4.5 V
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
–2.2
–2.4
–2.6
–2.8
–3.0
–3.2
VSY = 4.5V
VIN = 400mV
AV = –10
RL = 10kΩ
CL = 10pF
–1.0
0
–1.4
0
Figure 69. Positive Overload Recovery, VSY = 16 V
–4
–8
–12
TIME (2µs/DIV)
Figure 72. Negative Overload Recovery, VSY = 16 V
Rev. A | Page 22 of 50
OUTPUT VOLTAGE (V)
–0.8
3
1.5
13405-072
–0.6
4
2.0
VIN
0.2
13405-071
VIN
OUTPUT VOLTAGE (V)
–0.4
5
13405-067
INPUT VOLTAGE (V)
–0.2
0.4
2.5
OUTPUT VOLTAGE (V)
0
0.6
13405-070
7
INPUT VOLTAGE (V)
0.2
TIME (1µs/DIV)
OUTPUT
ERROR BAND
POST GAIN = 20
TIME (1µs/DIV)
OUTPUT
ERROR BAND
POST GAIN = 20
OUTPUT VOLTAGE (5mV/DIV)
INPUT
TIME (1µs/DIV)
ERROR BAND
POST GAIN = 20
TIME (1µs/DIV)
TIME (1µs/DIV)
INPUT VOLTAGES (250mV/DIV)
OUTPUT VOLTAGE (5mV/DIV)
INPUT
INPUT
VSY = 16V
DUT AV = –1
RL = 10kΩ
CL = 10pF
OUTPUT
ERROR BAND
POST GAIN = 20
13405-275
INPUT VOLTAGES (250mV/DIV)
Figure 77. Positive Settling Time to 0.1%, VSY = 10 V
VSY = 16V
DUT AV = –1
RL = 10kΩ
CL = 10pF
ERROR BAND
POST GAIN = 20
VSY = 10V
DUT AV = –1
RL = 10kΩ
CL = 10pF
OUTPUT
Figure 74. Negative Settling Time to 0.1%, VSY = 10 V
OUTPUT
INPUT
OUTPUT VOLTAGE (5mV/DIV)
VSY = 10V
DUT AV = –1
RL = 10kΩ
CL = 10pF
13405-277
INPUT VOLTAGES (250mV/DIV)
Figure 76. Positive Settling Time to 0.1%, VSY = 4.5 V
13405-274
INPUT VOLTAGES (250mV/DIV)
Figure 73. Negative Settling Time to 0.1%, VSY = 4.5 V
TIME (1µs/DIV)
Figure 75. Negative Settling Time to 0.1%, VSY = 16 V
Figure 78. Positive Settling Time to 0.1%, VSY = 16 V
Rev. A | Page 23 of 50
OUTPUT VOLTAGE (5mV/DIV)
ERROR BAND
POST GAIN = 20
INPUT
13405-278
OUTPUT
OUTPUT VOLTAGE (5mV/DIV)
INPUT
VSY = 4.5V
DUT AV = –1
RL = 10kΩ
CL = 10pF
OUTPUT VOLTAGE (5mV/DIV)
VSY = 4.5V
DUT AV = –1
RL = 10kΩ
CL = 10pF
13405-276
INPUT VOLTAGES (250mV/DIV)
ADA4530-1
13405-273
INPUT VOLTAGES (250mV/DIV)
Data Sheet
ADA4530-1
Data Sheet
0.1
10
VSY = 4.5V
AV = +1
RL = 10kΩ
VIN = 0.5V rms
VSY = 4.5V
AV = +1
RL = 10kΩ
f = 1kHz
1
THD + N (%)
THD + N (%)
90kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
0.01
0.1
0.01
100
1k
10k
100k
FREQUENCY (Hz)
0.001
0.001
13405-279
0.001
10
1
Figure 82. THD + N vs. Amplitude, VSY = 4.5 V
10
VSY = 10V
AV = +1
RL = 10kΩ
VIN = 2V rms
VSY = 10V
AV = +1
RL = 10kΩ
f = 1kHz
1
THD + N (%)
THD + N (%)
90kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
0.1
AMPLITUDE (V rms)
Figure 79. THD + N vs. Frequency, VSY = 4.5 V
0.1
0.01
13405-282
90kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
0.01
0.1
0.01
0.001
100
1k
10k
100k
FREQUENCY (Hz)
0.0001
0.001
13405-280
0.001
10
90kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
0.1
1
10
AMPLITUDE (V rms)
Figure 80. THD + N vs. Frequency, VSY = 10 V
1
0.01
13405-283
90kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
Figure 83. THD + N vs. Amplitude, VSY = 10 V
10
VSY = 16V
AV = +1
RL = 10kΩ
VIN = 4.5V rms
VSY = 16V
AV = +1
RL = 10kΩ
f = 1kHz
1
THD + N (%)
THD + N (%)
0.1
0.1
0.01
0.01
100
1k
10k
FREQUENCY (Hz)
100k
Figure 81. THD + N vs. Frequency, VSY = 16 V
0.001
0.001
0.01
0.1
1
AMPLITUDE (V rms)
Figure 84. THD + N vs. Amplitude, VSY = 16 V
Rev. A | Page 24 of 50
10
13405-284
0.001
10
13405-281
90kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
Data Sheet
ADA4530-1
3
100
10
1
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
VSY = 10V
NOISE = 4µV p-p
2
1
0
–1
–2
–3
TIME (1s/DIV)
Figure 86. 0.1 Hz to 10 Hz Noise
Figure 85. Voltage Noise Density, VSY = 10 V
Rev. A | Page 25 of 50
13405-286
INPUT REFERRED VOLTAGE (µV)
VSY = 10V
AV = +1
RL = 10kΩ
CL = 10pF
13405-285
VOLTAGE NOISE DENSITY (nV/√Hz)
1000
ADA4530-1
Data Sheet
GUARD AMPLIFIER
TA = 25°C, unless otherwise noted.
120
100
VSY = 4.5V
VCM = VSY/2
590 CHANNELS
TA = 25°C
x = –3.68µV
σ = 12.35µV
80
50
VOS (µV)
60
100
13405-091
30
40
50
60
70
80
90
–30
–20
–10
0
10
20
–90
–80
–70
–60
–50
–40
–100
VOS (µV)
–150
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
13405-094
VSY = 4.5V
VCM = VSY/2
574 CHANNELS
–100
0
Figure 90. Input Offset Voltage (VOS) vs. Temperature, VSY = 4.5 V
Figure 87. Input Offset Voltage Distribution, VSY = 4.5 V
100
120
VSY = 10V
VCM = VSY/2
590 CHANNELS
TA = 25°C
x = –3.8µV
σ = 12.4µV
100
80
50
VOS (µV)
60
0
–50
40
VSY = 10V
VCM = VSY/2
574 CHANNELS
–100
100
VOS (µV)
–150
–50
13405-092
30
40
50
60
70
80
90
–30
–20
–10
0
10
20
–100
0
–90
–80
–70
–60
–50
–40
20
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 88. Input Offset Voltage Distribution, VSY = 10 V
13405-095
NUMBER OF AMPLIFIERS
–50
40
20
Figure 91. Input Offset Voltage (VOS) vs. Temperature, VSY = 10 V
120
100
VSY = 16V
VCM = VSY/2
590 CHANNELS
TA = 25°C
x = –3.86µV
σ = 12.2µV
100
50
VOS (µV)
80
60
0
–50
40
VOS (µV)
100
13405-093
30
40
50
60
70
80
90
–30
–20
–10
0
10
20
–90
–80
–70
–60
–50
–40
0
VSY = 16V
VCM = VSY/2
574 CHANNELS
–100
20
–100
NUMBER OF AMPLIFIERS
0
–150
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 92. Input Offset Voltage (VOS) vs. Temperature, VSY = 16 V
Figure 89. Input Offset Voltage Distribution, VSY = 16 V
Rev. A | Page 26 of 50
13405-096
NUMBER OF AMPLIFIERS
100
Data Sheet
ADA4530-1
160
120
60
40
20
140
60
40
120
100
–0.2
0
0.2
0.4
0.6
0.8
1.0
VSY = 10V
VCM = VSY/2
574 CHANNELS
0°C ≤ TA ≤ 125°C
x = 0.017µV/°C
σ = 0.168µV/°C
80
60
40
Figure 94. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 10 V
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
TCVOS (µV/°C)
13405-101
TCVOS (µV/°C)
0
–1.0
13405-098
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–0.4
20
0
Figure 97. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 10 V
160
120
VSY = 16V
VCM = VSY/2
574 CHANNELS
–40°C ≤ TA ≤ 0°C
x = 0.27µV/°C
σ = 1.14µV/°C
NUMBER OF AMPLIFIERS
140
60
40
20
120
100
VSY = 16V
VCM = VSY/2
574 CHANNELS
0°C ≤ TA ≤ 125°C
x = 0.02µV/°C
σ = 0.168µV/°C
80
60
40
0
–1.0
13405-099
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
TCVOS (µV/°C)
7
20
0
–7
–0.6
160
VSY = 10V
VCM = VSY/2
574 CHANNELS
–40°C ≤ TA ≤ 0°C
x = 0.26µV/°C
σ = 1.14µV/°C
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
–0.8
Figure 96. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 4.5 V
20
NUMBER OF AMPLIFIERS
40
TCVOS (µV/°C)
120
80
60
13405-100
7
Figure 93. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 4.5 V
100
80
0
–1.0
13405-097
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
TCVOS (µV/°C)
80
100
20
0
100
120
VSY = 4.5V
VCM = VSY/2
574 CHANNELS
0°C ≤ TA ≤ 125°C
x = 0.014µV/°C
σ = 0.168µV/°C
Figure 95. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 16 V
–0.8
–0.6
–0.4
–0.2
0
0.2
TCVOS (µV/°C)
0.4
0.6
0.8
1.0
13405-102
80
140
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
100
VSY = 4.5V
VCM = VSY/2
574 CHANNELS
–40°C ≤ TA ≤ 0°C
x = 0.26µV/°C
σ = 1.14µV/°C
Figure 98. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 16 V
Rev. A | Page 27 of 50
ADA4530-1
Data Sheet
THEORY OF OPERATION
The guard pins are connected to the power supplies through
Diode D5 and Diode D6. During ESD events, the transient
current flows from the input pins through one of the antiparallel
diodes and harmlessly into the supplies through one of the power
supply diodes. During normal operation, the guard buffer (BUF1)
forces the voltage across the antiparallel diodes to 0 V. Resistor R1
shields the guard buffer from potentially large capacitances
connected to the guard pins. Its value is nominally 1 kΩ.
The ADA4530-1 is an operational amplifier specifically
designed to interface with the extremely high impedance
sensors used in electrometer applications.
A MOSFET input stage eliminates the gate leakage currents
associated with legacy junction gate field effect transistor
(JFET) electrometers. The ADA4530-1 achieves extremely low
input bias currents while simultaneously providing robust
protection against ESD damage. A unique ESD diode structure
provides protection while also allowing the diodes to be
guarded to minimize leakage currents to the input pins. The
ADA4530-1 integrates the precision buffer used to guard
internal ESD diode leakage paths. The output of this guard
buffer is also connected to external pins to allow the user to
guard external components against leakage currents.
INPUT STAGE
The input stage comprises a PMOS differential pair (M1, M2),
folded cascode transistors (M5 to M12), and current source I1.
The ADA4530-1 achieves its high performance specifications by
using low voltage MOS devices for its differential inputs. These
low voltage MOS devices offer better 1/f noise and bandwidth
per unit current compared to high voltage devices. The input
stage is isolated from the high system voltages with proprietary
protection circuitry. This regulation circuitry protects the input
devices from the high supply voltages in which the amplifier
can operate.
The input bias current is determined by the accuracy of the
guard voltage applied across the ESD diodes. The offset voltages
of the amplifier and guard buffer set the accuracy of the guard
voltage and, therefore, the input bias current.
The ADA4530-1 uses Analog Devices, Inc., DigiTrim™
technology to achieve its superior performance.
The proprietary high voltage protection circuitry in the
ADA4530-1 operates in such a way that it minimizes the
common-mode voltage changes seen by the amplifier input
stage for most of the input common-mode range. This circuitry
results in excellent disturbance rejection when operating in this
preferred input common-mode range. The performance
benefits of operating within this preferred range are shown in
the VOS vs. VCM graphs (see Figure 16 to Figure 18), the small
signal CMRR vs. VCM graph (see Figure 21), and the small signal
PSRR vs. VCM graph (see Figure 54).
DigiTrim is used to trim the offset voltage of the amplifier and
guard buffer to reject changes in the common-mode voltage,
power supply voltage, and temperature. This technique
significantly improves VOS, CMRR, PSRR, and TCVOS
specifications.
Figure 99 shows the simplified schematic of the ADA4530-1.
The amplifier uses a three-stage architecture with a fully
differential input stage to achieve excellent dc performance
specifications.
These input devices are protected from large differential input
voltages by the antiparallel ESD diodes (D1 to D4). The diodes
can conduct significant current when the differential voltage
exceeds 700 mV. The user must ensure that the current flowing
into the input pins is limited to the absolute maximum of 10 mA.
ESD STRUCTURE
The input ESD structure consists of Diode D1 to Diode D6.
The noninverting input is coupled to the guard pins (GRD)
by the D1 and D2 antiparallel diodes. The inverting input is
coupled to the guard pins by the D3 and D4 antiparallel diodes.
V+
HIGH VOLTAGE PROTECTION
M19
M20
M17
M18
D5
I1
+IN
GRD
M1
D1
D2
M2
M11
M12
M9
M10
M22
M3 M4
R1
GRD
OUT
V1
BUF1
D3
D4
M7
–IN
C2
C1
C3
M8
M5
D6
M6
HIGH VOLTAGE PROTECTION
V–
Figure 99. Simplified Schematic
Rev. A | Page 28 of 50
M15
M16
M13
M14
13405-299
M21
I2
Data Sheet
ADA4530-1
GAIN STAGE
The second stage of the amplifier comprises an NMOS differential pair (M3, M4) and folded cascode transistors (M13 to M20).
The amplifier features nested Miller compensation (C1 to C3).
OUTPUT STAGE
The ADA4530-1 features a complementary common-source
output stage consisting of the M21 and M22 transistors. These
transistors are configured in a Class AB topology and are biased
by the voltage source, V1. This topology allows the output
voltage to be within tens of millivolts of the supply rails,
achieving a rail-to-rail output swing. The output voltage is
limited by the output impedance of the transistors. The output
voltage swing is a function of the load current and can be
estimated using the output voltage to the supply rail vs. load
current graphs (see Figure 40 to Figure 45).
GUARD BUFFER
The guard buffer (BUF1) is a unity-gain amplifier that creates a
low impedance replica of the input common-mode voltage. The
buffer input is connected to the noninverting input (IN+). The
noninverting input voltage is approximately equal to the input
common-mode voltage when the main amplifier feedback loop
is settled.
The guard buffer uses a three-stage architecture similar to that
of the amplifier. The guard buffer uses a rail-to-rail output stage
that allows the guard voltage to swing within 100 mV of the
supply rails. Because the guard buffer output follows the input
common-mode voltage, this output swing limits the effectiveness
of the guard buffer at low input common-mode voltages. This
limit can be seen as a significant increase in input bias current
at low common-mode voltages in the input bias current vs.
common-mode voltage graphs (see Figure 22 to Figure 33). For
this reason, it is not recommended to operate the circuit with an
input common-mode voltage of less than 100 mV from the V−
supply rail.
The guard buffer output voltage can be degraded from excessive
loading. The 1 kΩ output resistance adds 1 μV of guard voltage
error per 1 nA of load current. It is possible to drive the guard
offset voltage out of its specifications with a few tens of nanoamperes of load current. For this reason, it is not recommended
to drive anything except insulation resistance (see the Insulation
Resistance and Guarding section) with the guard buffer. If more
drive strength is needed, the guard voltage can be buffered with
a low offset, low input bias current op amp such as the
ADA4661-2.
Rev. A | Page 29 of 50
ADA4530-1
Data Sheet
APPLICATIONS INFORMATION
INPUT PROTECTION
When either input of the ADA4530-1 exceeds one of the supply
rails by more than 300 mV, the input ESD diodes become
forward-biased and large amounts of current begin to flow
through them. Without current limiting, this excessive fault
current causes permanent damage to the device. If the inputs
are expected to be subject to overvoltage conditions, insert a
resistor in series with each input to limit the input current to
10 mA maximum. However, consider the resistor thermal noise
effect on the entire circuit.
SINGLE-SUPPLY AND RAIL-TO-RAIL OUTPUT
The ADA4530-1 is a single supply amplifier with an input
voltage range (IVR) from V− to V+ − 1.5 V. The amplifier has a
small keep alive input stage that allows it to function properly
when the input common-mode voltage is greater than the
specified IVR. This feature allows the ADA4530-1 to start up
and recover quickly in certain types of circuits where the IVR is
violated at power-up. The ac and dc performance of this keep
alive stage is poor; do not rely upon this keep alive stage for
normal use.
VSY = ±8V
VIN = ±8.3V
AV = +1
RL = 10kΩ
CL = 10pF
8
6
4
2
0
–2
–4
–6
VIN
VOUT
–8
13405-300
The ADA4530-1 is suited for applications requiring very low
input bias current and low offset voltage, including, but not
limited to, preamplifier applications, for a wide variety of
current output transducers (photodiodes, photomultiplier
tubes), spectrometry, chromatography, and high impedance
buffering for chemical sensors.
10
–10
TIME (200µs/DIV)
Figure 100. No Phase Reversal
CAPACITIVE LOAD STABILITY
The ADA4530-1 can safely drive capacitive loads of up to
250 pF in any configuration. As with most amplifiers, driving
larger capacitive loads than specified may cause excessive
overshoot and ringing, or even oscillation. A heavy capacitive
load reduces phase margin and causes the amplifier frequency
response to peak. Peaking corresponds to overshooting or
ringing in the time domain. Therefore, it is recommended that
external compensation be used if the ADA4530-1 must drive a
load exceeding 250 pF. This compensation is particularly
important in the unity-gain configuration, which is the worst
case for stability.
A quick and easy way to stabilize the op amp for capacitive load
drive is by adding a series resistor, RISO, between the amplifier
output terminal and the load capacitance, as shown in Figure 101.
RISO isolates the amplifier output and feedback network from
the capacitive load. However, with this compensation scheme,
the output impedance as seen by the load increases, and this
reduces gain accuracy.
+VSY
RISO
VIN
ADA4530-1
–VSY
VOUT
CL
13405-201
The ADA4530-1 has ultralow input bias currents that are
production tested at 25°C and 125°C to ensure that the device
meets its performance goals in a system application. An
integrated guard buffer is provided to minimize input pin
leakage in a printed circuit board (PCB) design, minimize
board component count, and enable ease of system design.
The guard buffer output pins are also strategically placed next
to the input pins to enable easy routing of the guard ring and
to prevent coupling between the inputs, power supplies, and
the output pin.
Figure 100 shows the input and output waveforms of the
ADA4530-1 configured as a unity-gain buffer with a supply
voltage of ±8 V. The output tracks the input voltage over the
entire range until the output voltage is clamped at its maximum
output swing. Note that the amplifier still operates even when
the signal is outside the specified input voltage range (−8 V ≤
IVR ≤ +6.5 V); this is due to the keep alive stage. Additionally, it
does not phase reverse. It is not recommended to apply an input
voltage that is outside of the input voltage range.
VOLTAGE (V)
The ADA4530-1 is a single, electrometer grade, CMOS
operational amplifier with femtoampere input bias current and
ultralow offset voltage. It operates over a wide supply voltage
range of 4.5 V (or ±2.25 V dual supply) to 16 V (or ±8 V dual
supply). It is a single-supply amplifier, where its input voltage
range includes the lower supply rail and has a rail-to-rail output.
The ADA4530-1 also achieves a low offset voltage of ±40 μV
maximum and offset voltage drift of ±0.5 μV/C maximum.
Figure 101. Stability Compensation with Isolating Resistor, RISO
Rev. A | Page 30 of 50
Data Sheet
ADA4530-1
Figure 102 shows the phase margin of the ADA4530-1 with
different values of output isolating resistors and capacitive
loads. Figure 103 shows the frequency response with 1 nF
capacitive load and different isolating resistors.
EMI REJECTION RATIO
Circuit performance is often adversely affected by high frequency
electromagnetic interference (EMI). When the signal strength is
low and transmission lines are long, an op amp must accurately
amplify the input signals. However, all op amp pins—the
noninverting input, inverting input, positive supply, negative
supply, and output pins—are susceptible to EMI signals. These high
frequency signals are coupled into an op amp by various means,
such as conduction, near field radiation, or far field radiation. For
example, wires and PCB traces can act as antennas and pick up
high frequency EMI signals.
80
70
60
Amplifiers do not amplify EMI or RF signals due to their
relatively low bandwidth. However, due to the nonlinearities of
the input devices, op amps can rectify these out of band signals.
When these high frequency signals are rectified, they appear as
a dc offset at the output.
50
1000
10000
CAPACITIVE LOAD (pF)
To describe the ability of the ADA4530-1 to perform as intended
in the presence of electromagnetic energy, the electromagnetic
interference rejection ratio (EMIRR) of the noninverting pin is
specified in Table 1, Table 2, and Table 3 of the Specifications
section. A mathematical method of measuring EMIRR is
defined as follows:
Figure 102. Phase Margin vs. Load Capacitance with Various Output
Isolating Resistors
100
VSY = 10V
AV = +1
CL = 1nF
PHASE
80
20
GAIN (RISO = 0Ω)
PHASE (RISO = 0Ω)
GAIN (RISO = 301Ω)
PHASE (RISO = 301Ω)
GAIN (RISO = 732Ω)
PHASE (RISO = 732Ω)
10k
PHASE (Degrees)
40
GAIN
20
–40
1k
EMIRR = 20log(VIN_PEAK/ΔVOS)
Figure 104 shows the typical EMIRR vs. frequency performance
for each of the specified supply voltages.
120
110
0
VSY = 4.5V TO 16V
100
–20
100k
1M
90
–40
10M
13405-303
GAIN (dB)
40
–20
80
60
60
0
100
FREQUENCY (Hz)
Figure 103. Frequency Response with CL = 1 nF and Various Isolating
Resistors
80
70
60
50
40
VSY = 4.5V
VSY = 10V
VSY = 16V
30
20
10M
100M
1G
FREQUENCY (Hz)
Figure 104. EMIRR vs. Frequency
Rev. A | Page 31 of 50
10G
13405-304
40
100
13405-302
RISO = 301Ω
RISO = 499Ω
RISO = 732Ω
EMIRR (dB)
PHASE MARGIN (Degrees)
VSY = 10V
AV = +1
ADA4530-1
Data Sheet
HIGH IMPEDANCE MEASUREMENTS
The ADA4530-1 is typically used in two kinds of circuits: a buffer
and a TIA. Buffer circuits are useful for measuring voltage output
sensors with high output resistance. Some example sensors include
pH probes and reference electrodes (RE) in coulometry control
loops. TIA circuits are useful for converting the signal from a
current output sensor to an output voltage. Some example
sensors include photodiodes and ion chambers.
The following sections describe some of the most important
error sources when using the ADA4530-1 in these circuits.
Simplified models with error sources are provided for the buffer
(see Figure 105) and the TIA (see Figure 106).
The buffer circuit models the voltage output sensor as a voltage
source (VSRC) with an output resistance (RSRC). The voltage on
the A terminal is sensed by Pin 1 of the ADA4530-1 in a
noninverting gain configuration (or a unity-gain configuration).
The B terminal is driven to a suitable reference voltage (signal
ground in this case).
If all errors sources are ignored, the output of the circuit is as
follows:
 R
VOUT  VSRC 1  F
 RS




VOLTAGE
SENSOR
ADA4530-1
A
1
+IN
RIN
RSRC
IB +
RSHUNT
8
VSRC
OUT
VOUT
6
–IN
VOS
RF
13405-310
RS
B
current through the feedback resistor. If all error sources are
ignored, the output of the circuit is as follows:
VOUT = ISRCRF
V+
RF
CURRENT
SENSOR
ADA4530-1
A
8
ISRC
RIN
RSRC
B
IB –
1
VOS
6
VOUT
Figure 106. Transimpedance Amplifier Circuit
INPUT BIAS CURRENT
The input bias current of the amplifier is a major error source in
high impedance electrometer circuits.
Like other semiconductor amplifiers, the input bias current of
the ADA4530-1 has an exponential dependence on temperature.
The input bias current of the ADA4530-1 increases by a factor
of 2.5 for every 10°C increase in temperature. Refer to the input
bias current vs. temperature graphs (see Figure 34 to Figure 36)
for typical temperature performance. Notice that the exponential diode currents cease to be the dominate contributor to the
input bias current at temperatures below 60°C to 70°C. The
residual 100 aA to 200 aA (aA = 10−18 A) bias currents are
dominated by other leakage paths that are highly sensitive to
environmental conditions. These vanishingly small bias currents
require highly controlled laboratory conditions to measure.
Most practical applications are dominated by other errors, and
the ADA4530-1 input bias current can be considered to be zero
for temperatures less than 70°C. The input bias current of the
ADA4530-1 can only be guaranteed to ±20 fA due to the
measurement limitations of a production environment even
though the achievable input bias currents are more than an
order of magnitude lower.
The input bias current affects the buffer circuit by loading down the
voltage sensor. The input bias current is forced to flow through the
output resistance of the sensor, which creates an error voltage.
VERR = IB+(RSRC)
Figure 105. Voltage Buffer Circuit
The TIA circuit models the current output sensor as a current
source (ISRC) with a shunt resistance (RSRC). The current from
the A terminal is connected to the inverting input pin of the
ADA4530-1 and the feedback resistor (RF). The B terminal and
the noninverting input of the amplifier are driven to a suitable
reference voltage (signal ground in this case). The negative
feedback of the circuit suppresses any voltage changes at the
A terminal. This suppression is accomplished by forcing all
IRF
RSHUNT
13405-311
The ADA4530-1 is designed to maximize the performance of very
high impedance circuits. Its performance advantages make it useful
for circuit impedances ranging from 100 MΩ to over 10 TΩ.
Measurements of high impedance circuits are subject to a number
of error sources. General information about making measurements
from high resistance sources can be found in the Low Level
Measurements Handbook, sixth edition (Keithley Instruments,
Inc., 2004).
The magnitude of this voltage error can be significant with very
high impedance sensors operating at high temperature. For
example, the input bias current can generate a maximum voltage
error of 25 mV from a 100 GΩ sensor operating at 125°C.
The input bias current affects the TIA circuit by summing
together with the sensor current. Both of these currents flow
through the feedback resistor to generate the output voltage as
follows:
VOUT = (ISRC + IB−)RF
Rev. A | Page 32 of 50
Data Sheet
ADA4530-1
The magnitude of the input bias current limits how small of a
signal current may be resolved accurately. For example, if the
acceptable error level is 10%, the minimum measurable signal
current is 2.25 pA for a circuit operating at 125°C.
ISRC = IB−(1/err – 1)
where err is the error level.
1
2.25 pA  250 fA
 1
 0.1 
equal to a few fA, which is the same magnitude as the input bias
current itself. These uncertainties make it impossible to calculate input resistances higher than a few hundred teraohms.
The input resistance affects the buffer circuit by loading down
the voltage sensor. This resistance acts as a voltage divider so
the voltage measured by the amplifier is some fraction of the
unloaded voltage of the sensor. This voltage drop is calculated
as follows:
VA  VSRC
INPUT RESISTANCE
The input resistance of the amplifier is another error source that
must be considered. Input resistance typically has two components: differential and common mode. The differential input
resistance is suppressed by the negative feedback of the circuit.
The ADA4530-1 has enough gain that the differential input
resistance is much too large to measure. The common-mode
input resistance (hereafter referred to as input resistance) is a
more important error source.
The input resistance is equal to the change in input bias current
relative to the change in input voltage. This change is not caused
by a physical resistance inside the ADA4530-1; it is the result of
a complex relationship between the accuracy of the guard voltage
across the ESD structures and the input common-mode voltage;
that is, the input resistance changes with common mode voltage. It
is also possible for the input resistance to be negative. Negative
input resistance means the input bias current decreases as the
common-mode voltage increases.
The input resistance, RIN, can be approximated by calculating
the slope of the input bias current vs. common-mode voltage
graphs (see Figure 22 to Figure 33). For example, the noninverting
input resistance can be calculated at 125°C from Figure 32. Note
that the input bias current changes by approximately 20 fA for
common-mode voltages from 4 V to 6 V.
RIN 
R IN 
VCM
I B 
2V
20 fA
RIN
RIN  RSRC
Consider the previous example of a 100 GΩ sensor operating at
125°C. The 100 TΩ input resistance causes the measured
voltage to equal 99.9% of the actual voltage, a 0.1% gain error.
The input resistance has much less of an effect on the TIA
circuit. The input common-mode voltage does not change in
this circuit; therefore, the error created is vanishingly small.
The input resistance affects the noise gain of the circuit, which
changes the input offset voltage error (see the Photodiode
Interface section for more information).
INPUT OFFSET VOLTAGE
The input offset voltage of the amplifier affects the buffer circuit
by adding directly to the voltage output of the sensor. This error
is typically much smaller than other errors.
The input offset voltage affects the TIA circuit in a different
manner. The burden voltage of the TIA is equal to the input
offset voltage. This burden voltage appears between the A and B
terminals. An error current is created by applying this burden
voltage across the sensor shunt resistance. For sensors with low
output resistances such as photodiodes, this error can be
significant. Consider a sensor with a 1 GΩ output resistance.
The 50 μV maximum offset voltage of the ADA4530-1 creates a
50 fA error current.
INSULATION RESISTANCE
 100 TΩ
The slope of the curves in the input bias current vs. commonmode voltage graphs increases rapidly outside the preferred
common-mode range (see Figure 22 to Figure 33). The input
resistance drops rapidly outside this range. This drop in input
resistance must be considered before operating these circuits
with input voltages close to the V− power supply.
Like the input bias current, the input resistance has a strong
temperature dependence. At lower temperatures, the amplifier
input resistance is so high that it is dominated by other error
sources. It is important to recognize the limitations of calculating
input resistance at lower temperatures. Measurement uncertainties make it difficult to accurately calculate the ΔIB term. Consider
the 85°C input bias current vs. common-mode voltage graphs
(see Figure 22 to Figure 27); the measurement uncertainties are
The ADA4530-1 has such low input bias current and such high
input resistance that the insulation resistance of the materials
that are used to construct the circuit is often the largest error
source. Any insulators with finite resistance that come in
contact with the high impedance conductor contribute to the
error current. Some examples include the printed circuit board
(PCB) laminate material, cable, and connector insulation.
The physical insulation resistance is distributed across the
entire contact surface of the high impedance conductor, and it
may end at several different conductors at different potentials. It
is useful to make a simple model where all of these resistance
paths are lumped into a single resistor. This lumped element is
shown as RSHUNT in the voltage buffer circuit (see Figure 105).
The insulation resistance affects the buffer circuit in the same
way as the amplifier input resistance. This resistance acts as a
voltage divider so that the voltage measured by the amplifier is
some fraction of the unloaded voltage of the sensor. This error
is significant because it is very difficult to maintain high
Rev. A | Page 33 of 50
ADA4530-1
Data Sheet
The effect on the insulation resistance on the TIA circuit depends
on the leakage path. The insulation resistance between the A
terminal and B terminal of the current sensor affects the circuit
in the same way as the amplifier input resistance. This error is
extremely small because the voltage across the insulation is
equal to the offset voltage of the amplifier. A much more
significant error is created from insulation paths to conductors
with significantly different potentials. This type of leakage path
is shown as lumped element, RSHUNT, in the TIA circuit (see
Figure 106). In this example, the leakage path is created from
the positive supply voltage (V+) to the A terminal. If the
positive supply voltage is 5 V relative to signal ground, 500 fA
flows through the insulation resistance of 10 TΩ. This large
error dominates the amplifier input bias current and input
resistance errors over the entire temperature range.
Leakage paths to high voltages can also affect the buffer circuit
with equally ruinous results.
GUARDING
High source impedances and low error requirements can create
insulation resistance requirements that are unrealistically high.
Fortunately, a technique called guarding can reduce these
requirements to a reasonable level. The concept of guarding is
to surround the high impedance conductor with another
conductor (guard) that is driven to the same voltage potential. If
there is no voltage across the insulation resistance (between
high impedance conductor and guard), there cannot be any
current flowing through it.
The ADA4530-1 uses guarding techniques internally, and it has
a very high performance guard buffer integrated. The output of
this buffer is made available externally to simplify the
implementation of guarding at the circuit level.
The voltage buffer circuit (see Figure 105) has been modified to
show the implementation of the guard (see Figure 107). In this
model, a conductor (VGRD) is added, and it completely separates
the high impedance (A) node from the low impedance (B) node
at a different voltage. The insulation resistance is modeled as
two resistances: all of the insulation between the A conductor
and the guard conductor (RSHUNT1), and all of the insulation
between the guard conductor and the B conductor (RSHUNT2).
The ADA4530-1 guard buffer then drives this guard conductor
(through Pin 2 and Pin 7) to the A terminal voltage. If the A
node and VGRD node are exactly the same voltage, no current
flows through the insulation resistance, RSHUNT1.
In practice, the voltage across RSHUNT1 cannot be 0 V, the guard
buffer offset voltage contributes to the difference in voltage
potential between the A node and VGRD node. For the
ADA4530-1, this offset voltage is trimmed to provide offsets
less than 100 μV when the input common-mode voltage is 1.5 V
from the supply rails. The guard buffer offset voltage and drift
are specified in Table 1, Table 2, and Table 3.
For example, assume that the voltage sensor produces an output
of 1 V. Without guarding, the 10 TΩ insulation resistance
creates an error current of 100 fA. With the guard, the voltage
across the insulation resistance is limited to 100 μV. The guard
limits the error current to 0.01 fA. In this example, the guard
reduces the error by a factor of 104 to an insignificant level.
VOLTAGE
SENSOR
ADA4530-1
A
1
RSHUNT1
RSRC
VGRD
2
7
8
VSRC
RSHUNT2
VOUT
6
RF
RS
B
13405-313
insulation resistance values in glass epoxy (such as FR-4) PCB
materials. Resistance values of 10 TΩ to 100 TΩ are achievable.
A 10 TΩ insulation resistance creates a 1% error with the 100 GΩ
sensor used in previous examples. Insulation resistance does not
have an exponential temperature dependence like the amplifier
errors previously discussed in the Input Bias Current section and
the Input Resistance section, which makes insulation resistance
the dominate error source at lower temperatures (less than 70°C).
Figure 107. Voltage Buffer Circuit with Guard
DIELECTRIC RELAXATION
Dielectric relaxation (also known as dielectric absorption or
soakage) is a property of all insulating materials that can limit
the performance of electrometer circuits that need to settle to a
few femtoamperes.
Dielectric relaxation is the delay in polarization of the dielectric
molecules in response to a changing electric field. This delay is
a property of all insulating materials. The magnitude and the
time constant of the delay depend on the specific dielectric
material. The delays in some materials can be minutes or even
hours.
Dielectric relaxation is a problem for electrometer circuits
because small displacement currents flow through the insulator
in response to the polarization of the molecules. Delays in
polarization cause delays in the dissipation of these currents,
which can dominate the settling time in these circuits.
In the context of capacitors, dielectric relaxation is called
dielectric absorption. Capacitors are specified with a test that
measures the residual open-circuit voltage after a specific
charge/discharge cycle. For electrometer circuits, it is more
useful to consider the short-circuit currents produced from step
changes in a test voltage.
A simple lumped circuit model of an insulator is connected to
the test voltage source (see Figure 108). The majority of the
dielectric polarizes instantly; this is modeled as Capacitor C1. A
small percentage of the dielectric polarizes slowly with a time
constant of τ2, modeled as Capacitor C2 and Resistor R2.
Rev. A | Page 34 of 50
Data Sheet
ADA4530-1
125
INSULATOR
MODEL
RS
ISRC
R2
C1
C2
13405-326
VSRC
75
12
50
8
25
4
0
0
–25
–4
–50
–8
–75
–12
–100
–16
–125
Figure 108. Dielectric Relaxation Model Test Circuit
0
0.5
1.0
1.5
2.0
2.5
ELAPSED TIME (Hours)
3.0
3.5
–20
4.0
Figure 110. Glass Epoxy Dielectric Relaxation Performance
VSRC
An alternative PCB laminate to consider is Rogers 4350B.
Rogers 4350B is a ceramic laminate designed for RF/microwave
circuits. Rogers 4350B is compatible with standard PCB production techniques and is widely available. The measurement
results for the Rogers 4350B material are shown in Figure 111.
This material requires less than 20 sec to dissipate the dielectric
relaxation current to less than 1 fA.
The current step response (ISRC) of the insulator to a voltage step
is shown in Figure 108. A large initial current charges Capacitor C1
with a fast time constant. This time constant, τ1, equals the source
resistance RS × C1 (see Figure 109). Long after Capacitor C1 is
charged, a much smaller current continues to flow, which charges
Capacitor C2. The time constant of charging is not affected by
the external circuitry; it depends only on the material properties of the insulator. The magnitude of the current depends on
the magnitude of the voltage change across the insulator.
The dielectric relaxation performance was measured for a
variety of PCB laminates using the test circuit in Figure 108.
An electrometer grade source measurement unit (SMU),
Keithley 6430, applies a ±100 V test stimulus and measures the
resulting current. The large alternating polarity test voltage
distinguishes the small dielectric relaxation current from the
input offset current of the SMU.
Based on its superior performance, it is recommended to use
Rogers 4350B laminates with the ADA4530-1 in the highest
performance applications. All of the critical characterization
measurements of the ADA4530-1 are taken using Rogers 4350B.
125
10
VSRC
ISRC
100
8
75
6
50
4
25
2
0
0
–25
–2
–50
–4
–75
–6
–100
–8
–125
The first PCB laminate tested is the industry-standard FR-4
glass epoxy. The measurement results are shown in Figure 110.
The glass epoxy laminate requires 1 hour to dissipate the
dielectric relaxation current to less than 10 fA. This result shows
that glass epoxy laminates are unsuitable for the highest
performance electrometer circuits.
Rev. A | Page 35 of 50
0
20
40
60
80
100 120 140
ELAPSED TIME (Seconds)
160
180
–10
200
Figure 111. Rogers 4350B Dielectric Relaxation Performance
CURRENT (fA)
Figure 109. Step Response of Dielectric Relaxation Model
13405-316
TIME
13405-314
2 = R2 × C2
APPLIED VOLTAGE (V)
1 = RS × C1
ISRC
16
CURRENT (fA)
APPLIED VOLTAGE (V)
τ2 = R2 × C2
20
VSRC
ISRC
100
13405-315
The size of C2 reflects the proportion of slow molecules. The
size depends on the material but it is typically 100 to 10,000
times smaller than C1. The size of R2 sets the time constant.
ADA4530-1
Data Sheet
HUMIDITY EFFECTS
The insulation resistance of the materials used to construct
circuits is sensitive to moisture. At lower temperatures (<70°C)
the insulation resistance creates more significant leakage
current errors than the amplifier itself. This means that the
relative humidity of the air is the most important error source at
lower temperatures. The dependence on humidity is evident in
the input bias current vs. temperature graphs (see Figure 34 to
Figure 36). There is significant deviation in the low temperature
measurements due to the difficulty maintaining a consistently
low relative humidity at low temperatures.
on Rogers 4350B PCBs (glass epoxy boards have poor humidity
absorption properties).
Figure 112 shows the effective input bias current vs. relative
humidity for seven characterization units. Figure 112 is plotted
with a split log axis to effectively show the magnitude and polarity
of the bias current. The magnitude of the leakage currents
changes by more than factor of 100 across the relative humidity
span from 5% to 80%. The effective bias current is much less
than 1 fA for typical conditioned environments (RH < 50%).
100
VSY = 10V
TA = 25°C
VCM = VSY/2
7 UNITS
10
To evaluate the humidity sensitivity of insulation resistance,
there are two mechanisms which must be considered:
adsorption and absorption.
1
IB (fA)
0.1
Adsorption is a process where thin films of molecules adhere to
the surface of a material. Water molecules are subject to this
process. The magnitude of the effect depends on the insulating
material and the relative humidity. Thin films of moisture are
conductive, and they act as leakage resistances in parallel with
the insulation resistance of the material. Because this is a
surface effect, guard ring techniques are effective at reducing it.
It is not possible to completely guard all the leakage paths: bulk
or surface. A relevant example of this limitation is the molding
compound of the SOIC package housing the ADA4530-1.
Surface and bulk paths exist from the input pins to all other
pins of the package. The nature of the resulting current depends
on the specific leakage path: paths to V+ increase the bias
current flowing out of the amplifier, paths to V− increase the
bias current flowing into the amplifier, and paths to VOUT lower
the effective feedback resistance in TIA circuits.
Consider the example of a circuit powered from ±5 V power
supplies with an input common-mode voltage of 0 V. Assume
that all of the leakage resistance between the input and V+ is
effectively 100 TΩ. This resistance creates a current equal to
50 fA flowing from V+. Assume that the leakage resistance
between the input and V− is effectively 250 TΩ. This resistance
creates a current equal to 20 fA flowing to V−. The net current
equals −30 fA flowing out of the input pin.
All of these leakage currents can be combined with the
amplifier input bias current and treated as an effective input
bias current. The effective input bias current sensitivity to
relative humidity of the ADA4530-1 is characterized for several
units. The test amplifiers are configured in TIA and unity buffer
circuits with 100 GΩ, hermetically sealed resistors (RX-1M1009FE)
as the feedback and source resistors, respectively. These glass
bodied resistors have a silicone coating (glass has poor humidity
adsorption properties). The ADA4530-1 amplifiers are mounted
–1
–10
–100
–1000
0
20
40
60
80
RELATIVE HUMIDITY (%)
13405-112
Absorption is a process where molecules enter the bulk of a
material. Water molecules can diffuse into a material and affect
the bulk conductivity of that material. Because the leakage paths
are through the bulk of the material, guard rings are not
effective at reducing it.
–0.1
Figure 112. Effective Input Bias Current vs. Relative Humidity
The magnitude of the effective input bias current becomes very
sensitive to the relative humidity at higher humidity levels
(>60%). Some of the units show an exponential dependence on
humidity (see the blue curve in Figure 112). Other units show a
less predictable dependence; the leakage current magnitude
increases rapidly, but the polarity can change. The net leakage
current is the sum of the currents sourced from higher voltages
(like V+) with the currents sunk by lower voltages (like V−). As
the humidity changes, the relative magnitudes of each of these
leakage paths can change, which can result in changes in the
polarity of the leakage current (see the red and green curves in
Figure 112).
The response time of these leakage currents depends on the
physical process that causes them. Because adsorption is a
surface effect, the film thickness rapidly achieves equilibrium
with changes in the relative humidity of the air. Because
absorption is a bulk diffusion process, it is very slow compared
to the adsorption process.
These widely different time constants mean that the effective
input bias current responds quickly to a step change in relative
humidity, but has a very long settling time. The step response of
one amplifier to a 50% to 60% relative humidity change is
shown in Figure 113. The high frequency response of the initial
humidity step (and the overshoot recovery) is on the order of
seconds to tens of seconds. Complete settling takes over a week
as the moisture slowly diffuses through the PCB insulation and
package molding compound. Note that each data point in
Figure 112 was taken after one week of settling time.
Rev. A | Page 36 of 50
Data Sheet
ADA4530-1
In practical applications, the relative humidity of the air changes
rapidly with daily and seasonal variations. The effective input
bias current response to these humidity changes has two parts.
The response due to the adsorption process follows the rapid
changes immediately. The response due to the absorption
process low-pass filters the humidity changes. This low-pass
response causes the effective input bias current to have longterm memory of the relative humidity fluctuations.
In summary, the ADA4530-1 can be designed using the specified
performance for normal laboratory (<60%) relative humidity
conditions. In applications that must operate in uncontrolled or
high humidity environments, some additional derating of the
input bias current is prudent. Characterize the amount of derating
on a per product basis because the net leakage depends on the
material types and physical dimensions of the insulators.
In this environment, measurements of the effective input bias
current appear to drift with time because the leakage currents
depend on the relative humidity for the previous week. This
long-term memory due to the absorption process may need to
be taken in account in certain circumstances (that is, long-term
product storage in an unconditioned high humidity environment prior to use).
The effective insulation resistance of an electrometer circuit can
be substantially degraded if the insulators are contaminated.
Solder flux, body oils, dust, and dirt are all possible sources of
contamination. Some of these contaminants form a parallel
leakage path across the surface of the existing insulator effectively lowering the insulation resistance. Guarding techniques
help to suppress these effects.
The rapid adsorption response can change the effective bias
current in response to local fluctuations in humidity. These
current fluctuations can be much larger than the low frequency
current noise of the amplifier and thermal noise of the resistors.
The sensitive circuitry can be isolated from these local humidity
fluctuations by restricting the airflow around the circuitry with
an air baffle. Electrostatic shielding added to reduce interference can also function as an air baffle. Remove or reduce the
sources of humidity fluctuations whenever possible. Avoid
breathing on the high impedance circuitry, for example.
The effects are more severe when the source of contamination
contains ionic compounds. In the presence of humidity, these
contaminates act as an electrolyte, which can form a weak
battery. Flux residue and body oils are particularly effective at
creating these parasitic batteries.
60
2
VSY = 10V
TA = 25°C
50
VCM = VSY/2
0
40
–2
30
–4
20
10
–6
RELATIVE HUMIDITY
IB
–8
0
25
50
75
100
125
ELAPSED TIME (Hours)
150
0
175
13405-402
IB (fA)
4
RELATIVE HUMIDITY (%)
70
6
Figure 113. Effective Input Bias Current Transient Response to Humidity Step
It is important to note that all electrometer circuits are subject
to humidity effects. The legacy circuits constructed with TO-99
packages using air wiring techniques have insulator leakage paths
such as the epoxy between the pins and the Teflon® standoffs used
to support the air wired components. The input bias currents of
legacy amplifiers are high enough to mask the humidity effects.
CONTAMINATION
As an example, the PCB insulation between two high impedance nodes was purposefully contaminated with a 3 mm drop of
rosin mildly activated (RMA) type solder flux. This sample was
dried and allowed to stabilize in laboratory conditions (25°C,
40% RH) for several days. After this time, the voltage vs. current
relationship was measured with an electrometer grade SMU
(see Figure 114).
This contamination formed a weak battery with an open circuit
voltage (VBATT) of 15 mV and an output resistance (RBATT) of
300 GΩ. This sort of contamination is disastrous in electrometer circuits because guarding techniques cannot suppress it. A
simplified model is made with the contamination battery applied
across the A terminal and B terminal of a TIA circuit (see
Figure 115). The A terminal and B terminal are both driven to
the same voltage, which creates an error current (IBATT) because
the open circuit battery voltage is dropped across the output
resistance as follows:
IBATT = VBATT ÷ RBATT
All of this battery current flows through the feedback resistance,
where it is summed with the signal and other error currents in
the circuit. The error current in this example is 50 fA. The battery
characteristics are subject to the environmental conditions;
therefore, the error current drifts with time, temperature, and
humidity.
Rev. A | Page 37 of 50
OUTPUT CURRENT (fA)
ADA4530-1
Data Sheet
400
CLEANING AND HANDLING
300
The contamination described in the Contamination section can
usually be removed by an appropriate cleaning process. Solvents
like isopropyl alcohol (IPA) are effective at removing the residue
from solder fluxes and body oils. Use high purity cleanroom
grade solvents to ensure that there is no additional contamination from the solvent itself.
200
100
0
–100
–200
–400
–100
–80
–60
–40 –20
0
20
40
APPLIED VOLTAGE (mV)
60
80
13405-319
–300
100
Figure 114. Current to Voltage Response of RMA Contaminated Insulation
IBATT
RF
ADA4530-1
A
B
The residual moisture must be allowed to completely evaporate
before the insulator can be used. This evaporation may take
many hours at room temperature; the process can be accelerated
by baking the insulators in an oven at elevated temperature.
For detailed cleaning and handling procedures, refer to the
ADA4530-1R-EBZ User Guide.
8
RBATT
BATTERY
MODEL V
BATT
Insulators that are severely contaminated benefit from mechanical abrasion in addition to the solvent. Ultrasonic cleaners are
highly effective. Scrubbing the area around the high impedance
insulators with an acid brush also works. Flush the insulators
with a final wash of fresh IPA to remove any contaminants
suspended in the solvent.
6
SOLDER PASTE SELECTION
VOUT
13405-312
1
Figure 115. TIA Circuit with Contamination Battery
Solder paste selection can drastically impact the performance of
the board if not cleaned properly. Solder flux residue on a PCB
degrades the low IB performance of the amplifier. An experiment
was performed to evaluate the cleaning procedure for different
solder paste types. Table 7 shows the result of the experiment.
The recommended cleaning procedure column lists the times
required to restore the effective input bias currents to less than
1 fA. The suggested solder paste of choice is the RMA type.
Table 7. Recommended Cleaning Procedures for Different Solder Paste Material
Solder Paste Type
RMA
Solder Paste Part Number
AIM RMA258-15R
Water Soluble
SAC305 Shenmao
No Clean
SAC 305 AMTECH LF4300
1
Recommended Cleaning Procedure1
15 min clean time in an ultrasonic cleaner with fresh IPA, followed by 1.5 hours
of bake time at 125°C
1.5 hours clean time in an ultrasonic cleaner with fresh IPA, followed by 1.5 hours
of bake time at 125°C
3 hours clean time in an ultrasonic cleaner with fresh IPA, followed by 3 hours of
bake time at 125°C
Bake time was not optimized and was set equal to the cleaning time.
Rev. A | Page 38 of 50
Data Sheet
ADA4530-1
CURRENT NOISE CONSIDERATIONS
The current noise from an amplifier input pin is important
when it flows through an impedance and generates a voltage
noise. If the current noise and impedance are large enough, the
resulting voltage noise can dominate the other noise sources in
the circuit such as the voltage noise of the resistors and amplifier.
For an electrometer amplifier such as the ADA4530-1, the
typical circuit impedances are so large that the current noise of
the amplifier can be the most important noise source.
To measure current noise, it is necessary to flow the noise
current through a test impedance large enough that the
resulting noise voltage is larger than the other noise voltages in
the circuit. Practically, this test impedance is usually a resistor.
All resistors have their own thermal noise. The value of thermal
noise is usually presented as an output referred voltage noise
spectral density (NSD), VNRTO.
VNRTO = √(4kTR)
where:
k is Boltzmann’s constant.
T is the temperature in Kelvin.
R is the resistance value.
The resistor thermal noise can be interpreted as a current NSD
by dividing the thermal noise with the resistance value, R, per
Ohm’s Law.
Table 8 shows the thermal noise of a series of resistor values
presented as both voltage and current noise. The current noise
of a resistor decreases as the resistance increases. This surprising
result illustrates that it is necessary to use high valued resistors
to measure low levels of current noise.
Table 8. Resistor Thermal Noise
Resistor Value
1 MΩ
100 MΩ
10 GΩ
1 TΩ
Voltage Noise
128 nV/√Hz
1.28 μV/√Hz
12.8 μV/√Hz
128 μV/√Hz
Current Noise
128 fA/√Hz
12.8 fA/√Hz
1.28 fA/√Hz
128 aA/√Hz
The measurement setup used to gather the current noise data is
shown in Figure 116. The ADA4530-1 is configured as a TIA
with a large value feedback resistor, RF. All amplifier current
noise from the inverting input flows through Resistor RF to
produce a voltage noise at VOUT.
CF
RF
ADA4530-1
The output referred voltage NSD, VNRTO, is sampled by the SR785
high performance dynamic signal analyzer (DSA) and is equal
to the root-sum-square of the amplifier current noise multiplied by
RF, the resistor thermal noise, and amplifier voltage noise.
VNRTO = √((IN−RF)2 + 4kTRF + VN2)
where:
IN− is the amplifier inverting current noise.
4kTRF is the resistor thermal noise.
VN2 is the amplifier voltage noise.
Calculate the current noise of the amplifier from VNRTO as follows:
IN  
VNRTO 2  4kTRF  VN 2
(1)
RF
For Equation 1 to be valid, the measured noise must be somewhat
larger than the resistor thermal noise plus the amplifier voltage
noise. In practice, ensure that the resistor current noise is less
than or equal to the amplifier current noise. For example, if the
amplifier noise is expected to be 2 fA/√Hz, use a value of RF that
is at least 10 GΩ, according to Table 8.
The amplifier voltage noise is not a concern at most frequencies
because the resistor thermal noise is much larger than the amplifier
voltage noise. At very low frequencies, this assumption is not
valid due to the 1/f characteristic of the amplifier voltage noise.
It is important to consider the bandwidth limitations of the
current noise measurement system shown in Figure 116. The
presence of stray capacitance makes it impossible to maintain
the high impedances required for the measurement. All stray
capacitance that couple the amplifier output to the inverting
input can be lumped into a single capacitor, CF, as shown in
Figure 116.
The current noise must pass through RF to become voltage
noise. However, in practice, the current noise passes through
the parallel combination of RF and CF to become voltage noise.
At frequencies higher than the RFCF pole, most of the noise current
flows through the capacitor and current noise calculations at
these frequencies are error prone due to the distributed parasitic
nature of CF. A good guideline is to set the measurement bandwidth limit equal to the RFCF pole frequency.
The measurement bandwidth limitations for high valued resistors
can be surprisingly low. Table 9 shows the −3 dB bandwidth of a
series of resistor values with a practical minimum stray capacitance
value.
Table 9. Bandwidth Limitations
SR785
DSA
13405-305
VOUT
Figure 116. Current Noise Measurement Setup
Resistor Value
1 MΩ
100 MΩ
10 GΩ
1 TΩ
Rev. A | Page 39 of 50
Capacitor Value
100 fF
100 fF
100 fF
100 fF
−3 dB Bandwidth
1.59 MHz
15.9 kHz
159 Hz
1.59 Hz
ADA4530-1
Data Sheet
Current Noise Density
128 aA/√Hz
1.28 fA/√Hz
12.8 fA/√Hz
128 fA/√Hz
Bandwidth
1.59 Hz
159 Hz
15.9 kHz
1.59 MHz
Table 10 demonstrates the error of the often claimed 0.1 fA/√Hz
at 10 kHz presented in the specifications of low input bias
current amplifiers. Measuring this value requires a 1 TΩ resistor
with less than 15.9 aF (15.9 × 10−18 F) of stray capacitance,
which is impossible.
These kinds of claims are simply shot noise calculations based
on the specified input bias currents of a few tens of femtoamperes.
Calculate the shot noise of a semiconductor as follows:
Shot Noise = √(2qIB)
where:
q is the charge on an electron.
IB is the current flowing through a junction.
Shot noise calculations are appropriate only for some legacy
JFET-based electrometer amplifiers, where only a single
junction is connected to the amplifier input pins. Modern high
impedance amplifiers have several semiconductor junctions
connected to the amplifier input pins. The most significant of
these junctions are the ESD diode structures. The input bias
currents are equal to the sum of these diode currents. The diode
currents are designed to cancel each other, but the shot noise
currents are uncorrelated and cannot cancel, which, in turn,
makes calculating the shot noise from the input bias current
impossible.
Even when appropriate, these shot noise calculations neglect all
capacitive coupling effects so that they are valid only at very low
frequencies. The gate to source capacitance of the input transistors couples noise currents from sources other than the input
junctions for frequencies above a few tens of hertz. This blowback
noise effect is present in all amplifiers, and it ensures that the
current NSD always increases as frequency increases.
The complex relationship between current noise, feedback
resistance, and bandwidth means that the proper way to
characterize the current noise of an electrometer amplifier is by
measuring the output NSD with a variety of feedback resistors
that cover the entire span of values used in the end applications.
Each feedback resistor establishes a boundary for the minimum
measurable current noise over a range of frequencies.
Resistor Value
100 MΩ
1 GΩ
10 GΩ
100 GΩ
1 TΩ
Manufacturer
Vishay
Ohmite
Ohmite
Ohmite
Ohmite
Device Number
RNX050100MDHLB
RX-1M1007GE
RX-1M1008JE
RX-1M1009FE
RX-1M100AKE
Figure 117 shows the output referred voltage NSD (VNRTO) of
the transimpedance test circuit for the test resistors listed in
Table 11. The calculated thermal noise for each resistor is
represented with the dashed line. The black dashed line
represents the 1/f voltage noise of the amplifier.
VSY = 10V
AV = +1
1TΩ
100
100
100GΩ
10GΩ
10
10
1GΩ
100MΩ
1/f
1
0.001
0.01
0.1
1
10
100
FREQUENCY (Hz)
1k
10k
1
100k
INPUT SERIES RESISTOR THERMAL NOISE (µV/√Hz)
Table 10. Measurement Current Noise Density vs. Bandwidth
Table 11. Test Resistor Device Numbers
13405-306
It is useful to construct a table that combines the resistor noise
and measurement bandwidth guidelines. Table 10 shows the
approximate bandwidth limitations for a variety of input
current noise measurements.
It is critically important to use high quality resistors during this
measurement. Many high valued resistors designed for high
voltage operation are nonlinear at low voltage levels and are not
suitable for electrometer work. Inferior resistors may also have
their own 1/f noise that corrupts the measurement results. Table 11
lists the resistors used for the characterization of the ADA4530-1.
TOTAL OUTPUT VOLTAGE NOISE DENSITY (µV/√Hz)
Reconsider the example amplifier with 2 fA/√Hz of current
noise. The required RF value of 10 GΩ also limits the
measurement bandwidth to 159 Hz according to Table 9.
Figure 117. Transimpedance NSD Referred to Output
VNRTO is dominated by the resistor noise for all of the test
resistors up 1 TΩ. This means that the current noise contribution from the ADA4530-1 is insignificant relative to the thermal
noise of these resistors.
It is possible to calculate the current noise of the ADA4530-1
with the 1 TΩ resistor. This result is shown in Figure 118. It is
impossible to calculate the amplifier current noise for all of the
other resistors. The most that can be said is that the amplifier
current noise is much less than the resistor noise. The current
noise densities of each of the test resistors are plotted as dashed
lines in Figure 118. The current noise of the ADA4530-1 is
below the resistor noise values.
Rev. A | Page 40 of 50
Data Sheet
Figure 120 shows the equivalent noise resistance vs. temperature.
From Figure 120, it is simple to determine that the ADA4530-1
contributes less noise than a 1 TΩ resistor for temperatures less
than 40°C. If the application requires 85°C operation, the
ADA4530-1 contributes as much noise as a 30 GΩ resistor. This
example illustrates the considerable impact that temperature
plays in determining the noise performance of an application.
100MΩ
10
1GΩ
10GΩ
1
100GΩ
10T
0.01
0.1
1
10
100
FREQUENCY (Hz)
1k
10k
100k
Figure 118. Current Noise Spectral Density
The current noise of the ADA4530-1 originates from the
saturation current of the ESD diodes. The diode saturation
current has an exponential dependence on temperature;
therefore, it is expected that the current noise tracks this
temperature behavior. The current noise of the ADA4530-1 is
characterized over temperature using the transimpedance
measurement circuit with a 1 TΩ resistor. The measurements
are limited to 85°C because of the maximum operating
temperature of the resistor. Figure 119 shows the current noise
density at a frequency of 0.1 Hz for all of the test temperatures.
It can be useful to calculate an equivalent noise resistance from
the current noise density data in Figure 119. This conversion
facilitates comparisons between the current noise generated by
the ADA4530-1 and the thermal noise of the feedback resistor
used in the circuit.
EQUIVALENT NOISE RESISTANCE (Ω)
0.1
0.01
0.001
400
300
200
20
30
40
50
60
TEMPERATURE (°C)
70
80
90
13405-308
100
10
20
30
40
50
60
TEMPERATURE (°C)
70
80
90
In summary, the excellent noise performance of the ADA4530-1
makes it ideal for electrometer applications. For impedances
less than 1 TΩ, the amplifier noise is negligible. Also, unlike
other amplifiers, the current noise has been fully characterized
and is free of excessive blowback noise.
500
0
10
Figure 120. Equivalent Noise Resistance vs. Temperature
600
0
100G
0
VSY = 10V
f = 0.1Hz
700
1T
10G
800
CURRENT NOISE DENSITY (aA/√Hz)
f = 0.1Hz
1TΩ
13405-309
VSY = 10V
AV = +1
13405-307
CURRENT NOISE DENSITY (fA/√Hz)
100
ADA4530-1
Figure 119. Current Noise Density vs. Temperature
Rev. A | Page 41 of 50
ADA4530-1
Data Sheet
LAYOUT GUIDELINES
PHYSICAL IMPLEMENTATION OF GUARDING
TECHNIQUES
impedance insulation. A gap of 15 mil between the A trace and
the guard ring is sufficient.
In the Guarding section, guarding was introduced as a technique fundamental to high impedance work. The goal of
guarding is to completely surround the insulation of high
impedance node with another conductor that is driven to the
guard voltage. This ideal is impossible to achieve in practice;
however, there are several practical structures that provide good
performance.
Another simplified layout demonstrates the implementation of
a guard ring in the TIA circuit (see Figure 122). The guard ring
is implemented in the same manner as the buffer circuit. The
primary difference is that the left half of the feedback resistor
(RF) and feedback capacitor (CF) are connected to the high
impedance node. The guard ring shape is extended around
these passive components to ensure that the entire high
impedance node is surrounded by guard. The guard ring is
directly driven from the ADA4530-1 guard buffer (Pin 7).
A guard ring is a structure typically used to implement the
guarding technique on the surface of the PCB. A simplified
layout of the buffer circuit implements the guard ring around
the high impedance (A) trace (see Figure 121). The output of
the voltage sensor is wired directly to the A and B pads in
Figure 121. The guard ring is a filled copper shape that
completely surrounds the high impedance (A) trace from the
sensor connection to the noninverting input (Pin 1). The guard
ring is driven directly from the ADA4530-1 guard buffer (Pin 2)
through a thermal relief shape connection. It is not necessary to
connect the other guard buffer output (Pin 7).
The solder mask was removed from the high impedance trace
and the guard trace to ensure that the guard makes electrical
contact with any surface leakage paths. For the same reason,
avoid printing any silkscreen in this section.
VOUT
RF
V+
A
C+
GUARD
GND
ADA4530-1
B
C–
V–
Figure 122. TIA Circuit Layout
RF
VOUT
V+
The guard voltage in the TIA circuit is nominally equal to the B
voltage, which makes it possible to drive the guard ring directly
from the B voltage without using the ADA4530-1 guard buffer.
When implementing the guard ring this way, do not make any
connection to the guard buffer outputs (Pin 2 and Pin 7).
GND
GUARD PLANE
V–
A guard plane is a structure used to implement the guarding
technique through the bulk of the PCB. The structure of the
guard plane is shown in a cross section of the PCB (see Figure 123).
The guard plane is a filled copper shape that is placed directly
below the high impedance (A) trace. This plane is connected to
the guard ring on the surface layer with vias.
RS
C+
B
ADA4530-1
C–
A
CF
13405-321
GUARD RING
13405-320
GUARD
Figure 121. Buffer Circuit Layout
There is not a large amount of exposed insulation between the
A trace and the guard ring. It is often counterproductive to
increase this spacing to try to increase the insulation resistance
because the exposed insulator tends to accumulate surface
charges generated from piezoelectric or triboelectric effects.
These charges are eventually swept across the insulator toward
the high impedance conductor. The magnitude of this error
current is dependent on the area of the exposed high
If the circuit board is constructed using high performance PCB
laminates such as Rogers 4350B, a hybrid stackup is required for
mechanical strength. The outside layers are ceramic, whereas the
core layers are conventional glass epoxy laminate. It is important to
place the guard shield on the boundary of the ceramic and glass
epoxy materials to protect the high impedance node from the
poor dielectric relaxation characteristics of the glass epoxy
materials.
Rev. A | Page 42 of 50
Data Sheet
ADA4530-1
SOLDER MASK
Traditional electrical interferers are not the only sources of concern.
Calculate the displacement current, I, in a capacitor as follows:
SOLDER MASK
GUARD
A
GUARD
ROGERS
4350B
I C
GUARD
13405-322
FR-4
Figure 123. Layout Cross Section with Guard Plane
VIA FENCE
A via fence is an additional structure that guards the lateral
leakage paths in the laminate between the guard ring and the
guard plane (see Figure 123). The fence is implemented by
surrounding the entire guard ring with vias that connect the
guard ring to the guard plane (see Figure 121 and Figure 122).
CABLES AND CONNECTORS
Guarding techniques are required for all of high impedance
wiring; not just on the PCB. Frequently, the high impedance
sensor is not directly mounted on the PCB with the electrometer amplifier and external cables are used to make the connection.
The typical way to guard a cable connecting to a current output
sensor is by using a coaxial cable. A coaxial cable consists of an
inner conductor surrounded with insulation, which is, in turn,
surrounded by a braided conductor. Use the inner conductor
for the high impedance (A) terminal and the outer braided
shield conductor for the low impedance (B) terminal. Conveniently, this arrangement effectively guards the coaxial insulation
resistance because the A terminal and B terminal are nominally
at the same voltage (when attached to a TIA interface circuit).
Voltage output sensors are more problematic because the A
terminal and B terminal are not at the same voltage. The typical
way to guard the voltage output sensor cable is to use triaxial
cable. Triaxial cable is constructed with an inner conductor with
two separate braided conductors. Each of these braided
conductors is separated from each other with insulation. Use
the inner conductor for the high impedance (A) terminal and
the inner braided conductor for the guard (VGRD) connection,
and use the outer braided conductor for the low impedance (B)
terminal. All the insulation around the inner conductor is
completely surrounded by the guard conductor, which keeps the
voltage drop across this insulation equal to zero.
ELECTROSTATIC INTERFERANCE
Very high impedance electrometer circuits are susceptible to
interference through capacitive coupling. The amount of capacitance required to couple low frequency signals is surprisingly
small. For example, line frequency (60 Hz) interference is
coupled (with a −3 dB loss) to a 1 TΩ impedance with only 3 fF
of coupling capacitance.
V
C
V
t
t
(2)
The second term in this equation is frequently ignored in most
circuits, but it can generate some unusual problems in electrometer circuits. The problem is that the movement of any charged
object changes the coupling capacitance between the object and
the electrometer, and this change in capacitance injects small
currents into the circuit. The ADA4530-1 is so sensitive that it
easily detects the movement of a hand or the movement of a
piece of paper. These types of effects are not periodic or
predictable, and they can appear as erratic dc shifts on the time
scales of interest.
Both of these types of interference can be reduced by the
addition of a shield. A shield is a piece of conductive material
placed between the high impedance input and the interference
source. This shield must be electrically connected to a low
impedance source (such as signal ground). If the shield physically interrupts all of the capacitive coupling paths, all of the
displacement current from the interference source is shunted to
the low impedance source.
Notice that the construction of a shield is almost the same as
the construction of a guard. Because of this similarity, many
guard structures also provide shielding as well. The primary
difference is that the dc voltage of the shield is not important,
whereas the guard must have a voltage equal to that of the high
impedance input. Shields that are driven by the guard buffer
have the added benefit of bootstrapping the capacitance between
the high impedance input and the shield. The disadvantage of
this approach is that the guard buffer output impedance is 1 kΩ,
which makes the shield less effective than a signal ground or a
chassis ground connection. The most effective systems typically
use the box within a box construction: the outer shield is driven
with ground and the inner shield is driven with guard.
There is another capacitive interference effect that typically
cannot be shielded. This displacement current is generated from
a change in capacitance with respect to time (the second term of
Equation 2). This change is due to the mechanical movement of
the circuit components. This movement, which can be caused
by mechanical impact or vibration, generates electrical interference.
This interference typically appears at unexpected frequencies
that are equal to the mechanical resonances of the components.
This effect must be considered when using traditional air wiring
techniques for large feedback resistors or relays. It is important
to ensure solid mechanical connections to Teflon standoffs for
this type of construction.
Rev. A | Page 43 of 50
ADA4530-1
Data Sheet
PHOTODIODE INTERFACE
The low input bias current and low input offset voltage makes
the ADA4530-1 an excellent choice for signal conditioning
photodiodes at extremely low illumination levels. Figure 124
shows the ADA4530-1 configured in a transimpedance amplifier interfacing with a photodiode operating in photovoltaic
mode (photodiode is zero biased). A photodiode produces an
output current proportional to the illumination level. The
amplifier converts the signal current, IPD, into an output voltage
with the following equation:
ture. An error current is created because the amplifier offset
voltage is applied across this shunt resistance, resulting in an
RTI error equal to
IVOS_RTI = VOS/RSHUNT
It is equivalent to think that the shunt resistance increases the
DC noise gain which multiplies the offset voltage to the output.
The RTO error due to VOS is equal to:
VOS_RTO = VOS × Noise Gain
VOS_RTO = VOS × (1 + RF/RSHUNT)
VOUT = IPD × RF
CF
The amplifier input resistance and insulation resistance appear
in parallel with the photodiode shunt resistance. These additional resistances reduce the effective shunt resistance, but they
are much larger than the photodiode shunt resistance and can
usually be ignored.
RF
VOUT
PHOTODIODE
13405-323
IPD
AC ERROR ANALYSIS
Figure 124. Transimpedance Amplifier with Photodiode
Figure 125 replaces the photodiode with an equivalent circuit
model. IPD is the photo current generated by incident light and
is proportional to the light level. The shunt capacitance (CSHUNT)
models the depletion capacitance of the diode. This capacitance
depends on the area of the photodiode and the voltage bias. The
shunt resistance (RSHUNT) represents the voltage vs. current slope
of the exponential diode curve near zero bias voltage.
CF
PHOTODIODE
CSHUNT
The classic way of analyzing this circuit is by examining the
noise gain vs. frequency (see Figure 126). At low frequencies,
the noise gain is determined by the ratio of the feedback to the
shunt resistance.
VOUT
RSHUNT
13405-324
IPD
RF
Photodiode TIA circuits typically require external compensation to
give satisfactory dynamic performance. The large feedback
resistor (RF) interacts with the large photodiode capacitance
(CSHUNT) to create a low frequency pole in the feedback network.
Photodiode shunt capacitance, amplifier input capacitance, and
trace capacitance are lumped into a single element, CSHUNT. The
phase shift due to this pole must be recovered prior to the
crossover frequency for the feedback loop to be stable. The
usual method to recover this phase shift is to create a zero in the
feedback factor with the addition of the feedback capacitor (CF).
NG1  1 
Figure 125. Transimpedance Amplifier with Photodiode Model
DC ERROR ANALYSIS
All of the errors described in the High Impedance Measurements
section related to TIA circuits are applicable to photodiode
interfaces.
The inverting input bias current, IB−, sums directly with the
photodiode current for a referred to input (RTI) error equal to
IB−. This current flows through the feedback resistor, creating a
referred to output (RTO) error equal to
VIB_RTO = IB− × RF
The amplifier offset voltage, VOS, is a major error source in
photodiode interface circuits because of the relatively low shunt
resistance of large area photodiodes. Typical values are in the
range of 1 GΩ to100 GΩ at 25°C. More importantly, the shunt
resistance decreases by half for every 10°C increase in tempera-
RF
RSHUNT
The troublesome low frequency pole (which is a zero in the
noise gain) occurs at Frequency f1. From this frequency onward,
the noise gain increases. If there is no feedback capacitor in the
circuit, the noise gain follows the dotted line until it intersects
with the amplifier open-loop gain curve. If these curves
intersect at the 20 dB/decade slopes shown in Figure 126, the
circuit is unstable.
The addition of CF adds a zero to the feedback factor (which is a
pole in the noise gain) at Frequency f2. Beyond Frequency f2, the
noise gain is determined by the ratio of the shunt capacitance to
the feedback capacitance.
Rev. A | Page 44 of 50
NG 2  1 
C SHUNT
CF
Data Sheet
ADA4530-1
OPEN-LOOP GAIN
GAIN (dB)
IF CF = 0fF
SIGNAL BANDWIDTH
CLOSED-LOOP BANDWIDTH
NG 2
NOISE GAIN
FREQUENCY (Hz)
f1
f2
f3
fUGC
13405-325
NG1
Figure 126. Transimpedance Noise Gain vs. Frequency
For completeness, the noise gain equations are as follows:
NOISE ANALYSIS
 2f 1 
 

 RF  f1


NG( f )  1 
 2f

R
S


1
 f2

f1 
Photodiode TIA circuits have four noise sources that must be
considered:




1
RF RSHUNT
CF  CSHUNT 
RF  RSHUNT
1
f2 
RF C F
For simplicity, bandwidth limitations are ignored in the noise
gain equations. The noise gain starts to roll-off when it
intersects with the open-loop gain of the amplifier. This pole
frequency (f3) is determined by the unity gain crossover
frequency (fUGC) of the amplifier and the high frequency noise
gain, NG2, as follows:
f3 
fUGC
 CSHUNT 
1 


CF 

(3)
The addition of CF has an impact on the signal frequency
response. At low frequencies, the transimpedance gain is equal
to RF. As the frequency increases, the impedance of CF drops
below RF and starts to reduce this transimpedance gain. This
signal gain equation is as follows:




1 

Signal Gain( f )  RF

 2f
 f 1

 2
The thermal noise of the feedback resistor (RF)
The saturation current noise of the photodiode
The current noise of the amplifier
The voltage noise of the amplifier
The noise contributions of these sources are typically referred to
output for analysis. The thermal noise of RF appears directly at
the output. This noise is filtered by the feedback capacitance so
that its −3 dB bandwidth is the same as the signal bandwidth (f2).
The photocurrent of a photodiode, IPD, produces shot noise equal to
INPD = √(2qIPD)
It is a mistake to assume that the noise goes to zero as the diode
current goes to zero. Zero net current out of the diode simply
means that the saturation current flowing in one direction is at
thermal equilibrium with the saturation current flowing in the
opposite direction. These currents are uncorrelated and add in a
root sum square fashion. This net current noise is equivalent to
the thermal noise of a physical resistor with a value of RSHUNT.
This convenient fact allows the photodiode to be accurately
modeled with a simple resistor, RSHUNT. The thermal noise of
RSHUNT is amplified by the ratio of the feedback resistance to the
shunt resistance. This noise is also filtered to the signal bandwidth.
The current noise of the amplifier flows through the feedback
resistor to become a noise voltage at the output. It is subject to
the same bandwidth limitations as the previous noise contributors.
The voltage noise of the amplifier is multiplied by the noise gain
of the circuit to the output. This noise source is significant for
two reasons. First, the high frequency noise gain can be high
due to the large ratio between the shunt capacitance and the
feedback capacitance. Second, the voltage noise bandwidth is
much higher than the other contributors. The noise bandwidth
is limited only by bandwidth of the amplifier.
Rev. A | Page 45 of 50
ADA4530-1
Data Sheet
Each of these noise contributors is graphed vs. frequency in
Figure 127. A summary of the noise sources and their RTO
contributions is shown in Table 12. The total RTO noise adds
the contributions of each noise source in root sum square.
100
The signal bandwidth increases as the feedback capacitance (CF)
decreases. The lower limit for CF is typically limited by one of
the following:
RF
RSHUNT
NSD (µV/√Hz)

10

IN–
VN
1


0.1
1
f2
f3
10
100
1k
FREQUENCY
13405-404
f1
improving. The photodiode noise is higher than the
amplifier current noise in nearly all practical photodiodes.
The low frequency noise gain due to RSHUNT. When RF is
larger than RSHUNT, the noise gain multiplies VOS and TCVOS
errors and the signal to error ratio stops improving.
Figure 127. Photodiode TIA RTO Noise Spectral Density
Parasitic feedback capacitances limit the minimum value of
CF to 50 fF to 100 fF.
Available component values. Physical components can be
found in surface mount packages for values from 0.1 pF to
1 pF in 100 fF increments.
Feedback loop stability. CF must be large enough to recover
enough phase shift prior to the loop crossover for stable
operation. This capacitance value can be a significant
consideration for smaller values of RF. Large values
(>1 GΩ) tend to be self compensating through the parasitic
feedback capacitance.
High frequency noise gain. The high frequency noise gain
is set by the ratio of CSHUNT to CF. For very large noise gains,
it is possible for the amplifier voltage noise to be greater
than the feedback resistor noise.
Table 12. Photodiode Interface Noise Sources

Noise Source
RF
Photodiode
IN− Amplifier
VN Amplifier
DESIGN EXAMPLE
RTO Noise
√(4kTRF)
(RF/RSHUNT)√(4kTRSHUNT)
RF × IN−
VN × noise gain
Noise Bandwidth
π/2 × f2
π/2 × f2
π/2 × f2
π/2 × f3
DESIGN RECOMMENDATIONS
The design goal for a large area photodiode TIA circuit is
usually to maximize SNR and minimize dc errors. Increasing
the feedback resistor size accomplishes both goals. The signal
gain increases directly with RF, whereas the noise increases in a
square root fashion. High gains also make the output signal
large relative to output voltage errors (such as VOS).
The upper limit for RF is typically determined by one of the
following:




Amplifier output swing. The maximum photocurrent
multiplied by RF must be less than amplifier swing
limitations.
Signal bandwidth (or settling time). Signal bandwidth is
dependent on RF × CF. Achieving high signal bandwidths
with large feedback resistors can require vanishingly small
feedback capacitors to implement. The ultimate limitation
is due to the parasitic feedback capacitance from the
fringing electric fields in the circuit. Parasitic capacitances
in the 50 fF to 100 fF range are possible. To put this in
perspective, a 100 fF parasitic capacitance limits the signal
bandwidth of a 100 GΩ TIA to 16 Hz.
The thermal noise of the photodiode (RSHUNT). When RF is
significantly larger than RSHUNT, the total noise is dominated by the photodiode and the SNR stops improving.
The current noise of the amplifier. When the current noise
of the amplifier is larger than the noise of RF, the SNR stops
In this section, an example TIA circuit is designed using a
photometry grade photodiode (Hamamatsu S1226-18BQ). This
medium area (1.2 mm2) silicon photodiode is responsive in the
ultraviolet (UV) through visible frequency range. The minimum shunt resistance (RSHUNT) is specified at 5 GΩ at 25°C. The
shunt capacitance (CSHUNT) is specified at 35 pF. The quartz
window limits the maximum operating temperature to 60°C.
Based on the specified minimum shunt resistance and the
recommendations in the Design Recommendations section, a
value of 10 GΩ is chosen for RF. This example circuit is powered
from ±5 V with the input common-mode voltage set at 0 V, which
allows a maximum photocurrent of approximately 500 pA.
An error budget is constructed based on the DC Error Analysis
section (see Table 13). The amplifier offset voltage applies the
maximum temperature drift limit to the maximum room
temperature offset limit. The photo diode shunt resistance limit
is reduced by half for every 10°C.
Table 13. Photodiode Interface DC Error Budget
Error Source
VOS
RSHUNT
Noise Gain
VOS Error RTO
IB
IB Error RTO
Total Error RTO
Total Error RTI
Rev. A | Page 46 of 50
25°C
40 μV
5 GΩ
3
120 μV
20 fA
200 μV
320 μV
32 fA
45°C
40 μV + 10 μV
1.25 GΩ
9
450 μV
20 fA
200 μV
650 μV
65 fA
60°C
40 μV + 18 μV
442 MΩ
23
1.3 mV
20 fA
200 μV
1.5 mV
150 fA
Data Sheet
ADA4530-1
TRANSIMPEDANCE GAIN (GΩ)
This circuit was constructed as described with a 10 GΩ feedback resistor (Ohmite RX-1M1008JE). The dc error performance
was measured over the 25°C to 60°C temperature range (see
Figure 128). The error increases rapidly with temperature as the
shunt resistance changes the noise gain exponentially. The total
RTI error ranges from +2 fA to −10 fA, considerably lower than
the worst case error budget, as expected.
–2
–40
–4
–60
–6
–80
–8
–100
–10
–120
–12
70
0
10
20
30
40
TEMPERATURE (°C)
50
60
1
10
100
1k
FREQUENCY (Hz)
10k
Figure 129. Transimpedance Gain vs. Frequency
The stability improvement can be seen in the time domain as
well. The circuits step response to a 10 pA photocurrent is
shown in Figure 130. The uncompensated circuit (red curve)
shows considerable (20%) overshoot. The compensated circuit
(blue curve) is overdamped.
40
VSY = 10V
TA = 25°C
IPD = 10pA
20
0
Figure 128. DC Error vs. Temperature
The ac performance of the circuit was also measured. The
circuit was initially constructed without a physical feedback
capacitor as a baseline. The transimpedance gain vs. frequency
is shown in Figure 129. The 30% frequency peaking seen in the
frequency response (red curve) indicates that the feedback loop
is marginally compensated with parasitic capacitance.
A physical capacitor was added to improve the loop compensation. This capacitor is a 300 fF C0G ceramic in a Size 0805,
surface-mount package (AVX UQCFVA0R3BAT2A\500). C0G
ceramic capacitors are good candidates for electrometer circuits
because they have adequate insulation resistance and dielectric
absorption performance. These low valued capacitors are designed
for RF use and are readily available. The 300 fF capacitor eliminates the frequency peaking completely (blue curve) but it
reduces the −3 dB bandwidth from 390 Hz to 50 Hz.
100k
4
2
0
–20
–2
–40
–4
–60
–6
–80
–8
–100
–10
–120
–12
CF = 0fF
CF = 300fF
–140
0
5
10
INPUT REFERRED CURRENT (pA)
–20
CF = 0fF
CF = 300fF
15
20
25
TIME (ms)
30
35
–14
40
13405-400
0
1
0.1
0.1
OUTPUT VOLTAGE (mV)
RTO ERROR (µV)
0
2
RTI ERROR (fA)
VSY = 10V
VCM = VSY/2
13405-401
20
VSY = 10V
VCM = VSY/2
TA = 25°C
10
13405-407
The total RTI error over the entire temperature range is less
than 150 fA, which is equal to 300 ppm of the 500 pA full-scale
range. Note that the extraordinarily low input bias current of
the ADA4530-1 is not a significant contributor to the total error
over temperature. The interaction of the offset voltage with the
shunt resistance of the photodiode is the most significant error
source.
Figure 130. 10 pA Step Response
A noise budget is constructed based on the Noise Analysis
section. The RTO noise budget is separated into noise sources
integrated with a low bandwidth (see Table 14) and those
integrated with a high bandwidth (see Table 15).
The low frequency noise contributors include the feedback
resistance, the shunt resistance and the amplifier current noise.
Each of these sources has a −3 dB bandwidth equal to the signal
bandwidth (50 Hz); this is equivalent to a noise bandwidth of
79 Hz. The most significant noise source is the photodiode
shunt resistance by a large margin. The second most significant
source is the feedback resistor. The amplifier current noise is so
low that it can be ignored.
Rev. A | Page 47 of 50
60°C
13.5 μV/√Hz
442 MΩ
2.8 μV/√Hz
22
61 μV/√Hz
0.24 fA/√Hz
2.4 μV/√Hz
62 μV/√Hz
194 μV rms
345 μV rms
549 μV rms
The sole high frequency noise contributor is the amplifier
voltage noise, which is multiplied by the high frequency noise
gain and band limited only by the amplifier gain. The −3 dB
bandwidth of the amplifier is 17 kHz (refer to Equation 3,
where f3 = fUGC ÷ NG2 = 2 MHz ÷ 118). The equivalent noise
bandwidth is 27 kHz. The high bandwidth is the reason the
high frequency noise is significant even though the noise
spectral density is much lower than the low frequency noise.
Table 15. High Frequency Noise Budget
Error Source
VN
High Frequency
Noise Gain
VN_RTO
High Frequency
RMS Total
25°C
14 nV/√Hz
118
45°C
14.5 nV/√Hz
118
60°C
14.8 nV/√Hz
118
1.6 μV/√Hz
271 μV rms
1.7 μV/√Hz
281 μV rms
1.7 μV/√Hz
286 μV rms
At low temperatures, the amplifier voltage noise is more significant than any other noise source. This is important because the
majority of this noise occurs outside the useful bandwidth of
the circuit. For this reason, it is prudent to add a low-pass filter
to the output of a photodiode TIA circuit. This filter can be active
or passive depending on the needs of the system. A simple RC
filter with a −3 dB cutoff of 500 Hz has an insignificant impact
on the frequency response of the signal path, but it lowers the
integrated noise from 271 μV rms to 45 μV rms (a 6× reduction).
The NSD was measured for this circuit with (blue curve) and
without (red curve) the 300 fF CF capacitor (see Figure 131). At
low frequencies, the NSD is approximately equal to the noise
from the feedback resistor alone (12.8 μV/√Hz). The value of
the low frequency NSD shows that the shunt resistance is much
larger than the specified minimum (which is expected). As
frequency increases, the resistor noise rolls off at the signal
bandwidth (50 Hz). The NSD then plateaus at the amplifier
voltage noise level until the bandwidth limitations of the
amplifier roll off the NSD toward zero.
1000
10
100
1
0.1
NSD, CF = 0fF
NSD, CF = 300fF
RMS, CF = 0fF
RMS, CF = 300fF
1
10
100
1k
FREQUENCY (Hz)
10k
10
100k
13405-405
45°C
13.2 μV/√Hz
1.25 GΩ
4.7 μV/√Hz
8
37 μV/√Hz
0.15 fA/√Hz
1.5 μV/√Hz
39 μV/√Hz
VSY = 10V
VCM = VSY/2
TA = 25°C
Figure 131. RTO Noise Spectral Density (25°C)
The dashed curves show the integration of the NSD across the
frequency spectrum. These are useful to calculate the rms noise
over a variety of bandwidths. For example, the rms noise over
the entire 100 kHz measurement bandwidth is 400 μV rms,
which is approximately the same as the calculated total noise of
333 μV rms. If a postfilter is added with a noise bandwidth of
1 kHz, Figure 131 shows that the integrated noise is 200 μV rms
(a 2× improvement).
The uncompensated circuit (red curves) shows considerably
worse noise performance. The frequency peaking due to the
marginal loop stability multiplies the noise as well as the signal.
In addition, the high frequency noise gain is larger, which adds
much more noise outside the signal bandwidth. Both of these
effects together generate 1.2 mV rms of total noise. Even if the
transient and frequency response of an undercompensated TIA
are acceptable, the large noise penalty may not be.
Lastly, the NSD was measured for this circuit at 60°C (see
Figure 132). As expected, the low frequency noise increased as a
result of the photodiode shunt resistance. The average low
frequency NSD is 22 μV/√Hz. Removing the contribution of RF
gives an RTO contribution of 17 μV/√Hz, which is equivalent to
an RTI current noise of 1.7 fA/√Hz. RSHUNT must be approximately 6.5 GΩ at 60°C to generate this noise.
100
NSD, CF = 300fF
RMS, CF = 300fF
VSY = 10V
VCM = VSY/2
TA = 60°C
10
1
0.1
100
1
10
100
1k
FREQUENCY (Hz)
10k
Figure 132. RTO Noise Spectral Density (60°C)
Rev. A | Page 48 of 50
1000
10
100k
INTEGRATED VOTLAGE NOISE (µV rms)
25°C
12.8 μV/√Hz
5 GΩ
9 μV/√Hz
2
18 μV/√Hz
0.07 fA/√Hz
700 nV/√Hz
22 μV/√Hz
100
13405-406
Error Source
VNRF
RSHUNT
VNRSHUNT
RF/RSHUNT
VNRSHUNT_RTO
IN−
IN−_RTO
Low Frequency
NSD Total
Low Frequency
RMS Total
VOLTAGE NOISE SPECTRAL DENSITY (µV/√Hz)
Table 14. Low Frequency Noise Budget
INTEGRATED VOTLAGE NOISE (µV rms)
Data Sheet
VOLTAGE NOISE SPECTRAL DENSITY (µV/√Hz)
ADA4530-1
Data Sheet
ADA4530-1
POWER SUPPLY RECOMMENDATIONS
Analog Devices offers a wide range of power management
products to meet the requirements of most high performance
signal chains.
Examples of a single- and dual-supply solution is shown in
Figure 133. The ADP2370 and ADP5075, cascaded with the
ADP7118 or ADM7170, and the ADP7182 generate clean
positive and negative rails. These rails power the ADA4530-1,
electrometer amplifier and/or the precision converter in a
typical signal chain.
BUCK
REGULATOR
ADP5075
INVERTING
REGULATOR
3.3V
INPUT
15V/12V/6V
INPUT
ADP5070
BOOST AND
INVERTING
REGULATOR
ADM7170/
ADP7118
+8.5V
OR +6V
ADP7118
+7.5V
OR +5V
Figure 134 shows the combined PSRR of using the ADP7118 to
provide +5 V on +VSY of the ADA4530-1, and the ADP7182 to
provide –5 V on–VSY, from a 9 V battery main supply. Figure 135
shows the maximum allowable ripple at the input so that the
combined PSRR of the LDO and the amplifier can still attenuate
the noise level down to the noise floor.
LDO
–8.5V
OR –6V
ADP7182
–7.5V
OR –5V
LDO
+6V
ADP7118
For example, if the main supply to the ADP7118 and ADA4530-1
has a switching noise of 20 mV p-p at 300 kHz, Figure 135 shows
that it is below the maximum value of 90 mV p-p. Therefore,
the combined PSRR of the system can still attenuate and bring
the noise level down to the noise floor, in effect, the 300 kHz
noise at the input is not seen at the output of the amplifier.
+5V
LDO
–6V
ADP7182
–5V
LDO
+12V/+10V/+5V
LDO
For a dual-supply application, the ADA4530-1 typically needs a
±5 V supply, although in some applications, a ±2.5 V to ±8 V
supply can be used. LDOs like the ADP7118 or ADM7170 are the
optimum choices for the positive supply, and the ADP7182 for
the negative supply. In addition, if a negative supply is not already
available, the ADP5075 or the ADP5070 can generate the
negative supply from a positive supply, as shown in Figure 133.
0
Figure 133. Recommended Power Solutions
–20
Table 16. Recommended Power Management Devices
ADP5070
ADM7170
ADP7118
ADP7182
Description
800 mA, dc-to-dc inverting regulator
High voltage, 1.2 MHz/600 kHz, 800 mA, low
quiescent current buck regulator
1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
6.5 V, 500 mA, ultralow noise, high PSRR, CMOS LDO
20 V, 200 mA, low noise, high PSRR, CMOS LDO
−28 V, −200 mA, low noise, linear regulator
–40
PSRR (dB)
Product
ADP5075
ADP2370
+PSRR
–PSRR
–60
–80
–100
–120
10k
POWER SUPPLY CONSIDERATIONS
100k
1M
FREQUENCY (Hz)
10M
13405-534
ADP2370
13405-533
12V
INPUT
also be used. An LDO like the ADM7170 or ADP7118 is ideal
to generate the low noise rail.
The PSRR of the ADA4530-1 is excellent at dc (approximately
150 dB); however, it decreases as frequency increases. To achieve
the best performance of the ADA4530-1, a low-noise supply is
necessary. If switching supplies are used for input rails, a low
dropout regulator (LDO) is essential to attenuate the switching
spurs to a level that does not affect the ADA4530-1 output.
Switching power supply noise typically spans a frequency range
from 300 kHz and up. The switching spurs can effectively be
attenuated using the LDO. Additional filtering around the LDO
may be necessary, especially when using a switching regulator to
generate an intermediate rail. Switching regulators also generate
high frequency noise content (>100 MHz), even when running
in the 100 kHz range, because of the high dv/dt of the switch
node. In this case, ferrite beads can be used, as described in the
AN-1120 Application Note and the AN-1368 Application Note.
Figure 134. Positive and Negative PSRR for the ADP7118 and ADP7182
Powering ADA4530-1, ±VSY = ±5 V, +IN = 0 V
For a single-supply application, the ADA4530-1 typically needs
a 5 V, 10 V, or 12 V supply, although a 4.5 V to 16 V supply can
Figure 135. Maximum Allowable Ripple at the Input of the LDOs to Bring
Spurs To Noise Floor Level (−120 dB)
1000
ADP7118
ADP7182
(mV p-p)
100
10
1
0.01
0.01
0.1
1
FREQUENCY (Hz)
Rev. A | Page 49 of 50
10
13405-535
0.1
ADA4530-1
Data Sheet
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 136. 8-Lead Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADA4530-1ARZ
ADA4530-1ARZ-R7
ADA4530-1ARZ-RL
ADA4530-1R-EBZ-BUF
ADA4530-1R-EBZ-TIA
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
8-Lead Small Outline Package [SOIC_N]
Evaluation Board Buffer Configuration for 8-Lead SOIC
Evaluation Board Transimpedance Configuration for 8-Lead SOIC
Z = RoHS Compliant Part.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13405-0-3/16(A)
Rev. A | Page 50 of 50
Package Option
R-8
R-8
R-8