DS3487 www.ti.com SNLS355C – MAY 1998 – REVISED APRIL 2013 DS3487 Quad TRI-STATE Line Driver Check for Samples: DS3487 FEATURES DESCRIPTION • • • • • • • The DS3487 quad RS-422 driver features four independent drivers which comply with EIA Standards for the electrical characteristics of balanced voltage digital interface circuits. The outputs are TRI-STATE structures which are forced to a high impedance state when the appropriate output control pin reaches a logic zero condition. All input pins are PNP buffered to minimize input loading for either logic one or logic zero inputs. 1 2 Four Independent Drivers TRI-STATE Outputs Fast Propagation Times (typ 10 ns) TTL Compatible 5V Supply Output Rise and Fall Times Less than 15 ns Pin Compatible with DS8924 and MC3487 Block and Connection Diagrams Figure 1. Block Diagram Figure 2. PDIP Package- Top View See Package Number D0016A or NFG0016E Truth Table (1) Input (1) Control Non-Inverting Inverting Input Output Output H H H L L H L H X L Z Z L = Low logic state H = High logic state X = Irrelevant Z = TRI-STATE (high impedance) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2013, Texas Instruments Incorporated DS3487 SNLS355C – MAY 1998 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage 8V Input Voltage 5.5V −65°C to +150°C Storage Temperature Maximum Power Dissipation (3) at 25°C PDIP Package 1476 mW SOIC Package 1051 mW Lead Temperature (Soldering, 4 seconds) (1) 260°C “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Derate PDIP molded package 11.9 mW/°C above 25°C. Derate SOIC package 8.41 mW/°C above 25°C. (2) (3) Operating Conditions Min Max Units 4.75 5.25 V 0 +70 °C Typ Max Units 0.8 V Supply Voltage, VCC DS3487 Temperature (TA) DS3487 Electrical Characteristics (1) (2) (3) (4) Parameter Test Conditions Min VIL Input Low Voltage VIH Input High Voltage IIL Input Low Current V IL = 0.5V −200 μA IIH Input High Current VIH = 2.7V 50 μA VIH = 5.5V 100 μA VCL Input Clamp Voltage I CL = −18 mA −1.5 V VOL Output Low Voltage I OL = 48 mA 0.5 V VOH Output High Voltage I OH = −20 mA IOS Output Short-Circuit Current −140 mA IOZ Output Leakage Current (TRI-STATE) −100 μA IOFF Output Leakage Current Power OFF 2.0 VCC = 0V Differential Output Voltage |VT|– VT| Difference in Differential Output Voltage ICC Power Supply Current 2 100 μA VO = 6V 100 μA VO = −0.25V −100 μA 0.4 V VO = 5.5V VT (3) (4) V VO = 0.5V Difference in Output Offset Voltage (2) 2.5 −40 |VOS– VOS| (1) V 2.0 V 0.4 V Active 50 80 mA TRI-STATE 35 60 mA Unless otherwise specified min/max limits apply across the 0°C to +70°C range for the DS3487. All typicals are given for VCC = 5V and TA = 25°C. All currents into device pins are positive, all currents out of device pins as negative. All voltages are referenced to ground unless otherwise specified. Only one output at a time should be shorted. Symbols and definitions correspond to EIA RS-422, where applicable. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS3487 DS3487 www.ti.com SNLS355C – MAY 1998 – REVISED APRIL 2013 Switching Characteristics VCC = 5V, TA = 25°C Parameter Test Conditions Min Typ Max Units tPHL Input to Output 10 15 ns tPLH Input to Output 10 15 ns tTHL Differential Fall Time 10 15 ns tTLH Differential Rise Time 10 15 ns tPHZ Enable to Output RL = 200Ω, CL = 50 pF 17 25 ns tPLZ Enable to Output RL = 200Ω, CL = 50 pF 15 25 ns tPZH Enable to Output RL = ∞, CL = 50 pF, S1 Open 11 25 ns tPZL Enable to Output RL = 200Ω, CL = 50 pF, S2 Open 15 25 ns AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS Input pulse: f = MHz, 50%; tr = tf ≤ 15 ns. Figure 3. Propagation Delays S1 and S2 closed except as noted. CL includes probe and jig capacitance. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS3487 3 DS3487 SNLS355C – MAY 1998 – REVISED APRIL 2013 www.ti.com Input pulse: f = MHz, 50%; tr = tf ≤ 15 ns. S1 = open for tPZH S2 = open for tPZL Figure 4. TRI-STATE Enable and Disable Delays Input pulse: f = MHz, 50%; tr = tf ≤ 15 ns. Figure 5. Differential Rise and Fall Times 4 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS3487 DS3487 www.ti.com SNLS355C – MAY 1998 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision B (April 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ............................................................................................................ 4 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS3487 5 PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS3487M/NOPB LIFEBUY SOIC D 16 48 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 DS3487M DS3487MX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 DS3487M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS3487MX/NOPB Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.3 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS3487MX/NOPB SOIC D 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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