Intersil ACTS573T Radiation hardened octal three-state transparent latch Datasheet

ACTS573T
Data Sheet
July 1999
Radiation Hardened Octal Three-State
Transparent Latch
Intersil’s Satellite Applications FlowTM (SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The Intersil ACTS573T is a Radiation Hardened Octal
Transparent Latch with an active low output enable. The
outputs are transparent to the inputs when the latch enable
(LE) is High. When the latch goes low the data is latched.
The output enable controls the three-state outputs. When
the output enable pins (OE) are high the output is in a high
impedance state. The latch operation is independent of the
state of output enable.
File Number
4613.1
Features
• QML Class T, Per MIL-PRF-38535
• Radiation Performance
- Gamma Dose (γ) 1 x 105 RAD(Si)
- Latch-Up Free Under Any Conditions
- Single Event Upset (SEU) Immunity: <1 x 10-10
Errors/Bit/Day (Typ)
- SEU LET Threshold . . . . . . . . . . . . .>100 MEV-cm2/mg
• 1.25 Micron Radiation Hardened SOS CMOS
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
Specifications
• Fast Propagation Delay . . . . . . . . 18ns (Max), 12ns (Typ)
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Pinouts
ACTS573T (SBDIP), CDIP2-T20
TOP VIEW
Detailed Electrical Specifications for the ACTS573T are
contained in SMD 5962-96725. A “hot-link” is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Ordering Information
1
D0
2
19 Q0
D1
3
18 Q1
D2
4
17 Q2
D3
5
16 Q3
D4
6
15 Q4
D5
7
14 Q5
D6
8
13 Q6
D7
9
12 Q7
GND 10
11 LE
20 VCC
TEMP.
RANGE
(oC)
ORDERING
INFORMATION
PART
NUMBER
5962R9672502TRC
ACTS573DTR-02
-55 to 125
5962R9672502TXC
ACTS573KTR-02
-55 to 125
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
ACTS573T (FLATPACK), CDFP4-F20
TOP VIEW
OE
1
20
VCC
D0
2
19
Q0
D1
3
18
Q1
D2
4
17
Q2
D3
5
16
Q3
D4
6
15
Q4
D5
7
14
Q5
D6
8
13
Q6
D7
9
12
Q7
10
11
LE
GND
1
OE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
ACTS573T
Functional Diagram
1 OF 8 IDENTICAL CIRCUITS
VCC
LE
p
Dn
n
p
OE
LE
LE
p
Qn
n
LE
n
OE
VSS
COMMON CONTROLS
LE
LE
LE
OE
OE
OE
TRUTH TABLE
OE
LE
DATA
OUTPUT
L
H
H
H
L
H
L
L
L
L
l
L
L
L
h
H
H
X
X
Z
NOTE: L = Low Logic Level, H = High Logic Level, X = Don’t Care, Z = High Impedance, l = Low Voltage Level Prior to High-to-Low Latch Enable
Transition, h = High Voltage Level Prior to High-to-Low Latch Enable Transition.
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ACTS573T
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
(2600µm x 2600µm x 533µm ±51µm)
Type: Silox (SiO2)
102 x 102 x 21mils ±2mil
Thickness: 8kÅ ±1kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm2
Type: Al Si Cu
Thickness: 10kÅ ±2kÅ
TRANSISTOR COUNT:
SUBSTRATE POTENTIAL:
190
Unbiased (Silicon on Sapphire)
PROCESS:
Bond Pad #20 First
CMOS SOS
BACKSIDE FINISH:
Sapphire
Metallization Mask Layout
(18) Q1
(19) Q0
(20) VCC
(1) OE
(2) D0
(3) D1
ACTS573T
D2 (4)
(17) Q2
D3 (5)
(16) Q3
NC
NC
NC
NC
Q6 (13)
Q7 (12)
LE (11)
(14) Q5
GND (10)
D5 (7)
D7 (9)
(15) Q4
D6 (8)
D4 (6)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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