TI1 DS92LX1622 10 - 50 mhz dc-balanced channel link iii serializer and deserializer with bi-directional control channel Datasheet

DS92LX1621, DS92LX1622
www.ti.com
SNLS327I – MAY 2010 – REVISED JANUARY 2014
DS92LX1621/DS92LX1622 10 - 50 MHz DC-Balanced Channel Link III Serializer and
Deserializer with Bi-Directional Control Channel
Check for Samples: DS92LX1621, DS92LX1622
FEATURES
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Configurable Data Throughput
– 12–bit (min) up to 600 Mbits/sec
– 16–bit (def) up to 800 Mbits/sec
– 18–bit (max) up to 900 Mbits/sec
10 MHz to 50 MHz Input Clock Support
Embedded Clock with DC Balanced Coding to
Support AC-Coupled Interconnects
Capable to Drive up to 10 Meters Shielded
Twisted-Pair
Bi-Directional Control Interface Channel with
I2C Support
I2C Interface for Device Configuration. Singlepin ID Addressing
16–bit Data Payload with CRC (Cyclic
Redundancy Check) for Checking Data
Integrity with Programmable Data
Transmission Error Detection and Interrupt
Control
Up to 6 Programmable GPIO's
AT-SPEED BIST Diagnosis Feature to Validate
Link Integrity
Individual Power-Down Controls for Both SER
and DES
User-Selectable Clock Edge for Parallel Data
on Both SER and DES
Integrated Termination Resistors
1.8V- or 3.3V-Compatible Parallel Bus Interface
Single Power Supply at 1.8V
IEC 61000–4–2 ESD Compliant
No Reference Clock Required on Deserializer
Programmable Receive Equalization
LOCK Output Reporting Pin to Ensure Link
Status
EMI/EMC Mitigation
– DES Programmable Spread Spectrum
(SSCG) Outputs
– DES Receiver Staggered Outputs
Temperature Range −40°C to +85°C
•
•
SER Package: 32 Pin WQFN (5mm x 5mm)
DES Package: 40 Pin WQFN (6mm x 6mm)
APPLICATIONS
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Industrial Displays, Touch Screens
Medical Imaging
DESCRIPTION
The DS92LX1621 / DS92LX1622 chipset offers a
Channel Link III interface with a high-speed forward
channel and a full-duplex back channel for data
transmission over a single differential pair. The
Serializer/Deserializer pair is targeted for direct
connections between automotive camera systems
and Host Controller/Electronic Control Unit (ECU).
The primary transport sends 16 bits of image data
over a single high-speed serial stream together with a
low latency bi-directional control channel transport
that supports I2C. Included with the 16-bit payload is
a selectable data integrity option for CRC (Cyclic
Redundancy Check) or parity bit to monitor
transmission link errors. Using TI’s embedded clock
technology
allows
transparent
full-duplex
communication over a single differential pair, carrying
asymmetrical bi-directional control information without
the dependency of video blanking intervals. This
single serial stream simplifies transferring a wide data
bus over PCB traces and cable by eliminating the
skew problems between parallel data and clock
paths. This significantly saves system cost by
narrowing data paths that in turn reduce PCB layers,
cable width, and connector size and pins.
In addition, the Deserializer inputs provide
equalization control to compensate for loss from the
media over longer distances. Internal DC balanced
encoding/decoding is used to support AC-Coupled
interconnects.
The sleep function provides a power-savings mode
and a remote wake up interrupt for signaling of a
remote device.
The Serializer is offered in a 32-pin WQFN package,
and Deserializer is offered in a 40-pin WQFN
package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2014, Texas Instruments Incorporated
DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
www.ti.com
Typical Application Diagram
Parallel
Data In
16
Image
Sensor
Parallel
Data Out
16
Channel Link III
2
2
DS92LX1622
DS92LX1621
Bidirectional
Back Ch.
Cntl Bus
Serializer
Microcontroller/
ECU
Bidirectional
Back Ch.
Cntl Bus
Bi-direction
Back Channel
Deserializer
Figure 1. Typical Application Circuit
RIN+ RT
RT
GPIO [1:0]
DOUT-
DS92LX1621 - SERIALIZER
LOCK
PASS
I C Controller
Encoder Decoder
CAD
Clock
Gen
Timing
and
Control
PDB
M/S
BISTEN
Decoder Encoder
SCL
FIFO
I2C Controller
SDA
ROUT[13:0] HS, VS
GPIO [1:0]
PCLK
CDR
Timing
and
Control
PDB
M/S
2
RIN-
Clock
Gen
FIFO
PLL
16
SDA
SCL
2
PCLK
Output Latch
DOUT+
Decoder
RT
RT
Deserializer
2
Serializer
16
Encoder
DIN[13:0] HS, VS
Input Latch
Block Diagrams
CAD
DS92LX1622 - DESERIALIZER
Figure 2. Block Diagram
DS92LX1621
Serializer
Channel Link III
High Speed
Camera Data
DOUT+
14
Image
Sensor
YUV/RGB
HSYNC
PCLK
14
YUV/RGB
DIN[13:0]
HS, VS
VSYNC
2
Camera Data
RIN+
DOUTPixel Clock
DS92LX1622
Deserializer
RIN-
ROUT[13:0]
HS, VS
VSYNC
Bi-Directional
Back Channel
PCLK
GPIO[1:0]
GPIO[1:0]
GPI/O
SDA
Camera Unit
SCL
HSYNC
Pixel Clock
2
GPI/O
SDA
SDA
SCL
SCL
ECU Module
Microcontroller
SDA
SCL
Figure 3. Application Block Diagram
2
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Product Folder Links: DS92LX1621 DS92LX1622
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
DS92LX1621 Pin Diagram
DIN[0]/GPIO[2]
16
DIN[1]/GPIO[3]
15
DIN[2]/GPIO[4]
GPIO[0]
14
DIN[3]/GPIO[5]
GPIO[1]
VDDCML
VDDD
13
DIN[4]
17
DOUT+
DIN[10]
12
DIN[5]
18
DOUT-
DIN[11]
11
DIN[6]
19
VDDT
DIN[12]
10
DIN[7]
20
VDDPLL
9
25
26
21
28
22
29
DIN[9]
23
30
DIN[8]
24
31
VDDIO
27
Top View
PDB
1
2
3
4
5
6
7
8
HSYNC
VSYNC
PCLK
SCL
SDA
CAD
RES
M/S
32
DIN[13]
DS92LX1621
Serializer
32-Pin WQFN
Figure 4. Serializer - DS92LX1621
32-Pin WQFN (RTV Package)
DS92LX1621 Serializer PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
32, 31, 30, 29,
27, 26, 24, 23,
22, 21, 20, 19,
18, 17
Inputs, LVCMOS w/
pull down
Parallel data inputs.
HSYNC
1
Inputs, LVCMOS w/
pull down
Parallel data input 14, typically used as Horizontal SYNC Input
VSYNC
2
Inputs, LVCMOS w/
pull down
Parallel data input 15, typically used as Vertical SYNC Input
PCLK
3
Input, LVCMOS w/
pull down
Pixel Clock Input Pin. Strobe edge set by TRFB control register.
DIN[13:0]
GENERAL PURPOSE INPUT OUTPUT (GPIO)
DIN[3:0]/
GPIO[5:2]
20, 19, 18, 17
Input/Output, Digital
DIN[3:0] general-purpose pins can be individually configured as either inputs
or outputs; used to control and respond to various commands.
GPIO[1:0]
16, 15
Input/Output, Digital
General-purpose pins can be individually configured as either inputs or
outputs; used to control and respond to various commands.
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX1621 DS92LX1622
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DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
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DS92LX1621 Serializer PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
Description
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL
4
Input/Output, Digital
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
5
Input/Output, Open
Drain
Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
M/S
8
Input, LVCMOS w/
pull down
I2C Mode Select
M/S = L, Master (default); device generates and drives the SCL clock line
M/S = H, Slave; device accepts SCL clock input
CAD
6
Input, analog
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (See Figure 29).
CONTROL AND CONFIGURATION
PDB
9
Input, LVCMOS w/
pull down
Power down Mode Input Pin.
PDB = H, Transmitter is enabled and is ON.
PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in the
SLEEP state, the PLL is shutdown, and IDD is minimized.
RES
7
Input, LVCMOS w/
pull down
Reserved. This pin MUST be tied LOW.
Channel Link III INTERFACE
DOUT+
13
Input/Output, CML
Non-inverting differential output, back-channel input.
DOUT-
12
Input/Output, CML
Inverting differential output, back-channel input.
VDDPLL
10
Power, Analog
PLL Power, 1.8V ±5%
VDDT
11
Power, Analog
Tx Analog Power, 1.8V ±5%
VDDCML
14
Power, Analog
LVDS & BC Dr Power, 1.8V ±5%
VDDD
28
Power, Digital
Digital Power, 1.8V ±5%
VDDIO
25
Power, Digital
Power for input stage, The single-ended inputs are powered from VDDIO.
DAP
Ground, DAP
DAP must be grounded. Connect to ground plane with at least 9 vias.
Power and Ground
VSS
4
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DS92LX1621, DS92LX1622
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
DS92LX1622 PIN DIAGRAM
PDB
LOCK
GPIO[0]
GPIO[1]
VDDOR1
ROUT[0]/GPIO[2]
ROUT[1]/GPIO[3]
ROUT[2]/GPIO[4]
ROUT[3]/GPIO[5]
22
21
ROUT[4]
ROUT[5]
18
ROUT[6]
17
ROUT[7]
16
VDDOR2
15
ROUT[8]
14
ROUT[9]
13
VDDD
12
ROUT[10]
11
ROUT[11]
VDDCML
DS92LX1622
Deserializer
40-Pin WQFN
35
RES
34
31
23
32
24
33
25
37
26
38
27
39
28
40
29
19
RES
30
20
PASS
VDDR
Top View
1
2
3
4
5
6
7
8
9
10
VSYNC
HSYNC
VDDOR3
ROUT[13]
ROUT[12]
M/S
PCLK
RES
VDDSSCG
VDDPLL
SCL
BISTEN
SDA
RIN-
CAD
36
RIN+
Figure 5. Deserializer - DS92LX1622
40-Pin WQFN (RTA Package)
DS92LX1622 Deserializer PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
9, 10, 11, 12,
14, 15, 17, 18,
19, 20, 21, 22,
23, 24
Outputs, LVCMOS
Parallel data outputs.
HSYNC
7
Output, LVCMOS
Parallel data output 14, typically used as Horizontal SYNC output
VSYNC
6
Output, LVCMOS
Parallel data output 14, typically used as Vertical SYNC output
PCLK
5
Output, LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RRFB control register
ROUT[13:0]
General Purpose Input Output (GPIO)
ROUT[3:0] /
GPIO[5:2]
GPIO[1:0]
21, 22, 23, 24
Input/Output, Digital
ROUT[3:0] general-purpose pins can be individually configured as either inputs
or outputs; used to control and respond to various commands.
26, 27
Input/Output, Digital
General-purpose pins can be individually configured as either inputs or outputs;
used to control and respond to various commands.
SERIAL CONTROL BUS - I2C COMPATIBLE
SCL
3
Input/Output, Digital
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
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Product Folder Links: DS92LX1621 DS92LX1622
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DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
www.ti.com
DS92LX1622 Deserializer PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
2
Input/Output, Open
Drain
40
Input, LVCMOS w/
pull up
SDA
Description
Data line for serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
I2C Mode Select
M/S
M/S = L, Master; device generates and drives the SCL clock line
M/S = H, Slave (default); device accepts SCL clock input
Continuous Address Decoder
CAD
1
Input, analog
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID address
(See Figure 29)
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB
29
Input, LVCMOS w/
pull down
PDB = H, Receiver is enabled and is ON.
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in the
SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is shutdown
and IDD is minimized.
LOCK Status Output Pin.
LOCK
28
Output, LVCMOS
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
PASS
31
Output, LVCMOS
32, 33, 39
-
When BISTEN = L; Normal operation
PASS is high to indicate no errors are detected. The PASS pin asserts low to
indicate a CRC error was detected on the link.
Reserved.
RES
Pin 39: This pin MUST be tied LOW.
Pins 32, 33: Leave pin open.
BIST MODE
BIST Enable Pin.
BISTEN
37
Input, LVCMOS w/
pull down
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS
31
Output, LVCMOS
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
Channel Link III INTERFACE
RIN+
35
Input/Output, CML
Noninverting differential input, back channel output.
RIN-
36
Input/Output, CML
Inverting differential input, back channel output.
POWER AND GROUND
4
Digital Power
SSCG Power, 1.8V ±5%
Power supply must be connect regardless if SSCG function is in operation
25, 16, 8
Digital Power
TTL Output Buffer Power, The single-ended outputs and control input are
powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDD
13
Digital Power
Digital Core Power, 1.8V ±5%
VDDR
30
Analog Power
Rx Analog Power, 1.8V ±5%
VDDCML
34
Analog Power
Bi-Directional Control Channel Driver Power, 1.8V ±5%
VDDPLL
38
Analog Power
PLL Power, 1.8V ±5%
DAP
Ground
VDDSSCG
VDDOR1/2/3
VSS
DAP must be grounded. Connect to the ground plane with at least 16 vias.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6
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DS92LX1621, DS92LX1622
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
Absolute Maximum Ratings (1) (2)
−0.3V to +2.5V
Supply Voltage ( VDD1V8)
−0.3V to +4.0V
Supply Voltage (VDD3V3)
LVCMOS Input Voltage (VDD1V8)
−0.3V to +(VDD1V8 + 0.3V)
LVCMOS Input Voltage (VDD3V3)
−0.3V to +(VDD3V3 + 0.3V)
−0.3V to +(VDD + 0.3V)
LVCMOS Output Voltage (VDD)
CML Driver I/O Voltage (VDD1V8)
−0.3V to (VDD1V8 + 0.3V)
CML Receiver I/O Voltage (VDD1V8)
−0.3V to (VDD1V8 + 0.3V)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Maximum Package Power Dissipation Capacity
1/θJA °C/W above +25°
Package Derating:
DS92LX1621 32L WQFN
θJA(based on 9 thermal vias)
34.3 °C/W
θJC(based on 9 thermal vias)
6.9 °C/W
Maximum Package Power Dissipation Capacity Package
1/θJA °C/W above +25°
Package Derating:
DS92LX1622 40L WQFN
θJA(based on 16 thermal vias)
28.0 °C/W
θJC(based on 16 thermal vias)
4.4 °C/W
ESD Rating (IEC 61000–4–2)
RD = 330Ω, CS = 150pF
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
≥±25 kV
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
≥±10 kV
≥±8 kV
ESD Rating (HBM)
(1)
(2)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
Nom
Max
Units
VDD (1.8V)
1.71
1.8
1.89
V
VDDIO (1.8V Mode)
1.71
1.8
1.89
V
VDDIO (3.3V Mode)
3
3.3
3.6
V
VDDn(1.8V)
25
mVp-p
VDDIO(1.8V)
25
mVp-p
VDD3V3
50
mVp-p
+85
°C
50
MHz
Supply Noise
Operating Free Air
Temperature (TA)
-40
Input Clock Rate
+25
10
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Serializer Electrical Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
s
LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 3.0V to 3.6V
2.0
VIN
V
VIL
Low Level Input Voltage
VIN = 3.0V to 3.6V
GND
0.8
V
IIN
Input Current
VIN = 0V or 3.6V
VIN = 3.0V to 3.6V
-20
+20
µA
VOH
High Level Output Voltage VDDIO = 3.0V to 3.6V
2.4
VDDIO
V
VOL
Low Level Output Voltage
GND
0.4
V
IOS
Output Short Circuit
Current
VOUT = 0V
TRI-STATE Output
Current
PDB = 0V,
VOUT = 0V or VDD
IOZ
VDDIO = 3.0V to 3.6V
IOH = +4mA
±1
Serializer GPIO
Outputs
-24
Deserializer
LVCMOS Outputs
-39
mA
LVCMOS Outputs
-20
±1
+20
µA
LVCMOS DC SPECIFICATIONS 1.8V I/O (TX INPUTS, RX OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input Voltage
VIN = 1.71V to 1.89V
0.65 VIN
VIN +0.3
VIL
Low Level Input Voltage
VIN = 1.71V to 1.89V
GND
0.35 VIN
IIN
Input Current
VIN = 0V or 1.89V
VIN = 1.71V to 1.89V
-20
VOH
High Level Output Voltage
VDDIO = 1.71V to 1.89V
IOH = −4mA
VOL
Low Level Output Voltage
VDDIO = 1.71V to 1.89V
IOL = +4 mA
IOS
Output Short Circuit
Current
VOUT = 0V
TRI-STATE Output
Current
PDB = 0V,
VOUT = 0V or VDD
IOZ
(4)
±1
V
+20
µA
VDDIO - 0.45
VDDIO
V
GND
0.45
V
Serializer GPIO
Outputs
-11
Deserializer
LVCMOS Outputs
-20
mA
LVCMOS Outputs
-20
±1
+20
µA
268
340
412
mV
1
50
mV
VDD - VOD
VDD (MAX) VOD (MIN)
V
1
50
mV
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
|VOD|
Output Differential Voltage RT = 100Ω
ΔVOD
Output Differential Voltage
RL = 100Ω
Unbalance
VOS
Output Differential Offset
Voltage
RL = 100Ω (See Figure 10)
ΔVOS
Offset Voltage Unbalance
RL = 100Ω
IOS
Output Short Circuit
Current
DOUT+/- = 0V,
PDB = L or H (4)
RT
Differential Internal
Termination Resistance
Differential across DOUT+ and DOUT-
VDD (MIN) VOD (MAX)
-27
80
100
mA
120
Ω
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
VTH
VTL
(1)
(2)
(3)
(4)
8
Differential Threshold
High Voltage
Differential Threshold Low
Voltage
+90
See Figure 12
mV
-90
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
Specification is guaranteed by characterization and is not tested in production.
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
Serializer Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
s
VIN
Differential Input Voltage
Range
RIN+ - RIN-
180
IIN
Input Current
VIN = VDD or 0V,
VDD = 1.89V
-20
±1
+20
µA
RT
Differential Internal
Termination Resistance
Differential across RIN+ and RIN-
80
100
120
Ω
62
90
mV
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDDS
IDDT
IDDIOT
IDDTZ
Serializer (Tx)
Total Supply Current
Mode (includes load
current)
RT = 100Ω
WORST CASE pattern
(See Figure 7)
RT = 100Ω
RANDOM PRBS-7 pattern
Serializer (Tx)
VDDIO Supply Current
(includes load current)
RT = 100Ω
WORST CASE pattern
(See Figure 7)
Serializer (Tx) Supply
Current Power-down
PDB = 0V; All other
LVCMOS Inputs = 0V
IDDIOTZ
IDDR
IDDIOR
IDDRZ
Deserializer (Rx) Supply
Current (includes load
current)
Deserializer (Rx) VDDIO
Supply Current (includes
load current)
Deserializer (Rx) Supply
Current Power-down
VDDn = 1.89V
CL = 8pF
WORST CASE Pattern
(See Figure 7)
VDDn = 1.89V,
f = 50MHz
Default Registers
2
VDDn = 3.6V,
f = 50MHz
Default Registers
7
15
VDD = 1.89V
370
775
VDDIO = 1.89V
55
125
VDDIO = 3.6V
65
135
f = 50 MHz
SSCG[3:0] = ON
Default Registers
60
96
f = 50 MHz
Default Registers
VDDIO = 1.89V
CL = 8pF
WORST CASE Pattern
(See Figure 7)
f = 50 MHz
Default Registers
VDDIO = 3.6V
CL = 8pF
Worst Case Pattern
IDDIORZ
55
VDDn = 1.89V,
f = 50MHz
Default Registers
VDDn = 3.6V
CL = 8pF
WORST CASE Pattern
PDB = 0V; All other
LVCMOS Inputs = 0V
mA
5
mA
53
mA
16
25
f = 50 MHz
Default Registers
38
64
VDDn = 1.89V
42
400
VDDIO = 1.89V
8
40
VDDIO = 3.6V
350
800
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Recommended Serializer Timing for PCLK (1) (2)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
tTCP
Transmit Clock Period
tTCIH
Transmit Clock Input High
Time
Conditions
Typ
Max
Units
20
T
100
ns
0.4T
0.5T
0.6T
ns
0.4T
0.5T
0.6T
ns
3
ns
10 MHz — 50 MHz
tTCIL
Transmit Clock Input Low
Time
tCLKT
PCLK Input Transition Time
fosc
Internal oscillator clock
source
(1)
Min
0.5
25
MHz
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
(2)
Serializer Switching Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RL = 100Ω (See Figure 8)
150
330
ps
RL = 100Ω
(See Figure 8)
150
330
ps
tLHT
CML Low-to-High Transition
Time
tHLT
CML High-to-Low Transition
Time
tDIS
Data Input Setup to PCLK
tDIH
Data Input Hold from PCLK
tPLD
Serializer PLL Lock
Time (4) (5)
RL = 100Ω
tSD
Serializer Delay
RT = 100Ω
f = 10-50 MHz
Reg Address 0x03h b[0] (TRFB = 1)
(See Figure 16)
tJIND
Serializer Output
Deterministic Jitter
Serializer output intrinsic deterministic
jitter. Measure with PRBS-7 test
pattern. PCLK = 50 MHz
0.13
UI (6)
tJINR
Serializer Output Random
Jitter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating – 1,0 pattern.
0.04
UI (6)
tJINT
Peak-to-peak Serializer
Output Jitter
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measure with PRBS-7 test
pattern.
0.396
UI (6)
λSTXBW
Serializer Jitter Transfer
Function -3 dB Bandwidth
PCLK = 50 MHz
Default Registers
1.9
MHz
δSTX
Serializer Jitter Transfer
Function
PCLK = 50 MHz
Default Registers
0.944
dB
δSTXf
Serializer Jitter Transfer
Function Peaking Frequency
PCLK = 50 MHz
Default Registers
500
kHz
(1)
(2)
(3)
(4)
(5)
(6)
10
Serializer Data Inputs (See Figure 14)
2.0
ns
2.0
ns
6.386T + 5
1
2
ms
6.386T +
12
6.386T +
19.7
ns
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
tPLD and tDDLT is the time required by the serializer and deserializer to obtain data lock when exiting power-down state with an active
PCLK.
Specification is guaranteed by design and is not tested in production.
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
Deserializer Switching Characteristics (1) (2) (3) (4)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
Receiver Output Clock Period
tRCP = tTCP
PCLK
20
T
100
ns
tPDC
PCLK Duty Cycle
Default Registers
SSCG[3:0] = OFF
PCLK
45
50
55
%
tCLH
LVCMOS Low-to-High Transition
Time
1.3
2.0
2.8
tCHL
LVCMOS High-to-Low Transition
Time
1.3
2.0
2.8
tCLH
LVCMOS Low-to-High Transition
Time
1.6
2.4
3.3
1.6
2.4
3.3
0.38T
0.5T
0.38T
0.5T
4.571T +
8
4.571T +
12
tCHL
LVCMOS High-to-Low Transition
Time
tROS
ROUT Setup Data to PCLK
VDDIO: 1.71V to 1.89V or
3.0V to 3.6V, CL = 8 pF
(lumped load)
Default Registers (See
Table 1) (5)
PCLK
VDDIO: 1.71V to 1.89V or
3.0V to 3.6V, CL = 8 pF
(lumped load)
Default Registers (See
Table 1) (6)
Deserializer Data
Outputs
VDDIO: 1.71V to 1.89V or
3.0V to 3.6V, CL = 8pF
(lumped load)
Default Registers ( See
Table 1)
Deserializer Data
Outputs
Default Registers
Register 0x03h b[0]
(RRFB = 1)
10 MHz-50 MHz
ns
ns
ns
tROH
ROUT Hold Data to PCLK
tDD
Deserializer Delay
tDDLT
Deserializer Data Lock Time
10 MHz-50 MHz
tRJIT
Receiver Input Jitter Tolerance (7)
50 MHz
0.53
tRDJ
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF
10 MHz
300
550
50 MHz
120
250
tDPJ
Deserializer Period Jitter (8)
PCLK
SSCG[3:0] = OFF
10 MHz
425
600
50 MHz
320
480
tDCCJ
Deserializer Cycle-to-Cycle Clock
Jitter (9)
PCLK
SSCG[3:0] = OFF
10 MHz
320
500
50 MHz
300
500
fdev
Spread Spectrum Clocking
Deviation Frequency
fmod
Spread Spectrum Clocking
Modulation Frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
LVCMOS Output Bus
(See Figure 21)
4.571T
+ 16
ns
10
ms
UI
ps
ps
ps
20 MHz-50 MHz
±0.5% to
±2.0%
%
20 MHz-50 MHz
±9 kHz to
±66 kHz
kHz
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
Specification is guaranteed by characterization and is not tested in production.
Specification is guaranteed by design and is not tested in production.
tRJIT max (0.61 UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2MHz) is greater than 1 UI.
tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
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Bi-Directional Control Bus Timing Specifications (SCL, SDA) - (See Figure 6)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
RECOMMENDED INPUT TIMING REQUIREMENTS
Min
Typ
Max
Units
100
kHz
(1)
fSCL
SCL Clock Frequency
>0
fLOW
SCL Low Period
4.7
µs
fHIGH
SCL High Period
4.0
µs
tHD:STA
Hold time for a start or a repeated start
condition
4.0
µs
tSU:STA
Set Up time for a start or a repeated
start condition
4.7
µs
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
250
ns
tSU:STO
Set Up Time for STOP Condition,
4.0
µs
tr
SCL & SDA Rise Time
1000
tf
SCL & SDA Fall Time
300
ns
Cb
Capacitive load for bus
400
pF
fSCL = 100 kHz
0
3.45
µs
ns
SWITCHING CHARACTERISTICS ( (2))
fSCL
SCL Clock Frequency
fLOW
Serializer M/S = 0 – R/W Register
0x05 = 0x40'h
100
Deserializer M/S = 0 – READ
Register 0x06 b[6:4] = 0x00'h
100
kHz
Serializer M/S = 0 – R/W Register
0x05 = 0x40'h
SCL Low Period
Deserializer M/S = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer M/S = 0 – R/W Register
0x05 = 0x40'h
4.7
μs
4.0
μs
μs
fHIGH
SCL High Period
tHD:STA
Hold time for a start or a repeated start
condition
Serializer M/S = 0 Register 0x05 =
0x40'h
4.0
tSU:STA
Set Up time for a start or a repeated
start condition
Serializer M/S = 0 Register 0x05 =
0x40'h
4.7
tHD:DAT
Data Hold Time
tSU:DAT
Data Set Up Time
tSU:STO
Set Up Time for STOP Condition
tf
SCL & SDA Fall Time
tBUF
Bus free time between a stop and start
condition
tTIMEOUT
NACK Time out
(1)
(2)
12
Deserializer M/S = 0 – READ
Register 0x06 b[6:4] = 0x00'h
μs
0
Serializer M/S = 0
3.45
250
ns
4.0
μs
300
Serializer M/S = 0
μs
ns
μs
4.7
Serializer M/S = 1
1
Deserializer MODE = 1
Register 0x06 b[2:0]=111'b
25
ms
Recommended Input Timing Requirements are input specifications and not tested in production.
Specification is guaranteed by design and is not tested in production.
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
SDA
tLOW
tf
tHD;STA
tr
tf
tBUF
tr
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tSU;STO
tSU;DAT
tHD;DAT
START
STOP
REPEATED
START
START
Figure 6. Bi-Directional Control Bus Timing
Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIH
Input High Level
SDA and SCL
0.7 x
VDDIO
VDDIO
V
VIL
Input Low Level Voltage
SDA and SCL
GND
0.3 x
VDDIO
V
VHY
Input Hysteresis
IOZ
TRI-STATE Output Current
PDB = 0V VOUT = 0V or VDD
-20
±1
+20
µA
IIN
Input Current
SDA or SCL, Vin = VDDIO or GND
-20
±1
+20
µA
CIN
Input Pin Capacitance
VOL
>50
mV
<5
Low Level Output Voltage
pF
SCL and SDA VDDIO = 3.0V IOL = 1.5
mA
0.36
SCL and SDA VDDIO = 1.71V IOL = 1
mA
0.36
V
AC Timing Diagrams and Test Circuits
Device Pin Name
Signal Pattern
T
PCLK
ODD DIN/ROUT
EVEN DIN/ROUT
Figure 7. “Worst Case” Test Pattern
Vdiff
80%
80%
20%
Vdiff = 0V
20%
tLHT
tHLT
Vdiff = (DOUT+) - (DOUT-)
Figure 8. Serializer CML Output Load and Transition Times
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100 nF
DOUT+
50:
ZDiff = 100:
SCOPE
BW 8 4.0 GHz
100:
50:
DOUT-
100 nF
16
DIN/HS/VS
PARALLEL-TO-SERIAL
Figure 9. Serializer CML Output Load and Transition Times
DOUT+
RL
DOUT-
PCLK
Figure 10. Serializer VOD DC Diagram
DOUT-
Single Ended
V
V
OD
V
OD+
ODV
DOUT+
|
OS
0V
Differential
V
OD+
0V
(DOUT+)-(DOUT-)
V
OD-
Figure 11. Serializer VOD DC Diagram
RIN+
VCM = 1.2V
RIN+
VT H
VID
VIN
VTL
VID
VIN
RIN-
RIN-
GND
Figure 12. Differential VTH/VTL Definition Diagram
14
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
80%
VDD
80%
PCLK
20%
20%
0V
tCLKT
tCLKT
Figure 13. Serializer Input Clock Transition Times
tTCP
PCLK
VDDIO/2
tDIS
VDDIO/2
VDDIO/2
tDIH
VDDIO
DIN/HS/VS VDDIO/2
Setup
Hold
VDDIO/2
0V
Figure 14. Serializer Setup/Hold Times
PDB
(3.3V I/O)
2.0V
PCLK
tPLD
TRI-STATE
DOUT±
TRI-STATE
Output Active
DIN/HS/VS
SYMBOL N
SYMBOL N+1
SYMBOL N+2
SYMBOL N+3
| |
Figure 15. Serializer Data Lock Time
tSD
SYMBOL N-2
SYMBOL N-1
| |
SYMBOL N
| |
SYMBOL N-3
| |
DOUT+-
| |
SYMBOL N-4
| |
|
PCLK
Figure 16. Serializer Delay
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2.0V
PDB
(3.3V I/O)
| |
t DDLT
RIN ±
TRI - STATE
|
LOCK
Figure 17. Deserializer Data Lock Time
80%
80%
Deserializer
20%
8 pF
lumped
20%
tCLH
tCHL
Figure 18. Deserializer LVCMOS Output Load and Transition Times
SYMBOL N+3
SYMBOL N+4
| |
| |
| |
RIN±
SYMBOL N+2
| |
SYMBOL N+1
| |
SYMBOL N
t DD
SYMBOL N- 2
SYMBOL N - 1
SYMBOL N
| |
SYMBOL N - 3
| ||
| |
| |
ROUT/
VS/HS
| |
PCLK
SYMBOL N+1
Figure 19. Deserializer Delay
tROS
VDDIO
ROUT/HS/VS
VDDIO/2
VDDIO/2
0V
tROH
VDDIO
PCLK
VDDIO/2
0V
Figure 20. Deserializer Output Setup/Hold Times
16
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
Frequency
FPCLK+
fdev
fdev (max)
FPCLK
FPCLK-
fdev (min)
Time
1 / fmod
Figure 21. Spread Spectrum Clock Output Profile
2
JITTER TRANSFER (dB)
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
1.0E+04
1.0E+05
1.0E+06
1.0E+07
MODULATION FREQUENCY (Hz)
Figure 22. Typical Serializer Jitter Transfer Function at 43 MHz
0.62
JITTER AMPLITUDE (UI)
0.61
0.60
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.52
1.0E+04
1.0E+05
1.0E+06
1.0E+07
JITTER FREQUENCY (Hz)
Figure 23. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz
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Table 1. DS92LX1621 Control Registers
Addr
(Hex)
0
Name
Bits
Field
R/W
Default
7:1
DEVICE ID
RW
0x58
SER ID
RW
0
0: Device ID is from CAD
1: Register I2C Device ID overrides CAD
0
Reserved
7:3
2
Reserved
18
2
STANDBY
RW
0
Standby mode control. Retains control
register data. Supported only when M/S =
0
0: Enabled. Low-current Standby mode
with wake-up capability. Suspends all
clocks and functions.
1: Disabled. Standby and wake-up
disabled
1
DIGITAL RESET0
RW
0
self clear
1: Resets the device to default register
values. Does not affect device I2C Bus or
Device ID
0
DIGITAL RESET1
RW
0
self clear
1: Digital Reset, retains all register values
7:0
7
RESERVED
RX CRC
CHECKER
ENABLE
0x20'h
RW
Reserved
1
Back Channel CRC Enable
0: Disable
1: Enable
For propper CRC operation, control
register 0x03h b[6] of the Deserializer
must be enabled.
CRC Fault Tolerant
Transmission
6
TX CRC GEN
ENABLE
RW
1
Forward Channel CRC Enable
0: Disable
1: Enable
For propper CRC operation, control
register 0x03h b[7] of the Deserializer
must be enabled.
VDDIO Control
5
VDDIO CONTOL
RW
1
Auto VDDIO detect
0: Disable
1: Enable (auto detect mode)
VDDIO Mode
4
VDDIO MODE
RW
1
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I2C Pass-Through
3
I2C PASSTHROUGH
RW
1
I2C Pass-Through Mode
0: Disabled
1: Enabled
Reserved
2
RESERVED
0
Reserved
PCLK_AUTO
1
PCLK_AUTO
1
Switch over to internal 25 MHz oscillator
clock in the absence of PCLK
0: Disable
1: Enable
1
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on
the Falling Clock Edge.
1: Parallel Interface Data is strobed on
the Rising Clock Edge.
TRFB
4
RESERVED
Reset
CRC Fault Tolerant
Transmission
3
7-bit address of Serializer; 0x58h
(1011_000X) default
I2C Device ID
0
1
Description
CRC Transmission
0
TRFB
7:6
RESERVED
5
CRC RESET
4:0
RESERVED
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RW
RW
01'b
RW
Reserved
0
1: CRC Reset.
Clears CRC Error counter.
0
Reserved
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
Table 1. DS92LX1621 Control Registers (continued)
Addr
(Hex)
Name
5
I2C Bus Rate
6
DES ID
Bits
Field
R/W
Default
Description
7:0
I2C BUS RATE
RW
0x40
I2C ratio is determined by the following:
fSCL = 6.25 MHz / register value (in
decimal)
0x40'h = ~100 kHz SCL (default)
Note: Register values <0x32'h are NOT
supported.
7:1
DES DEV ID
RW
0x60
Deserializer Device ID = 0x60
(1100_000X) default
0
RESERVED
7:1
SLAVE DEV ID
RW
0
Reserved
0
Slave Device ID. Must be programmed to
communicate with remote slave device
7
Slave ID
0
RESERVED
0
Reserved
8
Reserved
7:0
RESERVED
RW
0
Reserved
9
Reserved
7:0
RESERVED
RW
1
Reserved
A
CRC Errors
7:0
CRC ERROR B0
R
0
Number of CRC errors - 8 LSBs
B
CRC Errors
7:0
CRC ERROR B1
R
0
Number of CRC errors - 8 MSBs
Reserved
7:3
RESERVED
0
Reserved
PCLK Detect
2
PCLK DETECT
R
0
1: Valid PCLK detected
0: Valid PCLK not detected
CRC Check
1
DES ERROR
R
0
1: CRC error during communication with
Deserializer
Cable Link Detect
Status
0
LINK DETECT
R
0
1: Cable link detected
0: Cable link not detected
C
D
E
F
10
11
GPIO[0] Config
GPIO[1] Config
GPIO[2] Config
GPIO[3] Config
GPIO[4] Config
7:4
RESERVED
1
Reserved
3:2
RESERVED
0
Reserved
1
GPIO0 DIR
RW
0
0: Output
1: Input
0
GPIO0 EN
RW
1
0: TRI-STATE
1: Enabled
7:4
RESERVED
0
Reserved
3:2
RESERVED
0
Reserved
1
GPIO1 DIR
RW
0
0: Output
1: Input
0
GPIO1 EN
RW
1
0: TRI-STATE
1: Enabled
7:4
RESERVED
0
Reserved
3:2
RESERVED
0
Reserved
1
GPIO2 DIR
RW
1
0: Output
1: Input
0
GPIO2 EN
RW
1
0: TRI-STATE
1: Enabled
7:4
RESERVED
0
Reserved
3:2
RESERVED
0
Reserved
1
GPIO3 DIR
RW
1
0: Output
1: Input
0
GPIO3 EN
RW
1
0: TRI-STATE
1: Enabled
7:4
RESERVED
0
Reserved
3:2
RESERVED
0
Reserved
1
GPIO4 DIR
RW
1
0: Output
1: Input
0
GPIO4 EN
RW
1
0: TRI-STATE
1: Enabled
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Table 1. DS92LX1621 Control Registers (continued)
Addr
(Hex)
12
13
Name
GPIO[5] Config
General Purpose
Control Reg
Bits
Field
7:4
RESERVED
0
Reserved
3:2
RESERVED
0
Reserved
1
GPIO5 DIR
RW
1
0: Output
1: Input
0
GPIO5 EN
RW
1
0: TRI-STATE
1: Enabled
GPCR[7]
GPCR[6]
GPCR[5]
GPCR[4]
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
RW
0
0: LOW
1: HIGH
7:0
R/W
Default
Description
Table 2. DS92LX1622 Control Registers
Addr
(Hex)
Name
Bits
7:1
0
R/W
Default
DEVICE ID
RW
0x60h
DES ID
RW
0
0: Device ID is from CAD
1: Register I2C Device ID overrides CAD
0
Reserved
I2C Device ID
0
7:3
1
Field
RESERVED
2
REM_WAKEUP
RW
0
1
DIGITALRESET0
RW
0 self clear
1: Resets the device to default register values. Does not
affect device I2C Bus or Device ID
0
DIGITALRESET1
RW
0 self clear 1: Digital Reset, retains all register values
Reserved
7:6
Auto Clock
5
AUTO_CLOCK
OSS Select
4
OSS_SEL
0
Reserved
RW
0
1: Output PCLK or Internal 25 MHz Oscillator clock
0: Only PCLK when valid PCLK present
RW
0
Output Sleep State Select
0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW, when LOCK = L
0
SSCG Select
0000: Normal Operation, SSCG OFF
0001: fmod (KHz) PCLK/2168, fdev ±0.50%
0010: fmod (KHz) PCLK/2168, fdev ±1.00%
0011: fmod (KHz) PCLK/2168, fdev ±1.50%
0100: fmod (KHz) PCLK/2168, fdev ±2.00%
0101: fmod (KHz) PCLK/1300, fdev ±0.50%
0110: fmod (KHz) PCLK/1300, fdev ±1.00%
0111: fmod (KHz) PCLK/1300, fdev ±1.50%
1000: fmod (KHz) PCLK/1300, fdev ±2.00%
1001: fmod (KHz) PCLK/868, fdev ±0.50%
1010: fmod (KHz) PCLK/868, fdev ±1.00%
1011: fmod (KHz) PCLK/868, fdev ±1.50%
1100: fmod (KHz) PCLK/868, fdev ±2.00%
1101: fmod (KHz) PCLK/650, fdev ±0.50%
1110: fmod (KHz) PCLK/650, fdev ±1.00%
1111: fmod (KHz) PCLK/650, fdev +/-1.50%
2
20
7-bit address of Deserializer;
0x60h
(1100_000X) default
Remote Wake-up Select
1: Enable. Generate remote wakeup signal automatically
wake-up the Serializer in Standby mode
0: Disable. Puts the Serializer (M/S = 0) in Standby mode
when Deserializer M/S = 1
Reset
SSCG
Description
3:0
SSCG
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
Table 2. DS92LX1622 Control Registers (continued)
Addr
(Hex)
Name
Bits
R/W
Default
Description
7
Tx CRC CHECK
ENABLE
RW
1
Back Channel CRC Enable
0: Disable
1: Enable
For proper CRC operation, on Serailizer 0x03h b[6]
control register must be Enabled.
6
Rx CRC GEN
ENABLE
RW
1
Foward Channel CRC Enable
0: Disable
1: Enable For proper CRC operation, on Serailizer 0x03h
b[7] control register must be Enabled.
VDDIO Control
5
VDDIO CONTROL
RW
1
Auto voltage control
0: Disable
1: Enable (auto detect mode)
VDDIO Mode
4
VDDIO MODE
RW
0
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I2C Pass-Through
3
I2C PASSTHROUGH
RW
1
I2C Pass-Through Mode
0: Disabled
1: Enabled
Auto ACK
2
AUTO ACK
RW
0
0: Disable
1: Enable
CRC Reset
1
CRC RESET
RW
0
1: CRC reset
1
Pixel Clock Edge Select
0: Parallel Interface Data is strobed on the Falling Clock
Edge
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0
00'h: ~0.0 dB
01'h: ~4.5 dB
03'h: ~6.5 dB
07'h: ~7.5 dB
0F'h: ~8.0 dB
1F'h: ~11.0 dB
3F'h: ~12.5 dB
FF'h: ~14.0 dB
CRC Fault
Tolerant
Transmission
3
Field
RRFB
0
RRFB
RW
4
EQ Feature
Control1
7:0
EQ
5
Reserved
7:0
RESERVED
0
Reserved
Reserved
7
RESERVED
0
Reserved
0
Prescales the SCL clock line when reading data byte
from a slave device (M/S = 0)
000 : ~100 kHz SCL (default)
001 : ~125 kHz SCL
101 : ~11 kHz SCL
110 : ~33 kHz SCL
111 : ~50 kHz SCL
Other values are NOT supported.
1
Remote NACK Timer Enable In slave mode (MODE = 1)
if bit is set the I2C core will automatically timeout when
no acknowledge condition was detected.
1: Enable
0: Disable
SCL Prescale
6
Remote NACK
Remote NACK
6:4
3
2:0
RW
SCL_PRESCALE
REM_NACK_TIME
R
NACK_TIMEOUT
RW
RW
111'b
Remote NACK Timeout.
000: 2.0 ms
001: 5.2 ms
010: 8.6 ms
011: 11.8 ms
100: 14.4 ms
101: 18.4 ms
110: 21.6 ms
111: 25.0 ms
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Table 2. DS92LX1622 Control Registers (continued)
Addr
(Hex)
Name
7
SER ID
8
9
ID[1] Index
A
ID[2] Index
B
ID[3] Index
C
ID[4] Index
D
ID[5] Index
E
ID[6] Index
F
ID[7] Index
10
ID[0] Match
11
ID[1] Match
12
ID[2] Match
13
ID[3] Match
14
ID[4] Match
15
ID[5] Match
Field
R/W
Default
7:1
SER DEV ID
RW
0x58h
0
RESERVED
7:1
ID[0] INDEX
0
RESERVED
7:1
ID[1] INDEX
0
RESERVED
7:1
ID[2] INDEX
0
RESERVED
7:1
ID[3] INDEX
0
RESERVED
7:1
ID[4] INDEX
0
RESERVED
7:1
ID[5] INDEX
0
RESERVED
7:1
ID[6] INDEX
0
RESERVED
7:1
ID[7] INDEX
0
RESERVED
7:1
ID[0] MATCH
0
RESERVED
7:1
ID[1] MATCH
0
RESERVED
7:1
ID[2] MATCH
0
RESERVED
7:1
ID[3] MATCH
0
RESERVED
7:1
ID[4] MATCH
0
RESERVED
7:1
ID[5] MATCH
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Description
Serializer Device ID = 0x58
(1011_000X) default
0
Reserved
0
Target slave Device ID slv_id1 [7:1]
0
Reserved
0
Target slave Device ID slv_id1 [7:1]
0
Reserved
0
Target slave Device ID slv_id2 [7:1]
0
Reserved
0
Target slave Device ID slv_id3 [7:1]
0
Reserved
0
Target slave Device ID slv_id4 [7:1]
0
Reserved
0
Target slave Device ID slv_id5 [7:1]
0
Reserved
0
Target slave Device ID slv_id6 [7:1]
0
Reserved
0
Target slave Device ID slv_id7 [7:1]
0
Reserved
0
Alias to match Device ID slv_id0 [7:1]
0
Reserved
0
Alias to match Device ID slv_id1 [7:1]
0
Reserved
0
Alias to match Device ID slv_id2 [7:1]
0
Reserved
0
Alias to match Device ID slv_id3 [7:1]
0
Reserved.
0
Alias to match Device ID slv_id4 [7:1]
0
Reserved
0
Alias to match Device ID slv_id5 [7:1]
0
Reserved
0
Alias to match Device ID slv_id6 [7:1]
0
Reserved
0
RESERVED
7:1
ID[6] MATCH
0
RESERVED
7:1
ID[7] MATCH
0
Alias to match Device ID slv_id7 [7:1]
0
RESERVED
0
Reserved
RW
16
ID[6] Match
17
ID[7] Match
18
Reserved
7:0
RESERVED
0
Reserved
19
Reserved
7:0
RESERVED
1
Reserved
1A
CRC Errors
7:0
CRC ERROR B0
R
0
Number of CRC errors 8 LSBs
1B
CRC Errors
7:0
CRC ERROR B1
R
0
Number of CRC errors 8 MSBs
Reserved
7:3
RESERVED
0
Reserved
CRC Check
2
SER ERROR
R
0
CRC error during communication with Serializer on
Forward Channel
Signal Detect
Status
1
R
0
0: Active signal not detected
1: Active signal detected
LOCK Pin Status
0
R
0
0: CDR/PLL Unlocked
1: CDR/PLL Locked
1C
22
ID[0] Index
Bits
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
Table 2. DS92LX1622 Control Registers (continued)
Addr
(Hex)
1D
1E
1F
20
21
22
Name
GPIO[0] Config
GPIO[1] Config
GPIO[2] Config
GPIO[3] Config
GPIO[4] Config
GPIO[5] Config
Bits
Field
R/W
Default
7:3
RESERVED
RW
00010'b
2
GPIO0 SET
RW
1
1: Configured as GPIO
0: Configured as ROUT data (OSS_SEL controlled)
1
GPIO0 DIR
RW
1
0: Output
1: Input
0
GPIO0 EN
RW
1
0: TRI-STATE
1: Enabled
7:3
RESERVED
RW
0
Reserved
2
GPIO1 SET
RW
1
1: Configured as GPIO
0: Configured as ROUT data (OSS_SEL controlled)
1
GPIO1 DIR
RW
1
0: Output
1: Input
0
GPIO1 EN
RW
1
0: TRI-STATE
1: Enabled
7:3
RESERVED
RW
0
Reserved
2
GPIO2 SET
RW
0
1: Configured as GPIO
0: Configured as ROUT0 data (OSS_SEL controlled)
1
GPIO2 DIR
RW
0
0: Output
1: Input
0
GPIO2 EN
RW
1
0: TRI-STATE
1: Enabled
7:3
RESERVED
RW
0
Reserved
2
GPIO3 SET
RW
0
1: Configured as GPIO
0: Configured as ROUT1 data (OSS_SEL controlled)
1
GPIO3 DIR
RW
0
0: Output
1: Input
0
GPIO3 EN
RW
1
0: Tri-state
1: Enabled
7:3
RESERVED
RW
0
Reserved
2
GPIO4 SET
RW
0
1: Configured as GPIO
0: Configured as ROUT2 data (OSS_SEL controlled)
1
GPIO4 DIR
RW
0
0: Output
1: Input
0
GPIO4 EN
RW
1
0: TRI-STATE
1: Enabled
7:3
RESERVED
RW
0
Reserved
2
GPIO5 SET
RW
0
1: Configured as GPIO
0: Configured as ROUT3 data (OSS_SEL controlled)
1
GPIO5 DIR
RW
0
0: Output
1: Input
0
GPIO5 EN
RW
1
0: TRI-STATE
1: Enabled
RW
0
0: LOW
1: HIGH
RW
0
BIST Enable
0: Normal operation
1: Bist Enable
R
0
Bist Error Counter
23
General Purpose
Control Reg
7:0
GPCR[7]
GPCR[6]
GPCR[5]
GPCR[4]
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
24
BIST
0
BIST_EN
25
BIST_ERR
7:0
BIST_ERR
Description
Reserved
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Table 2. DS92LX1622 Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
R/W
Default
26
Remote Wake
Enable
7:6
REM_WAKEUP_E
N
RW
0
11: Enable remote wake up mode
00: Normal operation mode
Other values are NOT supported.
5:0
RESERVED
RW
0
Reserved
7:0
BCC
RW
0
0xE0: Normal Operation Mode. Users MUST program
this value.
27
24
BCC
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
FUNCTIONAL DESCRIPTION
The DS92LX1621 / DS92LX1622 Channel Link III chipset is intended for camera applications. The Serializer/
Deserializer chipset operates from a 10 MHz to 50 MHz pixel clock frequency. The DS92LX1621 transforms a
16-bit wide parallel LVCMOS data bus along with a bi-directional control bus into a single high-speed differential
pair. The high speed serial bit stream contains an embedded clock and DC-balance information which enhances
signal quality to support AC coupling. The DS92LX1622 receives the single serial data stream and converts it
back into a 16-bit wide parallel data bus together with the bi-directional control bus.
The bi-directional channel function of the DS92LX1621 / DS92LX1622 provides bi-directional communication
between the image sensor and the host device (FPGA, frame grabber, display, etc.). The integrated back
channel transfers data bi-directionally over the same differential pair used for video data interface. This interface
offers advantages over other chipsets by eliminating the need for additional wires for programming and control.
The bi-directional control channel is controlled via an I2C port. The bi-directional control channel offers
asynchronous communication and is not dependent on video blanking intervals.
SERIAL FRAME FORMAT
The DS92LX1621 / DS92LX1622 chipset will transmit and receive a pixel of data in the following format:
Figure 24. Serial Bitstream for 28-bit Symbol
The High Speed Forward Channel (HS_FC) is a 28-bit symbol composed of 16 bits of data containing camera
data & control information transmitted from Serializer to Deserializer. CLK1 and CLK0 represent the embedded
clock in the serial stream. CLK1 is always HIGH and CLK0 is always LOW. This data payload is optimized for
signal transmission over an AC coupled link. Data is randomized, balanced and scrambled. The data payload
may be checked using a 4-bit CRC function. The CRC monitors the link integrity of the serialized data and
reports when an error condition is detected.
The bi-directional control data is transferred over the single serial link along with the high-speed forward data.
This architecture provides a full duplex low speed forward and backward path across the serial link together with
a high speed forward channel without the dependence of the video blanking phase.
DESCRIPTION OF BI-DIRECTIONAL CONTROL BUS AND I2C MODES
The I2C compatible interface allows programming of the DS92LX1621, DS92LX1622, or an external remote
device (such as a camera) through the bi-directional control channel. Register programming transactions to/from
the DS92LX1621 / DS92LX1622 chipset are employed through the clock (SCL) and data (SDA) lines. These two
signals have open drain I/Os and both lines must be pulled-up to VDDIO by external resistor. Figure 6 shows the
timing relationships of the clock (SCL) and data (SDA) signals. Pull-up resistors or current sources are required
on the SCL and SDA busses to pull them high when they are not being driven low. A logic zero is transmitted by
driving the output low. A logic high is transmitted by releasing the output and allowing it to be pulled-up
externally. The appropriate pull-up resistor values will depend upon the total bus capacitance and operating
speed. The DS92LX1621 / DS92LX1622 I2C bus data rate supports up to 100 kbps according to I2C
specification.
To start any data transfer, the DS92LX1621 / DS92LX1622 must be configured in the proper I2C mode. Each
device can function as an I2C slave proxy or master proxy depending on the mode determined by M/S pin. The
Ser/Des interface acts as a virtual bridge between Master controller (MCU) and the remote device. When the
M/S pin is set to HIGH, the device is treated as a slave proxy; acts as a slave on behalf of the remote slave.
When addressing a remote peripheral or Serializer/ Deserializer (not wired directly to the MCU), the slave proxy
will forward any byte transactions sent by the Master controller to the target device. When M/S pin is set to LOW,
the device will function as a master proxy device; acts as a master on behalf of the I2C master controller. Note
that the devices must have complementary settings for the M/S configuration. For example, if the Serializer M/S
pin is set to HIGH then the Deserializer M/S pin must be set to LOW and vice-versa.
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DS92LX1621, DS92LX1622
Bus Activity:
Master
SDA Line
Register
Address
Slave
Address
7-bit Address
S
Stop
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Start
SNLS327I – MAY 2010 – REVISED JANUARY 2014
Data
P
0
A
C
K
A
C
K
A
C
K
Bus Activity:
Slave
S
Register
Address
Slave
Address
7-bit Address
A
C
K
Bus Activity:
Slave
Slave
Address
S
0
N
A
C
K
7-bit Address
A
C
K
Stop
SDA Line
Start
Bus Activity:
Master
Start
Figure 25. Write Byte
P
1
A
C
K
Data
Figure 26. Read Byte
SDA
1
2
6
MSB
R/W
Direction
Bit
Acknowledge
from the Device
7-bit Slave Address
SCL
ACK
LSB
MSB
7
8
9
LSB
N/ACK
Data Byte
*Acknowledge
or Not-ACK
1
8
2
Repeated for the Lower Data Byte
and Additional Data Transfers
START
9
STOP
Figure 27. Basic Operation
SDA
SCL
S
P
STOP condition
START condition, or
START repeat condition
Figure 28. START and STOP Conditions
SLAVE CLOCK STRETCHING
In order to communicate and synchronize with remote devices on the I2C bus through the bi-directional control
channel, slave clock stretching must be supported by the I2C master controller/MCU. The chipset utilizes bus
clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low
prior to the 9th clock of every I2C data transfer (before the ACK signal). The slave device will not control the
clock and only stretches it until the remote peripheral has responded; which is typically in the order of 12 μs
(typical).
26
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SNLS327I – MAY 2010 – REVISED JANUARY 2014
CAD PIN ADDRESS DECODER
The CAD pin is used to decode and set the physical slave address of the Serializer/Deserializer (I2C only) to
allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each
Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor and a
pull down resistor (RID) of the recommended value to set the physical device address. The recommended
maximum resistor tolerance is 0.1% worst case (0.2% total tolerance).
1.8V
10k
VDDIO
CAD
4.7k
4.7k
RCAD
HOST
SCL
SCL
SDA
SDA
SER
or
DES
To other
Devices
Figure 29. Serial Control Bus Connection
Table 3. CAD Resistor Value - DS92LX1621 Ser
Resistor RID Ω
(±0.1%)
Address 7'b
Address 8'b 0 appended (WRITE)
0
GND
7b' 101 1000 (h'58)
8b' 1011 0000 (h'B0)
2.0k
7b' 101 1001 (h'59)
8b' 1011 0010 (h'B2)
4.7k
7b' 101 1010 (h'5A)
8b' 1011 0100 (h'B4)
8.2k
7b' 101 1011 (h'5B)
8b' 1011 0110 (h'B6)
12.1k
7b' 101 1100 (h'5C)
8b' 1011 1000 (h'B8)
39.0k
7b' 101 1110 (h'5E)
8b' 1011 1100 (h'BC)
Table 4. CAD Resistor Value - DS92LX1622 Des
Resistor RID Ω
(±0.1%)
Address 7'b
Address 8'b 0 appended (WRITE)
0
GND
7b' 110 0000 (h'60)
8b' 1100 0000 (h'C0)
2.0k
7b' 110 0001 (h'61)
8b' 1100 0010 (h'C2)
4.7k
7b' 110 0010 (h'62)
8b' 1100 0100 (h'C4)
8b' 1101 0110 (h'C6)
8.2k
7b' 110 0011 (h'63)
12.1k
7b' 110 0100 (h'64)
8b' 1101 1000 (h'C8)
39.0k
7b' 110 0110 (h'66)
8b' 1100 1100 (h'CC)
CAMERA MODE OPERATION
In Camera mode, I2C transactions originate from the Master controller at the Deserializer side. The I2C slave
core in the Deserializer will detect if a transaction is intended for the Serializer or a slave at the Serializer.
Commands are sent over the bi-directional control channel to initiate the transactions. The Serializer will receive
the command and generate an I2C transaction on its local I2C bus. At the same time, the Serializer will capture
the response on the I2C bus and return the response on the forward channel link. The Deserializer parses the
response and passes the appropriate response to the Deserializer I2C bus.
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To configure the devices for camera mode operation, set the Serializer M/S pin to LOW and the Deserializer M/S
pin to HIGH. Before initiating any I2C commands, the Deserializer needs to be programmed with the target slave
device addresses and Serializer device address. SER_DEV_ID Register 0x07h sets the Serializer device
address and SLAVE_x_MATCH/SLAVE_x_INDEX registers 0x08h~0x17h set the remote target slave addresses.
In slave mode the address register is compared with the address byte sent by the I2C master. If the addresses
are equal to any of registers values, the I2C slave will acknowledge and hold the bus to propagate the transaction
to the target device otherwise it returns no acknowledge.
DISPLAY MODE OPERATION
In Display mode, I2C transactions originate from the controller attached to the Serializer. The I2C slave core in
the Serializer will detect if a transaction targets (local) registers within the Serialier or the (remote) registers within
the Deserializer or a remote slave connected to the I2C master interface of the Deserializer. Commands are sent
over the forward channel link to initiate the transactions. The Deserializer will receive the command and generate
an I2C transaction on its local I2C bus. At the same time, the Deserializer will capture the response on the I2C
bus and return the response as a command on the bi-directional control channel. The Serializer parses the
response and passes the appropriate response to the Serializer I2C bus.
The physical device ID of the I2C slave in the Serializer is determined by the analog voltage on the ID[x] input. It
can be reprogrammed by using the DEVICE_ID register and setting the bit . The device ID of the logical I2C
slave in the Deserializer is determined by programming the DES ID in the Serializer. The state of the CAD] input
on the Deserializer is used to set the device ID. The I2C transactions between Ser/Des will be bridged between
the host controller to the remote slave.
To configure the devices for display mode operation, set the Serializer M/S pin to HIGH and the Deserializer M/S
pin to LOW. Before initiating any I2C commands, the Serializer needs to be programmed with the target slave
device address and Serializer device address. DES_DEV_ID Register 0x06h sets the Deserializer device
address and SLAVE_DEV_ID register 0x7h sets the remote target slave address. If the I2C slave address
matches any of registers values, the I2C slave will hold the transaction allowing read or write to target device.
Note: In Display mode operation, registers 0x08h~0x17h on Deserializer must be reset to 0x00.
CRC (CYCLIC REDUNDANCY CHECK)
A 4-bit CRC per symbol is reserved for checking the link integrity during transmission. The reporting status pin
(PASS) is provided on the Deserializer side, which flags any mismatch of data transmitted to and from the
remote device. The Deserializer's PLL must first be locked (LOCK pin is HIGH) to ensure the PASS status is
valid. This error detection handling generates an interrupt signal onto the PASS output pin; notifying the host
controller as soon as any errors are identified. When an error occurs, the PASS will asserts LOW. An adjustable
interrupt threshold register is also available for managing the data flow.
ERROR DETECTION
The DS92LX1621 / DS92LX1622 chipset provides several error detection operations for ensuring data integrity in
long distance transmission and reception. The data error detection function offers user flexibility and usability of
performing bit-by-bit and data transmission error checking. The error detection operating modes support data
validation of the following signals:
• Bi-directional Control Channel control data detection across serial link
• Control VSYNC and HSYNC signals across serial link
• Parallel video/pixel data across serial link
PROGRAMMABLE CONTROLLER
An integrated I2C slave controller is embedded in each of the DS92LX1621 Serializer and DS92LX1622
Deserializer. It must be used to access and program the extra features embedded within the configuration
registers. Refer to Table 1 and Table 2 for details of control registers.
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MULTIPLE DEVICE ADDRESSING
Some applications require multiple camera devices with the same fixed address to be accessed on the same I2C
bus. The DS92LX1621 / DS92LX1622 provide slave ID matching/aliasing to generate different target slave
addresses when connecting more than two identical devices together on the same bus. This allows the slave
devices to be independently addressed. Each device connected to the bus is addressable through a unique ID
by programming of the SLAVE_ID_MATCH register on Deserializer. This will remap the SLAVE_ID_MATCH
address to the target SLAVE_ID_INDEX address; up to 8 ID indexes are supported. The host controller must
keep track of the list of I2C peripherals in order to properly address the target device. In a camera application, the
microcontroller is located on the Deserializer side. In this case, the microcontroller programs the slave address
matching registers and handles all data transfers to and from all slave I2C devices. This is useful in the event
where camera modules are removed or replaced. For example in the configuration shown in Figure 30:
• Host device (FPGA, frame grabber, etc.) is the I2C master and has an I2C master interface
• The I2C protocol is bridged from DES A to SER A and from DES B to SER B
• The I2C interfaces in SER A and SER B are both master interfaces
If the master controller transmits I2C slave 0xA0, the DES A address 0xE0 will forward the transaction to remote
Camera A. If the controller transmits slave address 0xA2, the DES B 0xE2 will recognize that 0xA2 is mapped to
0xA0 and will be transmitted to the remote Camera B. If controller sends command to address 0xB2, the DES B
0xE2 will forward transaction to slave device 0xB0.
The Slave ID index/match is supported only in the camera mode (SER: M/S pin = L; DES: M/S pin = H). For
Multiple device addressing in display mode (SER: M/S pin = H; DES: M/S pin = L), use the I2C pass through
function.
Camera A
DS92LX1621
Slave ID: (0xA0)
CMOS
Image
Sensor
DIN[15:0]
PCLK
ROUT[15:0]
PCLK
2
SDA
SCL
I C
SER A: CAD(0xD0)
PC /
EEPROM
Slave ID: (0xB0)
Camera B
DS92LX1621
Slave ID: (0xA0)
CMOS
Image
Sensor
SDA
SCL
2
I C
DES A: CAD(0xE0)
SLAVE_ID1_MATCH(0xA0)
SLAVE_ID1_INDEX(0xA0)
SLAVE_ID2_MATCH(0xB0)
SLAVE_ID2_INDEX(0xB0)
ECU
Module
DS92LX1622
DIN[15:0]
PCLK
ROUT[15:0]
PCLK
2
SDA
SCL
PC/
EEPROM
DS92LX1622
I C
SER B: CAD(0xD2)
Slave ID: (0xB0)
2
I C
DES B: CAD(0xE2)
SLAVE_ID2_MATCH(0xA2)
SLAVE_ID2_INDEX(0xA0)
SLAVE_ID2_MATCH(0xB2)
SLAVE_ID2_INDEX(0xB0)
SDA
SCL
PC
Master
Figure 30. Multiple Device Addressing
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I2C PASS THROUGH
I2C pass-through provides an alternative means to independently address slave devices. The mode enables or
disables I2C bidirectional control channel communication to the remote I2C bus. This option is used to determine
whether or not an I2C instruction is to be transferred over to the remote I2C device. When enabled, the I2C bus
traffic will continue to pass through and will be received by I2C devices downstream. If disabled, I2C commands
will be blocked to the remote I2C device. The pass through function also provides access and communication to
only specific devices on the remote bus. The feature is effective for both Camera mode and Display mode.
For example in the configuration shown in Figure 31:
If master controller transmits I2C transaction for address 0xA0, the SER A with I2C pass through enabled will
transfer I2C commands to remote Camera A. The SER B with I2C pass through disabled, any I2C commands will
be bypassed on the I2C bus to Camera B.
DS92LX1621
CMOS
Image
Sensor
DIN[15:0]
PCLK
SDA
SCL
Camera A
Slave ID: (0xA0)
ROUT[15:0]
PCLK
2
I C
SER A: I2C _MASTER
I2C_PASS_THRU Enabled
DS92LX1621
CMOS
Image
Sensor
DS92LX1622
SDA
SCL
2
I C
DES A: I2C_SLAVE
DS92LX1622
DIN[15:0]
PCLK
SDA
SCL
Camera B
Slave ID: (0xA0)
ECU
Module
ROUT[15:0]
PCLK
2
I C
SER B: I2C_MASTER
I2C_PASS_THRU Disabled
SDA
SCL
2
I C
DES B: I2C_SLAVE
PC
Master
Figure 31. I2C Pass Through
SYNCHRONIZING MULTIPLE CAMERAS
For applications requiring multiple cameras for frame-synchronization, it is recommended to utilize the General
Purpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To
synchronize the cameras properly, the system controller needs to provide a field sync output (such as a vertical
or frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronize
signal corresponds to the start and end of a frame and the start and end of a field. Note this form of
synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from
the bi-directional control channel, there will be a time variation of the GPIO signals arriving at the different target
devices (between the parallel links). The maximum latency delta (t1) of the GPIO data transmitted across
multiple links is 25 μs.
Note: The user must verify that the timing variations between the different links are within their system and timing
specifications.
For example in the configuration shown in Figure 32:
The maximum time (t1) between the rising edge of GPIO (i.e. sync signal) arriving at Camera A and Camera B is
25 μs.
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DS92LX1621
Camera A
CMOS
Image
Sensor
DS92LX1622
DATA
PCLK
DATA
PCLK
2
I C
Serializer A
FSYNC
FSO
GPIO
GPIO
FSIN
FSYNC
2
I C
Deserializer A
ECU
Module
Camera B
CMOS
Image
Sensor
DS92LX1621
DS92LX1622
DATA
PCLK
DATA
PCLK
2
I C
Serializer B
FSYNC
2
FSO
GPIO
GPIO
FSIN
FSYNC
PC
I C
Deserializer B
Figure 32. Synchronizing Multiple Cameras
DES A
GPIO[n] Input
SER B
GPIO[n] Output
|
SER A
GPIO[n] Output
|
DES B
GPIO[n] Input
t1
Figure 33. GPIO Delta Latency
GENERAL PURPOSE I/O (GPIO)
The DS92LX1621 / DS92LX1622 has up to 6 GPIO (2 dedicated and 4 programmable). GPIO[0] and GPIO[1]
are always available and GPIO[2:5] are available depending on the parallel data bus size. DIN/ROUT[0:3] can be
programmed into GPIOs (GPIO[2:5]) when the parallel data bus is less than 12 bits wide (10-bit data + HS,VS).
Each GPIO can be configured as either an input or output port. The GPIO maximum switching rate is up to 66
kHz when configured for communication between Deserializer GPI to Serializer GPO. Whereas data flow
configured for communication between Serializer GPI to Deserializer GPO is limited by the maximum data rate of
the PCLK.
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AT-SPEED BIST (BISTEN, PASS)
An optional AT SPEED Built in Self Test (BIST) feature supports at speed testing of the high-speed serial and
the bidirectional control channel link. Control pins at the Deserializer are used to enable the BIST test mode and
allow the system to initiate the test and set the duration. A HIGH on PASS pin indicates that all payloads
received during the test were error free during the BIST duration test. A LOW on this pin at the conclusion of the
test indicates that one or more payloads were detected with errors.
The BIST duration is defined by the width of BISTEN. BIST starts when Deserializer LOCK goes HIGH and
BISTEN is set HIGH. BIST ends when BISTEN goes LOW. Any errors detected after the BIST Duration are not
included in PASS logic. Note: AT-SPEED BIST is only available in the Camera mode and not the Display mode.
The following diagram shows how to perform system AT SPEED BIST:
Serializer MODE = 0 and Deserializer MODE = 1
Apply power for Serializer and Deserializer
Normal
Step 1: Enable AT SPEED BIST by placing the
Deserializer in BIST by mode setting BISTEN = H
BIST Wait
Step 4: Place System in
Normal Operating Mode
BISTEN = L
Step 2: Deserializer will setup Serializer and enable BIST
mode through Bidirectional control channel
communication and then reacquire forward channel clock
BIST Start
Step 3: Stop AT SPEED BIST by turning off BIST
mode with BISTEN = L at the Deserializer.
BIST Stop
Figure 34. AT-SPEED BIST System Flow Diagram
Step 1: Place the Deserializer in BIST Mode.
Serializer and Deserializer power supply must be supplied. Enable the AT SPEED BIST mode on the
Deserializer by setting the BISTEN pin High. The DS92LX1622 GPIO[1:0] pins are used to select the PCLK
frequency of the on-chip oscillator for the BIST test on high speed data path.
Table 5. BIST Oscillator Frequency Select
DES GPIO [1:0]
32
Oscillator Source
min (MHz)
typ (MHz)
00
External PCLK
01
Internal
10
Internal
25
11
Internal
12.5
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10
max (MHz)
50
50
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The Deserializer GPIO[1:0] set to 00 will bypass the on-chip oscillator and an external oscillator to Serializer
PCLK input is required. This allows the user to operate BIST under different frequencies other than the
predefined ranges.
Step 2: Enable AT SPEED BIST by placing the Serializer into BIST mode.
The deserializer will communicate through the back-channel to configure Serializer into BIST mode. Once the
BIST mode is set, the Serializer will initiate BIST transmission to the Deserializer.
Wait 10 ms for Deserializer to acquire lock and then monitor the LOCK pin transition from LOW to HIGH. At this
point, AT SPEED BIST is operational and the BIST process has begun. The Serializer will start transfer of an
internally generated PRBS data pattern through the high speed serial link. This pattern traverses across the
interconnecting link to the Deserializer. Check the status of the PASS pin; a HIGH indicates a pass, a LOW
indicates a fail. A fail will stay LOW for ½ a clock cycle. If two or more bits fail in a row the PASS pin will toggle ½
clock cycle HIGH and ½ clock cycle low. The user can use the PASS pin to count the number of fails on the high
speed link. In addition, there is a defined SER and DES register that will keep track of the accumulated error
count. The Serializer DS92LX1621 GPIO[0] pin will be assigned as a PASS flag error indicator for the bidirectional control channel link.
Recovered
Pixel Clock
Case 1: No bit errors
Start Pixel
BISTEN
Recovered
Pixel Data
PASS
Previous
³&5&´6WDWH
³&5&´6WDWH
Case 2: Bit error(s)
Recovered
Pixel Data
PASS
B
B
B
B
Previous
³&5&´6WDWH
³&5&´6WDWH
E
E
E
E
Case 3: Bit error(s) AFTER BIST Duration
Recovered
Pixel Data
PASS
B
Previous
³&5&´6WDWH
³&5&´6WDWH
B = Bad Pixel
PE = Payload Error
BIST Duration
(when BISTEN=H)
CRC Status
(when BISTEN=L)
Figure 35. BIST Timing Diagram
Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail.
To end BIST, the system must pull BISTEN pin of the Deserializer LOW. The BIST duration is fully defined by
the BISTEN width and thus the Bit Error Rate is determined by how long the system holds BISTEN HIGH.
fpixel (MHz)
BIST Duration (s)
x Total Pixels Transmitted = Total Bits Transmitted
= BIST Duration (s) x
Pixel
1 Pixel period (ns) x Total Bits
Bit (Pixel) Error Rate
-1
= [Total Bits Transmitted]
(for passing BIST)
=
[Total Bits Transmitted x Bits/Pixel] -1
Figure 36. BIST BER Calculation
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For instance, if BISTEN is held HIGH for 1 second and the PCLK is running at 43 MHz with 16 bpp, then the Bit
Error Rate is no better than 1.46E-9.
Step 4: Place system in Normal Operating Mode by disabling BIST at the Serializer.
Once Step 3 is complete, AT SPEED BIST is over and the Deserializer is out of BIST mode. To fully return to
Normal mode, apply Normal input data into the Serializer.
Any PASS result will remain unless it is changed by a new BIST session or cleared by asserting and releasing
PDB. The default state of PASS after a PDB toggle is HIGH.
It is important to note that AT SPEED BIST will only determine if there is an issue on the link that is not related to
the clock and data recovery of the link (whose status is flagged with LOCK pin).
LVCMOS VDDIO OPTION
1.8V or 3.3V SER Inputs and DES Outputs are user configurable to provide compatibility with 1.8V and 3.3V
system interfaces.
REMOTE WAKE UP (Camera Mode)
After initial power up, the SER is in a low-power Standby mode. The DES (controlled by host controller) 'Remote
Wake-up' register allows the DES side to generate a signal across the link to remotely wake-up the SER. Once
the SER detects the wake-up signal, the SER switches from Standby mode to active mode. In active mode, the
SER locks onto PCLK input (if present), otherwise the on-chip oscillator is used as the input clock source. Note
the host controller should monitor the DES LOCK pin and confirm LOCK = H before performing any I2C
communication across the link.
For Remote Wake-up to function properly:
• The chipset needs to be configured in Camera mode: SER M/S = 0 and DES M/S = 1
• The SER expects remote wake-up by default at power on.
• Configure the control channel driver of the DES to be in remote wake up mode by setting DES register 0x26
to 0xC0.
• Perform remote wake up on SER by setting DES register 0x01 b[2] to 1.
• Return the control channel driver of the DES to the normal operation mode by setting DES register 0x26 to 0.
The SER can also be put into standby mode by programming the DES remote wake up control register 0x01 b[2]
REM_WAKEUP to 0.
POWERDOWN
The SER has a PDB input pin to ENABLE or Powerdown the device. The modes can be controlled by the host
and is used to disable the link to save power when the remote device is not operational. An auto mode is also
available. In this mode, the PDB pin is tied HIGH and the SER switches over to an internal oscillator when the
PCLK stops or not present. When a PCLK starts again, the SER will then lock to the valid input PCLK and
transmits the data to the DES. In powerdown mode, the high-speed driver outputs are static (HIGH).
The DES has a PDB input pin to ENABLE or Powerdown the device. This pin can be controlled by the system
and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied
HIGH and the DES will enter powerdown when the serial stream stops. When the serial stream starts up again,
the DES will lock to the input stream and assert the LOCK pin and output valid data. In powerdown mode, the
Data and PCLK outputs are set by the OSS_SEL control register.
POWER UP REQUIREMENTS AND PDB PIN
It is required to delay and release the PDB input signal after VDD (VDDn and VDDIO) power supplies have
settled to the recommended operating voltages. A external RC network can be connected to the PDB pin to
ensure PDB arrives after all the VDD have stabilized.
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SIGNAL QUALITY ENHANCERS
Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of
equalization is controlled via register setting.
EMI REDUCTION
Des - Receiver Staggered Output
The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a
defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching
simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall
EMI.
Des Spread Spectrum Clocking Compatibilty
The DS92LX1622 parallel data and clock outputs have programmable SSCG ranges from 9 kHz–66 kHz and
±0.5%– ±2% from 20 MHz to 50 MHz. The modulation rate and modulation frequency variation of output spread
is controlled through the SSC control registers.
PIXEL CLOCK EDGE SELECT (TRFB/RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the Falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 37. Programmable PCLK Strobe Select
Applications Information
AC COUPLING
The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme. To
use the device in an AC-coupled application, insert external AC coupling capacitors in series in the Channel Link
III signal path as illustrated in Figure 38.
DOUT+
RIN+
DOUT-
RIN-
D
R
Figure 38. AC-Coupled Application
For high-speed Channel Link III transmissions, the smallest available package should be used for the AC
coupling capacitor. This will help minimize degradation of signal quality due to package parasitics. The most
common used capacitor value for the interface is 0.1μF.
TYPICAL APPLICATION CONNECTION
Figure 39 shows a typical connection of the DS92LX1621 Serializer.
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DS92LX1621 (SER)
VDDIO
VDDIO
C12
FB1
C8
1.8V
VDDT
C4
FB2
C10
C5
FB3
C11
C6
FB4
C7
FB5
C3
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
HSYNC
VSYNC
LVCMOS
Parallel
Bus
C9
C13
VDDPLL
VDDCML
VDDD
C1
Serial
Channel
Link III
Interface
DOUT+
DOUTC2
PCLK
1.8V
LVCMOS
Control
Interface
MODE
PDB
10 k:
ID[X]
GPIO
Control
Interface
RID
GPIO[0]
GPIO[1]
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C9 = 0.1 PF
C10 - C13 = 4.7 PF
C14 - C15 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB7: Impedance = 1 k:(@ 100 MHz)
low DC resistance (<1:)
VDDIO
RPU
I2C
Bus
Interface
RPU
SCL
FB6
SDA
FB7
C14
Optional
Optional
C15
RES
DAP (GND)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 39. DS92LX1621 Typical Connection Diagram
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Figure 40 shows a typical connection of the DS92LX1622 Deserializer.
DS92LX1622 (DES)
1.8V
VDDD
C13
C11
FB1
C3
FB2
C4
FB3
C5
VDDIO
VDDIO1
C8
VDDR
FB6
C12
C14
VDDIO2
C9
VDDSSCG
VDDIO3
C10
VDDPLL
FB4
C15
C6
FB5
C16
C7
VDDCML
C1
Serial
Channel
Link III
Interface
RIN+
RINC2
TP_A
RES_PIN32
RES_PIN33
TP_B
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
LVCMOS
Parallel
Bus
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
HSYNC
VSYNC
PCLK
LVCMOS
Control
Interface
MODE
PDB
RPU
I2C
Bus
Interface
GPIO
Control
Interface
GPIO[0]
GPIO[1]
VDDIO
RPU
SCL
LOCK
PASS
FB7
SDA
FB8
C17
1.8V
C18
Optional
10 k:
Optional
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13 - C16 = 4.7 PF
C17 - C18 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB8: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
ID[X]
RID
RES_PIN40
DAP (GND)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 40. DS92LX1622 Typical Connection Diagram
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TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and
signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment.
The interconnect for Channel Link III interface should present a differential impedance of 100 Ohms. Use of
cables and connectors that have matched differential impedance will minimize impedance discontinuities.
Shielded or un-shielded cables may be used depending upon the noise environment and application
requirements. The chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The
maximum signaling rate increases as the cable length decreases. Therefore, the chipset supports 50 MHz at
shorter distances.
Other cable parameters that may limit the cable's performance boundaries are: cable attenuation, near-end
crosstalk and intra-pair skew.
For obtaining optimal performance, the following is recommended:
• Use Shielded Twisted Pair (STP) cable
• 100Ω ± 10% differential impedance and 24 AWG (or lower AWG) cable
• Low intra-pair skew (less than 0.1UI), impedance matched
• Terminate unused conductors
• Optimum settings for deserializer Register 0x27 (See Table 2)
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential
lines of 100 Ohms are typically recommended for differential interconnect. The closely coupled lines help to
ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled
lines will also radiate less.
Information on the LLP style package is provided in the AN-1187 Leadless Leadframe Package (LLP) Application
Report (literature number SNOA401).
38
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX1621 DS92LX1622
DS92LX1621, DS92LX1622
www.ti.com
SNLS327I – MAY 2010 – REVISED JANUARY 2014
INTERCONNECT GUIDELINES
For full details, see the Channel-Link PCB and Interconnect Design-In Guidelines (literature number SNLA008)
and the Transmission Line RAPIDESIGNER Operation and Applications Guide (literature number SNLA035).
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual (literature number SNLA187), which is
available in PDF format from the TI LVDS & CML Solutions web site.
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX1621 DS92LX1622
Submit Documentation Feedback
39
DS92LX1621, DS92LX1622
SNLS327I – MAY 2010 – REVISED JANUARY 2014
www.ti.com
REVISION HISTORY
Changes from Revision H (April 2013) to Revision I
Page
•
Changed "tri-state" and "low" OSS values to reflect correct bit definition .......................................................................... 20
•
Added user-recommended value for deserializer echo cancellation in general-purpose cables ....................................... 24
•
Added tolerance for transmission cable impedance ........................................................................................................... 38
•
Added tolerance range for transmission cable skew .......................................................................................................... 38
•
Added reference to optimum settings information in deserializer Reg 0x27 ...................................................................... 38
Changes from Revision G (April 2013) to Revision H
•
40
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 39
Submit Documentation Feedback
Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DS92LX1621 DS92LX1622
PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS92LX1621SQ/NOPB
ACTIVE
WQFN
RTV
32
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LX1621
DS92LX1621SQE/NOPB
ACTIVE
WQFN
RTV
32
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LX1621
DS92LX1621SQX/NOPB
ACTIVE
WQFN
RTV
32
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LX1621
DS92LX1622SQ/NOPB
ACTIVE
WQFN
RTA
40
1000
Green (RoHS
& no Sb/Br)
SN
Level-3-260C-168 HR
-40 to 85
LX1622
DS92LX1622SQE/NOPB
ACTIVE
WQFN
RTA
40
250
Green (RoHS
& no Sb/Br)
SN
Level-3-260C-168 HR
-40 to 85
LX1622
DS92LX1622SQX/NOPB
ACTIVE
WQFN
RTA
40
2500
Green (RoHS
& no Sb/Br)
SN
Level-3-260C-168 HR
-40 to 85
LX1622
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Nov-2013
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DS92LX1621SQ/NOPB
WQFN
RTV
32
DS92LX1621SQE/NOPB
WQFN
RTV
DS92LX1621SQX/NOPB
WQFN
RTV
DS92LX1622SQ/NOPB
WQFN
DS92LX1622SQE/NOPB
DS92LX1622SQX/NOPB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
32
250
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
32
4500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
RTA
40
1000
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
WQFN
RTA
40
250
178.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
WQFN
RTA
40
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Nov-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS92LX1621SQ/NOPB
WQFN
RTV
32
1000
213.0
191.0
55.0
DS92LX1621SQE/NOPB
WQFN
RTV
32
250
213.0
191.0
55.0
DS92LX1621SQX/NOPB
WQFN
RTV
32
4500
367.0
367.0
35.0
DS92LX1622SQ/NOPB
WQFN
RTA
40
1000
367.0
367.0
38.0
DS92LX1622SQE/NOPB
WQFN
RTA
40
250
213.0
191.0
55.0
DS92LX1622SQX/NOPB
WQFN
RTA
40
2500
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
RTA0040A
SQA40A (Rev B)
www.ti.com
MECHANICAL DATA
RTV0032A
SQA32A (Rev B)
www.ti.com
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