TI1 DRV5055A4QLPG Ratiometric linear hall effect sensor Datasheet

Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
DRV5055
SBAS640 – JANUARY 2018
DRV5055 Ratiometric Linear Hall Effect Sensor
1 Features
3 Description
•
•
•
•
The DRV5055 device is a linear Hall effect sensor
that responds proportionally to magnetic flux density.
The device can be used for accurate position sensing
in a wide range of applications.
1
•
•
•
•
Ratiometric Linear Hall Effect Magnetic Sensor
Operates From 3.3-V and 5-V Power Supplies
Analog Output With VCC / 2 Quiescent Offset
Magnetic Sensitivity Options (At VCC = 5 V):
– A1: 100 mV/mT, ±21-mT Range
– A2: 50 mV/mT, ±42-mT Range
– A3: 25 mV/mT, ±85-mT Range
– A4: 12.5 mV/mT, ±169-mT Range
Fast 20-kHz Sensing Bandwidth
Low-Noise Output With ±1-mA Drive
Compensation For Magnet Temperature Drift
Standard Industry Packages:
– Surface-Mount SOT-23
– Through-Hole TO-92
2 Applications
•
•
•
•
•
•
•
•
•
Precise Position Sensing
Industrial Automation and Robotics
Home Appliances
Gamepads, Pedals, Keyboards, Triggers
Height Leveling, Tilt and Weight Measurement
Fluid Flow Rate Measurement
Medical Devices
Absolute Angle Encoding
Current Sensing
The device operates from 3.3-V or 5-V power
supplies. When no magnetic field is present, the
analog output drives half of VCC. The output changes
linearly with the applied magnetic flux density, and
four sensitivity options enable maximal output voltage
swing based on the required sensing range. North
and south magnetic poles produce unique voltages.
Magnetic flux perpendicular to the top of the package
is sensed, and the two package options provide
different sensing directions.
The device uses a ratiometric architecture that can
eliminate error from VCC tolerance when the external
analog-to-digital converter (ADC) uses the same VCC
for its reference. Additionally, the device features
magnet temperature compensation to counteract how
magnets drift for linear performance across a wide
–40°C to 125°C temperature range.
Device Information(1)
PART NUMBER
DRV5055
PACKAGE
SOT-23 (3)
2.92 mm × 1.30 mm
TO-92 (3)
4.00 mm × 3.15 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Schematic
Magnetic Response
OUT
VCC
VCC
DRV5055
VCC
OUT
BODY SIZE (NOM)
Controller
VL (MAX)
ADC
VCC / 2
GND
Copyright © 201 7, Texas Instrumen ts Incorpor ate d
0V
north
VL (MIN)
0 mT
B
south
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV5055
SBAS640 – JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Magnetic Characteristics...........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 14
8.3 Do's and Don'ts ...................................................... 16
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Examples................................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
January 2018
*
Initial release.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
DRV5055
www.ti.com
SBAS640 – JANUARY 2018
5 Pin Configuration and Functions
DBZ Package
3-Pin SOT-23
Top View
LPG Package
3-Pin TO-92
Top View
1
VCC
3
OUT
GND
2
1
2
VCC
3
GND OUT
Pin Functions
PIN
NAME
SOT-23
TO-92
VCC
1
1
OUT
2
GND
3
I/O
DESCRIPTION
—
Power supply. TI recommends connecting this pin to a ceramic capacitor to ground
with a value of at least 0.01 µF.
3
O
Analog output
2
—
Ground reference
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Power supply voltage
VCC
–0.3
7
V
Output voltage
OUT
–0.3
VCC + 0.3
V
Magnetic flux density, BMAX
Unlimited
T
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
3
DRV5055
SBAS640 – JANUARY 2018
www.ti.com
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
±2500
Charged-device model (CDM), per JEDEC specification
JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Power supply voltage (1)
IO
Output continuous current
TA
Operating ambient temperature (2)
(1)
(2)
MIN
MAX
3
3.63
4.5
5.5
UNIT
V
–1
1
mA
–40
125
°C
There are two isolated operating VCC ranges. For more information see the Operating VCC Ranges section.
Power dissipation and thermal limits must be observed.
6.4 Thermal Information
DRV5055
THERMAL METRIC
(1)
SOT-23 (DBZ)
TO-92 (LPG)
3 PINS
3 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
170
121
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66
67
°C/W
RθJB
Junction-to-board thermal resistance
49
97
°C/W
YJT
Junction-to-top characterization parameter
1.7
7.6
°C/W
YJB
Junction-to-board characterization parameter
48
97
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
for VCC = 3 V to 3.63 V and 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
ICC
Operating supply current
tON
Power-on time (see Figure 11)
fBW
Sensing bandwidth
td
Propagation delay time
BND
Input-referred RMS noise density
BN
Input-referred noise
VN
(1)
(2)
4
Output-referred noise (2)
B = 0 mT, no load on OUT
From change in B to change in OUT
MIN
TYP
MAX
6
10
175
330
10
µs
VCC = 3.3 V
215
BN × S
µs
kHz
130
VCC = 5 V
mA
20
VCC = 5 V
BND × 6.6 × √20 kHz
UNIT
0.12
VCC = 3.3 V
0.2
DRV5055A1
12
DRV5055A2
6
DRV5055A3
3
DRV5055A4
1.5
nT/√Hz
mTPP
mVPP
B is the applied magnetic flux density.
VN describes voltage noise on the device output. If the full device bandwidth is not needed, noise can be reduced with an RC filter.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
DRV5055
www.ti.com
SBAS640 – JANUARY 2018
6.6 Magnetic Characteristics
for VCC = 3 V to 3.63 V and 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
2.43
2.5
2.57
1.59
1.65
1.71
B = 0 mT, TA = 25°C
VQΔT
Quiescent voltage temperature drift
B = 0 mT,
TA = -40°C to 125°C versus 25°C
VQRE
Quiescent voltage ratiometry error (2)
Sensitivity
VCC = 5 V,
TA = 25°C
Linear magnetic sensing range (3) (4)
VCC = 3.3 V,
TA = 25°C
VL
Linear range of output voltage (4)
STC
Sensitivity temperature compensation
for magnets (5)
SLE
Sensitivity linearity error (4)
SSE
Sensitivity symmetry error
(4)
SRE
Sensitivity ratiometry error
SΔL
Sensitivity lifetime drift
(1)
(2)
(3)
(4)
(5)
(2)
V
V
±0.2%
VCC = 3.3 V,
TA = 25°C
BL
UNIT
±1% × VCC
High-temperature operating stress for
1000 hours
VCC = 5 V,
TA = 25°C
S
MAX
VCC = 3.3 V
Quiescent voltage
Quiescent voltage lifetime drift
TYP
VCC = 5 V
VQ
VQΔL
MIN
<0.5%
DRV5055A1
95
100
105
DRV5055A2
47.5
50
52.5
DRV5055A3
23.8
25
26.2
DRV5055A4
11.9
12.5
13.2
DRV5055A1
57
60
63
DRV5055A2
28.5
30
31.5
DRV5055A3
14.3
15
15.8
DRV5055A4
7.1
7.5
7.9
DRV5055A1
±21
DRV5055A2
±42
DRV5055A3
±85
DRV5055A4
±169
DRV5055A1
±22
DRV5055A2
±44
DRV5055A3
±88
DRV5055A4
±176
mV/mT
mT
0.2
VCC – 0.2
0.12
VOUT is within VL
±1%
VOUT is within VL
±1%
TA = 25°C,
with respect to VCC = 3.3 V or 5 V
High-temperature operating stress for
1000 hours
–2.5%
V
%/°C
2.5%
<0.5%
%
B is the applied magnetic flux density.
See the Ratiometric Architecture section.
BL describes the minimum linear sensing range at 25°C taking into account the maximum VQ and Sensitivity tolerances.
See the Sensitivity Linearity section.
STC describes the rate the device increases Sensitivity with temperature. For more information, see the Sensitivity Temperature
Compensation For Magnets section.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
5
DRV5055
SBAS640 – JANUARY 2018
www.ti.com
6.7 Typical Characteristics
for TA = 25°C (unless otherwise noted)
2.8
2.6
2.6
Quiescent Voltage (V)
Quiescent Voltage (V)
2.4
2.2
2
VCC = 3.3 V
VCC = 5 V
1.8
2.4
2.2
2
1.8
1.6
1.6
-40
1.4
-20
0
20
40
60
80
Temperature (qC)
100
120
140
3
3.25
3.5
3.75
D002
Figure 1. Quiescent Voltage vs Temperature
4 4.25 4.5 4.75
Supply Voltage (V)
5.25
5.5
D003
Figure 2. Quiescent Voltage vs Supply Voltage
80
120
100
60
DRV5055A1
DRV5055A2
DRV5055A3
DRV5055A4
Sensitivity (mV/mT)
Sensitivity (mV/mT)
5
40
DRV5055A1
DRV5055A2
DRV5055A3
DRV5055A4
80
60
40
20
20
0
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
0
-40
140
20
40
60
80
Temperature (qC)
100
120
140
D005
Figure 4. Sensitivity vs Temperature, VCC = 5 V
100
DRV5055A1
DRV5055A2
DRV5055A3
DRV5055A4
DRV055A1
DRV055A2
DRV055A3
DRV055A4
80
60
40
20
3
3.1
3.2
3.3
3.4
Supply Voltage (V)
3.5
0
4.5
3.6
4.6
D006
Figure 5. Sensitivity vs Supply Voltage, VCC = 3.3 V ±10%
6
0
120
Sensitivity (mV/mT)
Sensitivity (mV/mT)
Figure 3. Sensitivity vs Temperature, VCC = 3.3 V
70
65
60
55
50
45
40
35
30
25
20
15
10
5
-20
D004
4.7
4.8
4.9
5
5.1 5.2
Supply Voltage (V)
5.3
5.4
5.5
D007
Figure 6. Sensitivity vs Supply Voltage, VCC = 5 V ±10%
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
DRV5055
www.ti.com
SBAS640 – JANUARY 2018
Typical Characteristics (continued)
for TA = 25°C (unless otherwise noted)
Operating Supply Current (mA)
6.6
6.4
6.2
6
5.8
5.6
5.4
VCC = 3.3 V
VCC = 5 V
5.2
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D001
Figure 7. Operating Supply Current vs Temperature
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
7
DRV5055
SBAS640 – JANUARY 2018
www.ti.com
7 Detailed Description
7.1 Overview
The DRV5055 is a 3-pin linear Hall effect sensor with fully integrated signal conditioning, temperature
compensation circuits, mechanical stress cancellation, and amplifiers. The device operates from 3.3-V and 5-V
(±10%) power supplies, measures magnetic flux density, and outputs a proportional analog voltage that is
referenced to VCC.
7.2 Functional Block Diagram
Element Bias
Offset
Cancellation
Temperature
Compensation
Bandgap
Reference
VCC
Trim
Registers
GND
0.01 F
(minimum)
VCC
Optional filter
Precision
Amplifier
OUT
Output
Driver
Copyright © 201 7, Texas Instrumen ts Incorpor ate d
7.3 Feature Description
7.3.1 Magnetic Flux Direction
As shown in Figure 8, the DRV5055 is sensitive to the magnetic field component that is perpendicular to the top
of the package.
TO-92
B
B
SOT-23
PCB
Figure 8. Direction of Sensitivity
8
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
DRV5055
www.ti.com
SBAS640 – JANUARY 2018
Feature Description (continued)
Magnetic flux that travels from the bottom to the top of the package is considered positive in this document. This
condition exists when a south magnetic pole is near the top (marked-side) of the package. Magnetic flux that
travels from the top to the bottom of the package results in negative millitesla values.
N
S
S
PCB
N
PCB
Figure 9. The Flux Direction for Positive B
7.3.2 Magnetic Response
When the DRV5055 is powered, the DRV5055 outputs an analog voltage according to Equation 1:
(
)
VOUT = VQ + B × Sensitivity (25°C) × (1 + STC × (TA ± 25° C))
where
•
•
•
•
•
•
VQ is typically half of VCC
B is the applied magnetic flux density
Sensitivity(25°C) depends on the device option and VCC
STC is typically 0.12%/°C
TA is the ambient temperature
VOUT is within the VL range
(1)
As an example, consider the DRV5055A3 with VCC = 3.3 V, a temperature of 50°C, and 67 mT applied.
Excluding tolerances, VOUT = 1650 mV + 67 mT × (15 mV/mT × (1 + 0.0012/°C × (50°C – 25°C))) = 2685 mV.
7.3.3 Sensitivity Linearity
The device produces a linear response when the output voltage is within the specified VL range. Outside this
range, sensitivity is reduced and nonlinear. Figure 10 graphs the magnetic response.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
9
DRV5055
SBAS640 – JANUARY 2018
www.ti.com
Feature Description (continued)
OUT
VCC
VL (MAX)
VCC / 2
0V
north
VL (MIN)
B
south
0 mT
Figure 10. Magnetic Response
Equation 2 calculates parameter BL, the minimum linear sensing range at 25°C taking into account the maximum
quiescent voltage and sensitivity tolerances.
VL(MAX) ± VQ(MAX)
BL(MIN) =
S(MAX)
(2)
The parameter SLE defines linearity error as the difference in sensitivity between any two positive B values, and
any two negative B values, while the output is within the VL range.
The parameter SSE defines symmetry error as the difference in sensitivity between any positive B value and the
negative B value of the same magnitude, while the output voltage is within the VL range.
7.3.4 Ratiometric Architecture
The DRV5055 has a ratiometric analog architecture that scales the quiescent voltage and sensitivity linearly with
the power-supply voltage. For example, the quiescent voltage and sensitivity are 5% higher when VCC = 5.25 V
compared to VCC = 5 V. This behavior enables external ADCs to digitize a consistent value regardless of the
power-supply voltage tolerance, when the ADC uses VCC as its reference.
Equation 3 calculates sensitivity ratiometry error:
S(VCC) / S(5V)
SRE = 1 ±
for V CC = 4.5 V to 5.5 V,
VCC / 5V
SRE = 1 ±
S(VCC) / S(3.3V)
VCC / 3.3V
for V CC = 3 V to 3.63 V
where
•
•
•
S(VCC) is the sensitivity at the current VCC voltage
S(5V) or S(3.3V) is the sensitivity when VCC = 5 V or 3.3 V
VCC is the current VCC voltage
Equation 4 calculates quiescent voltage ratiometry error:
VQ(VCC) / VQ(5V)
VQRE = 1 ±
for V CC = 4.5 V to 5.5 V,
VCC / 5V
VQRE = 1 ±
(3)
VQ(VCC) / VQ(3.3V)
VCC / 3.3V
for V CC = 3 V to 3.63 V
where
•
•
•
10
VQ(VCC) is the quiescent voltage at the current VCC voltage
VQ(5V) or VQ(3.3V) is the quiescent voltage when VCC = 5 V or 3.3 V
VCC is the current VCC voltage
Submit Documentation Feedback
(4)
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
DRV5055
www.ti.com
SBAS640 – JANUARY 2018
Feature Description (continued)
7.3.5 Operating VCC Ranges
The DRV5055 has two recommended operating VCC ranges: 3 V to 3.63 V and 4.5 V to 5.5 V. When VCC is in
the middle region between 3.63 V to 4.5 V, the device continues to function, but sensitivity is less known
because there is a crossover threshold near 4 V that adjusts device characteristics.
7.3.6 Sensitivity Temperature Compensation For Magnets
Magnets generally produce weaker fields as temperature increases. The DRV5055 compensates by increasing
sensitivity with temperature, as defined by the parameter STC. The sensitivity at TA = 125°C is typically 12%
higher than at TA = 25°C.
7.3.7 Power-On Time
After the VCC voltage is applied, the DRV5055 requires a short initialization time before the output is set. The
parameter tON describes the time from when VCC crosses 3 V until OUT is within 5% of VQ, with 0 mT applied
and no load attached to OUT. Figure 11 shows this timing diagram.
VCC
3V
tON
time
Output
95% × V Q
Invalid
time
Figure 11. tON Definition
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
11
DRV5055
SBAS640 – JANUARY 2018
www.ti.com
Feature Description (continued)
7.3.8 Hall Element Location
Figure 12 shows the location of the sensing element inside each package option.
SOT-23
Top View
SOT-23
Side View
centered
650 µm
±50 µm
±80 µm
TO-92
Top View
2 mm
2 mm
TO-92
Side View
1.54 mm
1.61 mm
±50 µm
1030 µm
±115 µm
Figure 12. Hall Element Location
7.4 Device Functional Modes
The DRV5055 has one mode of operation that applies when the Recommended Operating Conditions are met.
12
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
DRV5055
www.ti.com
SBAS640 – JANUARY 2018
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Selecting the Sensitivity Option
Select the highest DRV5055 sensitivity option that can measure the required range of magnetic flux density, so
that the output voltage swing is maximized.
Larger-sized magnets and farther sensing distances can generally enable better positional accuracy than very
small magnets at close distances, because magnetic flux density increases exponentially with the proximity to a
magnet. TI created an online tool to help with simple magnet calculations at http://www.ti.com/product/drv5013.
8.1.2 Temperature Compensation for Magnets
The DRV5055 temperature compensation is designed to directly compensate the average drift of neodymium
(NdFeB) magnets and partially compensate ferrite magnets. The residual induction (Br) of a magnet typically
reduces by 0.12%/°C for NdFeB, and 0.20%/°C for ferrite. When the operating temperature of a system is
reduced, temperature drift errors are also reduced.
8.1.3 Adding a Low-Pass Filter
As shown in the Functional Block Diagram, an RC low-pass filter can be added to the device output for the
purpose of minimizing voltage noise when the full 20-kHz bandwidth is not needed. This filter can improve the
signal-to-noise ratio (SNR) and overall accuracy. Do not connect a capacitor directly to the device output without
a resistor in between because doing so can make the output unstable.
8.1.4 Designing for Wire Break Detection
Some systems must detect if interconnect wires become open or shorted. The DRV5055 can support this
function.
First, select a sensitivity option that causes the output voltage to stay within the VL range during normal
operation. Second, add a pullup resistor between OUT and VCC. TI recommends a value between 20 kΩ to
100 kΩ, and the current through OUT must not exceed the IO specification, including current going into an
external ADC. Then, if the output voltage is ever measured to be within 150 mV of VCC or GND, a fault condition
exists. Figure 13 shows the circuit, and Table 1 describes fault scenarios.
PCB
DRV5055
VCC
OUT
VCC
Cable
VOUT
GND
Copyright © 201 7, Texas Instrumen ts Incorpor ate d
Figure 13. Wire Fault Detection Circuit
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
13
DRV5055
SBAS640 – JANUARY 2018
www.ti.com
Table 1. Fault Scenarios and the Resulting VOUT
FAULT SCENARIO
VOUT
VCC disconnects
Close to GND
GND disconnects
Close to VCC
VCC shorts to OUT
Close to VCC
GND shorts to OUT
Close to GND
8.2 Typical Application
S
N
Figure 14. Common Magnet Orientation
8.2.1 Design Requirements
Use the parameters listed in Table 2 for this design example.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VCC
5V
Magnet
15 × 5 × 5 mm NdFeB
Travel distance
12 mm
Maximum B at the sensor at 25°C
±75 mT
Device option
DRV5055A3
8.2.2 Detailed Design Procedure
Linear Hall effect sensors provide flexibility in mechanical design, because many possible magnet orientations
and movements produce a usable response from the sensor. Figure 14 shows one of the most common
orientations, which uses the full north to south range of the sensor and causes a close-to-linear change in
magnetic flux density as the magnet moves across.
When designing a linear magnetic sensing system, always consider these three variables: the magnet, sensing
distance, and the range of the sensor. Select the DRV5055 with the highest sensitivity that has a BL (linear
magnetic sensing range) that is larger than the maximum magnetic flux density in the application. To determine
the magnetic flux density the sensor receives, TI recommends using magnetic field simulation software, referring
to magnet specifications, and testing.
14
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
DRV5055
www.ti.com
SBAS640 – JANUARY 2018
8.2.3 Application Curve
Figure 15 shows the simulated magnetic flux from a NdFeB magnet.
Figure 15. Simulated Magnetic Flux
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
15
DRV5055
SBAS640 – JANUARY 2018
www.ti.com
8.3 Do's and Don'ts
Because the Hall element is sensitive to magnetic fields that are perpendicular to the top of the package, a
correct magnet approach must be used for the sensor to detect the field. Figure 16 shows correct and incorrect
approaches.
CORRECT
N
S
S
N
N
S
INCORRECT
N
S
Figure 16. Correct and Incorrect Magnet Approaches
16
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
DRV5055
www.ti.com
SBAS640 – JANUARY 2018
9 Power Supply Recommendations
A decoupling capacitor close to the device must be used to provide local energy with minimal inductance. TI
recommends using a ceramic capacitor with a value of at least 0.01 µF.
10 Layout
10.1 Layout Guidelines
Magnetic fields pass through most nonferromagnetic materials with no significant disturbance. Embedding Hall
effect sensors within plastic or aluminum enclosures and sensing magnets on the outside is common practice.
Magnetic fields also easily pass through most printed-circuit boards, which makes placing the magnet on the
opposite side possible.
10.2 Layout Examples
VCC
GND
VCC
GND
OUT
OUT
Figure 17. Layout Examples
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
17
DRV5055
SBAS640 – JANUARY 2018
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Using Linear Hall Effect Sensors to Measure Angle
• Incremental Rotary Encoder Design Considerations
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: DRV5055
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV5055A1QDBZR
PREVIEW
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
55A1
DRV5055A1QDBZT
PREVIEW
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
55A1
DRV5055A1QLPG
PREVIEW
TO-92
LPG
3
1000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
55A1
DRV5055A1QLPGM
PREVIEW
TO-92
LPG
3
3000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
55A1
DRV5055A2QDBZR
PREVIEW
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
55A2
DRV5055A2QDBZT
PREVIEW
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
55A2
DRV5055A2QLPG
PREVIEW
TO-92
LPG
3
1000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
55A2
DRV5055A2QLPGM
PREVIEW
TO-92
LPG
3
3000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
55A2
DRV5055A3QDBZR
PREVIEW
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
55A3
DRV5055A3QDBZT
PREVIEW
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
55A3
DRV5055A3QLPG
PREVIEW
TO-92
LPG
3
1000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
55A3
DRV5055A3QLPGM
PREVIEW
TO-92
LPG
3
3000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
55A3
DRV5055A4QDBZR
PREVIEW
SOT-23
DBZ
3
3000
TBD
Call TI
Call TI
-40 to 125
55A4
DRV5055A4QDBZT
PREVIEW
SOT-23
DBZ
3
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
55A4
DRV5055A4QLPG
PREVIEW
TO-92
LPG
3
1000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
55A4
DRV5055A4QLPGM
PREVIEW
TO-92
LPG
3
3000
Green (RoHS
& no Sb/Br)
CU SN
N / A for Pkg Type
-40 to 125
55A4
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2018
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DRV5055 :
• Automotive: DRV5055-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DRV5055A1QDBZR
SOT-23
DBZ
3
3000
180.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.15
2.77
1.22
4.0
8.0
Q3
DRV5055A1QDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5055A2QDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5055A2QDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5055A3QDBZR
SOT-23
DBZ
3
3000
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5055A3QDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
DRV5055A4QDBZT
SOT-23
DBZ
3
250
180.0
8.4
3.15
2.77
1.22
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jan-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV5055A1QDBZR
SOT-23
DBZ
3
3000
213.0
191.0
35.0
DRV5055A1QDBZT
SOT-23
DBZ
3
250
213.0
191.0
35.0
DRV5055A2QDBZR
SOT-23
DBZ
3
3000
213.0
191.0
35.0
DRV5055A2QDBZT
SOT-23
DBZ
3
250
213.0
191.0
35.0
DRV5055A3QDBZR
SOT-23
DBZ
3
3000
213.0
191.0
35.0
DRV5055A3QDBZT
SOT-23
DBZ
3
250
213.0
191.0
35.0
DRV5055A4QDBZT
SOT-23
DBZ
3
250
213.0
191.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
LPG0003A
TO-92 - 5.05 mm max height
SCALE 1.300
TRANSISTOR OUTLINE
4.1
3.9
3.25
3.05
3X
0.55
0.40
5.05
MAX
3
1
3X (0.8)
3X
15.5
15.1
3X
0.48
0.35
3X
2X 1.27 0.05
0.51
0.36
2.64
2.44
2.68
2.28
1.62
1.42
2X (45 )
1
(0.5425)
2
3
0.86
0.66
4221343/C 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
LPG0003A
TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE
0.05 MAX
ALL AROUND
TYP
FULL R
TYP
METAL
TYP
(1.07)
3X ( 0.75) VIA
2X
METAL
(1.7)
2X (1.7)
2
1
2X
SOLDER MASK
OPENING
3
2X (1.07)
(R0.05) TYP
(1.27)
SOLDER MASK
OPENING
(2.54)
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE:20X
4221343/C 01/2018
www.ti.com
TAPE SPECIFICATIONS
LPG0003A
TO-92 - 5.05 mm max height
TRANSISTOR OUTLINE
0
13.0
12.4
1
0
1
1 MAX
21
18
2.5 MIN
6.5
5.5
9.5
8.5
0.25
0.15
19.0
17.5
3.8-4.2 TYP
6.55
6.15
12.9
12.5
0.45
0.35
4221343/C 01/2018
www.ti.com
4203227/C
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.4
1.2
PIN 1
INDEX AREA
1.12 MAX
B
A
0.1 C
1
0.95
3.04
2.80
1.9
3X
3
0.5
0.3
0.2
2
(0.95)
C A B
0.25
GAGE PLANE
0 -8 TYP
0.10
TYP
0.01
0.20
TYP
0.08
0.6
TYP
0.2
SEATING PLANE
4214838/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214838/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated