EN29LV641H/L EN29LV640U EN29LV641H/L EN29LV640U 64 Megabit (4096K x 16-bit) Flash Memory, CMOS 3.0 Volt-only Uniform Sector Flash Memory FEATURES • Single power supply operation - Full voltage range: 2.7 to 3.6 volts for read, erase and program operations • Low power consumption (typical values at 5 MHz) - 9 mA typical active read current - 20 mA typical program/erase current - Less than 1 µA current in standby or automatic sleep mode. • JEDEC standards compatible - Pinout and software compatible with singlepower supply Flash standard Software features: • Sector Group Protection - Provide locking of sectors to prevent program or erase operations within individual sectors - Additionally, temporary Sector Group Unprotect allows code changes in previously protected sectors. • Standard DATA# polling and toggle bits feature • Unlock Bypass Program command supported • Sector Erase Suspend / Resume modes: Read and program another Sector during Sector Erase Suspend Mode • Manufactured on 0.18μm process technology • Support JEDEC Common Flash Interface (CFI). • Flexible Sector Architecture: - One hundred and twenty-eight 32K-Word sectors. • Minimum 100K program/erase endurance cycles. • - High performance for program and erase Word program time: 8µs typical Sector Erase time: 500ms typical Chip Erase time: 64s typical • Package Options Hardware features: • RESET# hardware reset pin - Hardware method to reset the device to read mode. • WP# input pin - Write Protect (WP#) function allows protection of first or last 32K-word sector, regardless of previous sector protect status • ACC input pin - Acceleration (ACC) function provides accelerated program times for higher throughput for manufacturing. - 48-pin TSOP - 63 ball 11mm x 12mm FBGA GENERAL DESCRIPTION The EN29LV641H/L / EN29LV640U is a 64-Megabit (4,194,304x16), electrically erasable, read/write non-volatile flash memory. Any word can be programmed typically in 8µs. This device is entirely command set compatible with the JEDEC single-power-supply Flash standard. The EN29LV641H/L / EN29LV640U is designed to allow either single Sector or full Chip erase operation, where each Sector Group can be protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector. This Data Sheet may be revised by subsequent versions 1 or modifications due to changes in technical specifications. ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U PRODUCT SELECTOR GUIDE Product Number EN29LV641H/L / EN29LV640U Regulated Voltage Range: VCC=3.0 – 3.6 V 70R Speed Option Full Voltage Range: VCC=2.7 – 3.6 V 90 Max Access Time (ns) 70 90 Max CE# Access Time (ns) 70 90 Max OE# Access Time (ns) 30 35 BLOCK DIAGRAM RY/BY# VCC VSS RESET# DQ15-DQ0 Sector Protect Switches Erase Voltage Generator Input/Output Buffers State Control WE# WP# ACC# Command Register Program Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector Timer Address Latch STB STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix A21-A0 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 2 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U CONNECTION DIAGRAMS Note: No RY/BY# pin for TSOP package , VIO should be tied directly to VCC. Note: No WP# pin for FBGA package VIO should be tied directly to VCC. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 3 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U TABLE 1. PIN DESCRIPTION Pin Name Function A21-A0 22 Address inputs DQ15-DQ0 16 Data Inputs/Outputs LOGIC DIAGRAM A21 – A0 DQ15 – DQ0 CE# Chip Enable Input CE# OE# Output Enable Input OE# WE# WE# Write Enable Input WP# WP# Hardware Write Protect Input ACC Acceleration Input RY/BY# Ready/Busy status output RESET# Hardware Reset Input Pin Vcc Supply Voltage (2.7-3.6V) VIO Output Buffer Power Supply this pin should be tied directly to VCC Vss Ground NC Not Connected to anything ACC RESET# VIO This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Note: WP# pins are for EN29LV641H/L only. RY/BY# is available for EN29LV640U only. 4 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 RY/BY# EN29LV641H/L EN29LV640U ORDERING INFORMATION EN29LV641 H ─ 90 T I P PACKAGING CONTENT (Blank) = Conventional P = Pb Free TEMPERATURE RANGE I = Industrial (-40°C to +85°C) C = Commercial (0°C to +70°C) PACKAGE T = 48-pin TSOP W= 63-Ball Fine Pitch Ball Grid Array (FBGA) 0.80mm pitch, 11mm x 12mm package SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR for WRITE PROTECT (WP#=0) H = highest address sector protected L = lowest address sector protected BASE PART NUMBER EN29LV641 / EN29LV640U 64 Megabit(4M x 16-Bit) Uniform Sector Flash Optional Data I/O voltage 3V Read, Erase and Program PRODUCT SELECTOR GUIDE Valid Combinations for TSOP Packages EN29LV641H–90 EN29LV641L–90 EN29LV641H–70R, EN29LV641L–70R Vcc Vcc = 2.7V-3.6V TI, TC Vcc = 3.0V-3.6V Valid Combinations for FBGA Packages EN29LV640U–90 EN29LV640U–70R Vcc Vcc = 2.7V-3.6V WI, WC This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Vcc = 3.0V-3.6V 5 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Table 2. Sector (Group) Address Tables Sector Group Protect/Unprotect Sector Group SG0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 A21-A17 Sector Address Range for Sector Erase Sector A21 A20 A19 A18 A17 A16 A15 Address Range (hexadecimal) SA0 0 0 0 0 0 0 0 000000–007FFF SA1 0 0 0 0 0 0 1 008000–00FFFF SA2 0 0 0 0 0 1 0 010000–017FFF SA3 0 0 0 0 0 1 1 018000–01FFFF SA4 0 0 0 0 1 0 0 020000–027FFF SA5 0 0 0 0 1 0 1 028000–02FFFF SA6 0 0 0 0 1 1 0 030000–037FFF SA7 0 0 0 0 1 1 1 038000–03FFFF SA8 0 0 0 1 0 0 0 040000–047FFF SA9 0 0 0 1 0 0 1 048000–04FFFF SA10 0 0 0 1 0 1 0 050000–057FFF SA11 0 0 0 1 0 1 1 058000–05FFFF SA12 0 0 0 1 1 0 0 060000–067FFF SA13 0 0 0 1 1 0 1 068000–06FFFF SA14 0 0 0 1 1 1 0 070000–077FFF SA15 0 0 0 1 1 1 1 078000–07FFFF SA16 0 0 1 0 0 0 0 080000–087FFF SA17 0 0 1 0 0 0 1 088000–08FFFF SA18 0 0 1 0 0 1 0 090000–097FFF SA19 0 0 1 0 0 1 1 098000–09FFFF SA20 0 0 1 0 1 0 0 0A0000–0A7FFF SA21 0 0 1 0 1 0 1 0A8000–0AFFFF SA22 0 0 1 0 1 1 0 0B0000–0B7FFF SA23 0 0 1 0 1 1 1 0B8000–0BFFFF SA24 0 0 1 1 0 0 0 0C0000–0C7FFF SA25 0 0 1 1 0 0 1 0C8000–0CFFFF SA26 0 0 1 1 0 1 0 0D0000–0D7FFF SA27 0 0 1 1 0 1 1 0D8000–0DFFFF SA28 0 0 1 1 1 0 0 0E0000–0E7FFF SA29 0 0 1 1 1 0 1 0E8000–0EFFFF SA30 0 0 1 1 1 1 0 0F0000–0F7FFF SA31 0 0 1 1 1 1 1 0F8000–0FFFFF 00000 00001 00010 00011 00100 00101 00110 00111 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 6 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Sector Group SG8 SG9 SG10 SG11 SG12 SG13 SG14 SG15 A21-A17 Sector A21 A20 A19 A18 A17 A16 A15 Address Range (hexadecimal) SA32 0 1 0 0 0 0 0 100000–107FFF SA33 0 1 0 0 0 0 1 108000–10FFFF SA34 0 1 0 0 0 1 0 110000–117FFF SA35 0 1 0 0 0 1 1 118000–11FFFF SA36 0 1 0 0 1 0 0 120000–127FFF SA37 0 1 0 0 1 0 1 128000–12FFFF SA38 0 1 0 0 1 1 0 130000–137FFF SA39 0 1 0 0 1 1 1 138000–13FFFF SA40 0 1 0 1 0 0 0 140000–147FFF SA41 0 1 0 1 0 0 1 148000–14FFFF SA42 0 1 0 1 0 1 0 150000–157FFF SA43 0 1 0 1 0 1 1 158000–15FFFF SA44 0 1 0 1 1 0 0 160000–167FFF SA45 0 1 0 1 1 0 1 168000–16FFFF SA46 0 1 0 1 1 1 0 170000–177FFF SA47 0 1 0 1 1 1 1 178000–17FFFF SA48 0 1 1 0 0 0 0 180000–187FFF SA49 0 1 1 0 0 0 1 188000–18FFFF SA50 0 1 1 0 0 1 0 190000–197FFF SA51 0 1 1 0 0 1 1 198000–19FFFF SA52 0 1 1 0 1 0 0 1A0000–1A7FFF SA53 0 1 1 0 1 0 1 1A8000–1AFFFF SA54 0 1 1 0 1 1 0 1B0000–1B7FFF SA55 0 1 1 0 1 1 1 1B8000–1BFFFF SA56 0 1 1 1 0 0 0 1C0000–1C7FFF SA57 0 1 1 1 0 0 1 1C8000–1CFFFF SA58 0 1 1 1 0 1 0 1D0000–1D7FFF SA59 0 1 1 1 0 1 1 1D8000–1DFFFF SA60 0 1 1 1 1 0 0 1E0000–1E7FFF SA61 0 1 1 1 1 0 1 1E8000–1EFFFF SA62 0 1 1 1 1 1 0 1F0000–1F7FFF SA63 0 1 1 1 1 1 1 1F8000–1FFFFF 01000 01001 01010 01011 01100 01101 01110 01111 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 7 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Sector Group SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 A21-A17 Sector A21 A20 A19 A18 A17 A16 A15 Address Range (hexadecimal) SA64 1 0 0 0 0 0 0 200000–207FFF SA65 1 0 0 0 0 0 1 208000–20FFFF SA66 1 0 0 0 0 1 0 210000–217FFF SA67 1 0 0 0 0 1 1 218000–21FFFF SA68 1 0 0 0 1 0 0 220000–227FFF SA69 1 0 0 0 1 0 1 228000–22FFFF SA70 1 0 0 0 1 1 0 230000–237FFF SA71 1 0 0 0 1 1 1 238000–23FFFF SA72 1 0 0 1 0 0 0 240000–247FFF SA73 1 0 0 1 0 0 1 248000–24FFFF SA74 1 0 0 1 0 1 0 250000–257FFF SA75 1 0 0 1 0 1 1 258000–25FFFF SA76 1 0 0 1 1 0 0 260000–267FFF SA77 1 0 0 1 1 0 1 268000–26FFFF SA78 1 0 0 1 1 1 0 270000–277FFF SA79 1 0 0 1 1 1 1 278000–27FFFF SA80 1 0 1 0 0 0 0 280000–287FFF SA81 1 0 1 0 0 0 1 288000–28FFFF SA82 1 0 1 0 0 1 0 290000–297FFF SA83 1 0 1 0 0 1 1 298000–29FFFF SA84 1 0 1 0 1 0 0 2A0000–2A7FFF SA85 1 0 1 0 1 0 1 2A8000–2AFFFF SA86 1 0 1 0 1 1 0 2B0000–2B7FFF SA87 1 0 1 0 1 1 1 2B8000–2BFFFF SA88 1 0 1 1 0 0 0 2C0000–2C7FFF SA89 1 0 1 1 0 0 1 2C8000–2CFFFF SA90 1 0 1 1 0 1 0 2D0000–2D7FFF SA91 1 0 1 1 0 1 1 2D8000–2DFFFF SA92 1 0 1 1 1 0 0 2E0000–2E7FFF SA93 1 0 1 1 1 0 1 2E8000–2EFFFF SA94 1 0 1 1 1 1 0 2F0000–2F7FFF SA95 1 0 1 1 1 1 1 2F8000–2FFFFF 10000 10001 10010 10011 10100 10101 10110 10111 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 8 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Sector Group SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 A21-A17 Sector A21 A20 A19 A18 A17 A16 A15 Address Range (hexadecimal) SA96 1 1 0 0 0 0 0 300000–307FFF SA97 1 1 0 0 0 0 1 308000–30FFFF SA98 1 1 0 0 0 1 0 310000–317FFF SA99 1 1 0 0 0 1 1 318000–31FFFF SA100 1 1 0 0 1 0 0 320000–327FFF SA101 1 1 0 0 1 0 1 328000–32FFFF SA102 1 1 0 0 1 1 0 330000–337FFF SA103 1 1 0 0 1 1 1 338000–33FFFF SA104 1 1 0 1 0 0 0 340000–347FFF SA105 1 1 0 1 0 0 1 348000–34FFFF SA106 1 1 0 1 0 1 0 350000–357FFF SA107 1 1 0 1 0 1 1 358000–35FFFF SA108 1 1 0 1 1 0 0 360000–367FFF SA109 1 1 0 1 1 0 1 368000–36FFFF SA110 1 1 0 1 1 1 0 370000–377FFF SA111 1 1 0 1 1 1 1 378000–37FFFF SA112 1 1 1 0 0 0 0 380000–387FFF SA113 1 1 1 0 0 0 1 388000–38FFFF SA114 1 1 1 0 0 1 0 390000–397FFF SA115 1 1 1 0 0 1 1 398000–39FFFF SA116 1 1 1 0 1 0 0 3A0000–3A7FFF SA117 1 1 1 0 1 0 1 3A8000–3AFFFF SA118 1 1 1 0 1 1 0 3B0000–3B7FFF SA119 1 1 1 0 1 1 1 3B8000–3BFFFF SA120 1 1 1 1 0 0 0 3C0000–3C7FFF SA121 1 1 1 1 0 0 1 3C8000–3CFFFF SA122 1 1 1 1 0 1 0 3D0000–3D7FFF SA123 1 1 1 1 0 1 1 3D8000–3DFFFF SA124 1 1 1 1 1 0 0 3E0000–3E7FFF SA125 1 1 1 1 1 0 1 3E8000–3EFFFF SA126 1 1 1 1 1 1 0 3F0000–3F7FFF SA127 1 1 1 1 1 1 1 3F8000–3FFFFF 11000 11001 11010 11011 11100 11101 11110 11111 Note: The sizes of all sectors are 32K-word. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 9 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U USER MODE DEFINITIONS TABLE 3. BUS OPERATIONS Operation CE# OE# WE# RESET# WP# ACC A21-A0 DQ15-DQ0 Read L L H H X X AIN DOUT Write L H L H (Note 1) X AIN Accelerated Program L H L H (Note 1) VHH Vcc ± 0.3V X X Vcc ± 0.3V X H X High-Z TTL Standby H X X H X H X High-Z Output Disable L H H H X X X High-Z Hardware Reset X X X L X X X High-Z CMOS Standby B B B B B Sector Group Protect L H L VID H X Sector Group Unprotect L H L VID H X Temporary Sector Group Unprotect X X X VID H X B B B B B B B B B (Note 3) B B B AIN B (Note 3) B B B SA, A6=L, A1=H, A0=L SA, A6=H, A1=H, A0=L AIN B B B (Note 3) (Note 3) (Note 3) L=logic low= VIL, H=Logic High= VIH, VID = VHH = 11 ± 0.5V = 10.5 ─ 11.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector Addresses (A21-A15), DIN=Data In, DOUT=Data Out, AIN=Address In B B B B B B B B B B B B Notes: 1. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the first or last sector independent of whether those sectors were protected or unprotected; if the system asserts VIH on the WP# pin, the device reverts to whether the first or last sector was previously protected or unprotected. If ACC = VHH, all sectors will be unprotected. B B B B 2. Please refer to “Sector Group Protection & Unprotection”, Flowchart 6a and Flowchart 6b. 3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm. Read Mode The device is automatically set to reading array data after device power-up or hardware reset. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm After the device accepts an Sector Erase Suspend command, the device enters the Sector Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Sector Erase Suspend mode, the system may once again read array This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 10 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U data with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional information. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high or while in the autoselect mode. See the “Reset Command” for additional details. Output Disable Mode When the OE# pin is at a logic high level (VIH), the output from the device is disabled. The output pins are placed in a high impedance state. B B Standby Mode The device has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical). It is placed in CMOS-compatible standby when the CE# pin is at VCC ± 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when the CE# pin is at VIH. When in standby modes, the outputs are in a high-impedance state independent of the OE# input. B B B B B B B Automatic Sleep Mode The device has an automatic sleep mode, which minimizes power consumption. The devices will enter this mode automatically when the states of address bus remain stable for tacc + 30ns. ICC4 in the DC Characteristics table shows the current specification. With standard access times, the device will output new data when addresses change. Writing Command Sequences To write a command or command sequence to program data to the device or erase data, the system has to drive WE# and CE# to VIL, and OE# to VIH. B B B The device has an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The system can also read the autoselect codes by entering the autoselect mode, which need the autoselect command sequence to be written. Please refer to the “Command Definitions” for all the available commands. Autoselect Identification Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying sector group protection, the sector group address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The “Command Definitions” table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0. B B To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See “Command Definitions” for details on using the autoselect mode. Note that a Reset command is required to return to read mode when the device is in the autoselect mode. B This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 11 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 B EN29LV641H/L EN29LV640U TABLE 4. Autoselect Codes (Using High Voltage, VID) B Description CE# OE# WE# Manufacturer ID: Eon L L H Autoselect Device ID L A21 to A15 A14 to A10 A9 X VID 2 P P A8 B A7 A6 A5 to A2 A1 A0 X L X L L 1 H P X B B XX1Ch P L L H X X VID B B X DQ15 to DQ0 XX7Fh X L X L H 22D7h XX01h Sector Protection Verification L L H SA X VID B B X X L X H L (Protected) XX00h (Unprotected) L=logic low= VIL, H=Logic High= VIH, VID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector Addresses B B B B B B Note: 1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh. 2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode. B B ACC: Accelerated Program Operation The device offers accelerated program operation which enables the programming in higher speed. When ACC is raised to VHH, the memory automatically enters the Unlock Bypass mode (please refer to “Command Definitions”), temporarily unprotects every protected sector groups, and reduces the time required for program operation. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. When ACC returns to VIH or VIL, normal operation resumes. The transitions from VIH or VIL to VHH and from VHH to VIH or VIL must be slower than tVHH, see Figure 5. Note that the ACC pin must not be left floating or unconnected. In addition, ACC pin must not be at VHH for operations other than accelerated program. It could cause the device to be damaged. Never raise this pin to VHH from any mode except Read mode; otherwise the memory may be left in an indeterminate state. A 0.1µF capacitor should be connected between the ACC pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program. RESET#: Hardware Reset When RESET# is driven low for tRP, all output pins are tristates. All commands written in the internal state machine are reset to reading array data. B B Please refer to timing diagram for RESET# pin in “AC Characteristics”. Sector Group Protection & Unprotection The hardware sector group protection feature disables both program and erase operations in any sector group. The hardware chip unprotection feature re-enables both program and erase operations in previously This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 12 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U protected sector group. A sector group consists of four adjacent sectors that would be protected at the same time. Please see Table 2 which show the organization of sector groups. There are two methods to enable this hardware protection circuitry. The first one requires only that the RESET# pin be at VID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 6a and 6b for the algorithm and Figure 11 for the timings. When doing Sector Group Unprotect, all the unprotected sector groups must be protected prior to any unprotect write cycle. The second method is for programming equipment. This method requires VID to be applied to both OE# and A9 pins and non-standard microprocessor timings are used. This method is described in a separate document, the Datasheet Supplement of EN29LV641H/L / EN29LV640U, which can be obtained by contacting a representative of Eon Silicon Solution, Inc. U WP#: Write Protect The Write Protect function provides a hardware method to protect the first or last sector against erase and program without using VID. When WP# is Low, the device protects the first or last sector regardless of whether these sectors were previously protected or unprotected using the method described in “Sector Group Protection & Unprotection”, Program and Erase operations in these sectors are ignored. When WP# is High, the device reverts to the previous protection status of the first or last sector. Program and Erase operations can now modify the data in those sectors unless the sector is protected using Sector Group Protection. Note that the WP# pin must not be left floating or unconnected. Temporary Sector Group Unprotect Start This feature allows temporary unprotection of previously protected sector groups to change data while in-system. The Temporary Sector Group Unprotect mode is activated by setting the RESET# pin to VBID.B During this mode, formerly protected sector groups can be programmed or erased by simply selecting the sector group addresses. Once VBIDB is removed from the RESET# pin, all the previously protected sector groups are protected again. See accompanying flowchart and timing diagrams in Figure 10 for more details. Notes: 1. All protected sector groups are unprotected. (If WP#=VIL, the first or last sector will remain protected.) 2. Previously protected sector groups are protected again. B Reset#=VID (note 1) B B B B Perform Erase or Program Operations RESET#=VIH B B Temporary Sector Group Unprotect Completed (note 2) B B This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 13 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U COMMON FLASH INTERFACE (CFI) The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC IDindependent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-8.The upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode. Table 5. CFI Query Identification String Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 6. System Interface String Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0003h 0000h 000Ah 0000h 0005h 0000h 0002h 0000h Description Vcc Min (write/erase) DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt Vcc Max (write/erase) DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt Vpp Min. voltage (00h = no Vpp pin present) Vpp Max. voltage (00h = no Vpp pin present) Typical timeout per single byte/word write 2N µS Typical timeout for Min, size buffer write 2N µS (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max timeout for full chip erase 2N times typical (00h = not supported) P P P P P P P P P P P P P P P P Table 7. Device Geometry Definition This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 14 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0017h 0001h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 007Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Description Device Size = 2N bytes P P Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device P P Erase Block Region 1 Information (refer to the CFI specification of CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information Table 8. Primary Vendor-specific Extended Query Addresses 40h 41h 42h 43h 44h Data 0050h 0052h 0049h 0031h 0033h 45h 0004h 46h 0002h 47h 0004h 48h 0001h 49h 0004h 4Ah 0000h 4Bh 0000h 4Ch 0000h 4Dh 00A5h 4Eh 00B5h 4Fh 00XXh Description Query-unique ASCII string “PRI” Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0 = Required, 1 = Not Required Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page Minimum ACC (Acceleration) Supply Voltage 00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV Maximum ACC (Acceleration) Supply Voltage 00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV 00h = Uniform Sector Devices This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 15 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Hardware Data protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise. Low VCC Write Inhibit B B When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. B B B B B B Write Pulse “Glitch” protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read. B B B B B B Power-up Write Inhibit During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = VIL, WE#= VIL and OE# = VIH, the device will not accept commands on the rising edge of WE#. B B B B B B This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 16 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U COMMAND DEFINITIONS The operations of the device are selected by one or more commands written into the command register. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode. Table 9. EN29LV641H/L / EN29LV640U Command Definitions Cycles Bus Cycles (Note 1-2) Command Sequence st 1 Cycle P P Addr Data nd 2 rd th 3 Cycle 4 Cycle Cycle Addr Data Addr Data Addr P P P P P P Data th 5 Cycle P P th 6 Cycle P P Addr Data Addr Data 1 RA RD Reset 1 xxx F0 Manufacturer ID 4 555 AA 2AA 55 555 90 000 100 7F 1C Device ID 4 555 AA 2AA 55 555 90 X01 22D7 Sector Protect Verify (Note 4) 4 555 AA 2AA 55 555 90 (SA) X02 XX00 XX01 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program 2 XXX A0 PA PD Unlock Bypass Reset 2 XXX 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Sector Erase Suspend 1 BA B0 Sector Erase Resume 1 BA 30 CFI Query 1 55 98 Autoselect Read (Note 3) Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PA SA = Sector Address: address of the Sector to be erased or verified (in Autoselect mode). Address bits A21-A15 uniquely select any Sector. Notes: 1. Data bits DQ15-DQ8 are don’t care in command sequences, except for RD and PD. 2. Unless otherwise noted, address bits A21-A15 are don’t cares. 3. No unlock or command cycles required when device is in read mode. 4. The data is 00h for an unprotected sector group and 01h for a protected sector group. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 17 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Reading Array Data The device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. Following an Sector Erase Suspend command, Sector Erase Suspend mode is entered. The system can read array data using the standard read timings from sectors other than the one which is being erase-suspended. If the system reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Sector Erase Suspend mode, the system may once again read array data with the same exception. The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high during an active program or erase operation or while in the autoselect mode. See next section for details on Reset. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t-care for this command. The reset command may be written between the cycle sequences in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the cycle sequences in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Sector Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the cycle sequences in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies in Sector Erase Suspend mode). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices ID codes, and determine whether or not a sector group is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires VID on address bit A9 and is intended for commercial programmers. B B Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 9 any number of times, without needing another command sequence. The system must write the reset command to exit the autoselect mode and return to reading array data. Word Programming Command Programming is performed by using a four-bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#, whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 18 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Any commands written to the device during the program operation are ignored. Programming status can be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a “0” to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. When programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode. Programming is allowed in any sequence across sector boundaries. Unlock Bypass To speed up programming operation, the Unlock Bypass Command may be used. Once this feature is activated, the shorter two-cycle Unlock Bypass Program command can be used instead of the normal four-cycle Program Command to program the device. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset command can be accepted. This mode is exited after issuing the Unlock Bypass Reset Command. The device powers up with this feature disabled The device provides accelerated program operations through the ACC pin. When ACC is asserted to VHH, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass Program command sequence. B B Chip Erase Command Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Chip Erase algorithm are ignored. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. If there are several sectors to be erased, Sector Erase Command sequences must be issued for each sector. That is, only a sector address can be specified for each Sector Erase command. Users must issue another Sector Erase command for the next sector to be erased after the previous one is completed. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 19 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U using DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms. Sector Erase Suspend / Resume Command The Sector Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation. The Sector Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are don’t-cares when writing the Sector Erase Suspend command. When the Sector Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. Normal read and write timings and command definitions apply. Please note that Autoselect command sequence can not be accepted during Sector Erase Suspend. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The Autoselect command is not supported during Sector Erase Suspend Mode. The system must write the Sector Erase Resume command (address bits are don’t-care) to exit the sector erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Sector Erase Suspend command can be written after the device has resumed erasing. WRITE OPERATION STATUS DQ7: DATA# Polling The device provides DATA# polling on DQ7 to indicate the status of the embedded operations. The DATA# Polling feature is active during the Programming, Sector Erase, Chip Erase, and Sector Erase Suspend. (See Table 10) When the embedded programming is in progress, an attempt to read the device will produce the complement of the data written to DQ7. Upon the completion of the programming operation, an attempt to read the device will produce the true data written to DQ7. DATA# polling is valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence for program. When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output during the read cycles. For Chip Erase or Sector Erase, DATA# polling is valid after the rising edge of the last WE# or CE# pulse in the six-cycle sequence. DATA# Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the address used is in a protected sector. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 20 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable (OE#) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on the time the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operation and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 should be read on the subsequent read attempts. The flowchart for DATA# Polling (DQ7) is shown on Flowchart 4. The DATA# Polling (DQ7) timing diagram is shown in Figure 6. RY/BY#: Ready/Busy Status output The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. In the output-low period, signifying Busy, the device is actively erasing or programming. This includes programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. DQ6: Toggle Bit I The device provides a “Toggle Bit” on DQ6 to indicate the status of the embedded programming and erase operations. (See Table 10) During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by active OE# or CE#) will result in DQ6 toggling between “zero” and “one”. Once the embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During Programming, the Toggle Bit is valid after the rising edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after the rising edge of the sixth WE# pulse for sector erase or chip erase. In embedded programming, if the sector being written to is protected, DQ6 will toggles for about 2 µs, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected sectors are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read mode without changing data in all protected sectors. The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 5. The Toggle Bit timing diagram is shown in Figure 7. DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the DQ6 is toggling after detecting a “1” on DQ5. The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 21 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U DQ3: Sector Erase Timer After writing a sector erase command sequence, the output on DQ3 can be checked to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) When sector erase starts, DQ3 switches from “0” to “1”. This device does not support multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since it immediately shows as a “1” after the first 30h command. Future devices may support this feature. DQ2: Erase Toggle Bit II The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to the following table to compare outputs for DQ2 and DQ6. Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Flowchart 5 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, after the initial two read cycles, the system determines that the toggle bit is still toggling. And the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 22 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Write Operation Status Operation Standard Mode Sector Erase Suspend Mode DQ7 DQ6 DQ5 DQ3 DQ2 RY/BY# Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 1 No Toggle 0 N/A Toggle 1 Data Data Data Data Data 1 DQ7# Toggle 0 N/A N/A 0 Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend Program Table 10. Status Register Bits DQ Name Logic Level ‘1’ 7 DATA# POLLING ‘0’ DQ7 DQ7# ‘-1-0-1-0-1-0-1-’ 6 TOGGLE BIT DQ6 ‘-1-1-1-1-1-1-1-‘ 5 3 2 ERROR BIT SECTOR ERASE TIME BIT TOGGLE BIT Definition Erase Complete or erased sector in Sector Erase Suspend Erase On-Going Program Complete or data of non-erased sector during Sector Erase Suspend Program On-Going Erase or Program On-going Read during Sector Erase Suspend Erase Complete ‘1’ Program or Erase Error ‘0’ Program or Erase On-going ‘1’ Erase operation start ‘0’ Erase timeout period on-going ‘-1-0-1-0-1-0-1-’ DQ2 Chip Erase, Sector Erase or Read within EraseSuspended sector. (When DQ5=1, Erase Error due to currently addressed Sector or Program on Erase-Suspended sector Read on addresses of non Erase-Suspend sectors Notes: DQ7: DATA# Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. DQ6: Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going. DQ5: Error Bit: set to “1” if failure in programming or erase DQ3: Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES). DQ2: Toggle Bit: indicates the Erase status and allows identification of the erased Sector. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 23 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U EMBEDDED ALGORITHMS Flowchart 1. Embedded Chip Erase START Write Data AAh to Address 555h Write Data 55h to Address 2AAh Write Data 80h to Address 555h Write Data AAh to Address 555h Write Data 55h to Address 2AAh Write Data 10h to Address 555h Data Poll from System No DATA = FFh? Embedded Chip Erase in progress Yes Erasure Completed This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 24 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Flowchart 2. Embedded Sector Erase START Write Data AAh to Address 555h Write Data 55h to Address 2AAh Write Data 80h to Address 555h Write Data AAh to Address 555h Write Data 55h to Address 2AAh Write Data 30h to Sector Address Data Poll from System DATA = FFh? No Embedded Sector Erase in progress Yes No Last Sector to Erase? Yes Erasure Completed This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 25 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Flowchart 3. Embedded Program START Write Data AAh to Address 555h Write Data 55h to Address 2AAh Write Data A0h to Address 555h Write Programmed Data to Destination Address Data Poll from System No Verify OK? Embedded Program in progress Yes Increment Address No Last Address? Yes Program Completed This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 26 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Flowchart 4. DATA# Polling Algorithm Start Read DQ7-DQ0 Adr = VA DQ7 = Data? Yes No No DQ5 = 1? Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be re-checked even if DQ5 = “1” in case the first set of reads was done at the exact instant when the status data was in transition. Yes Read DQ7-DQ0 Adr = VA Yes DQ7 = Data? No Fail Pass Flowchart 5. Toggle Bit Algorithm Start Read DQ7-DQ0 twice No DQ6 = Toggle? Yes No DQ5 = 1? Yes Notes: 1. The system should be re-checked the toggle bit even if DQ5 = “1” in case the first set of reads was done at the exact instant when the status data was in transition. Read DQ7-DQ0 No DQ6 = Toggle? Yes Fail This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 27 Pass ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Flowchart 6a. In-System Sector Group Protect Flowchart START PLSCNT = 1 RESET# = VID Wait 1 µs Temporary Sector Group Unprotect Mode No First Write Cycle = 60h? Yes Set up sector group address To Protect: Write 60h to sector group addr with A6 = 0, A1 = 1, A0 = 0 Wait 150 µs To Verify: Write 40h to sector group address with A6 = 0, A1 = 1, A0 = 0 Increment PLSCNT Reset PLSCNT = 1 Wait 0.4 µs Read from sector address with A6 = 0, A1 = 1, A0 No PLSCNT = 25? No Data = 01h? Yes Yes Device failed Protect another sector? Yes No Remove VID from RESET# Write reset command Sector Group Protect Algorithm This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Sector Group Protect complete 28 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Flowchart 6b. In-System Sector Group Unprotect Flowchart START PLSCNT = 1 Protect all sector groups: The indicated portion of the sector group protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (see Diagram 6a.) RESET# = VID Wait 1 µS No Temporary Sector Group Unprotect Mode First Write Cycle = 60h? Yes No All sectors protected? Yes Set up first sector group address Unprotect: Write 60H to sector address with A6 = 1, A1 = 1, A0 = 0 Wait 15 ms Verify Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 =0 Increment PLSCNT Wait 0.4 µS No PLSCCNT = 1000? Read from sector group address with A6 = 1, A1 = 1, A0 = 0 No Yes Yes Device failed Set up next sector group address Data = 00h? Last sector group verified? No Yes Remove VID from RESET# Write reset command Sector Group Unprotect complete Sector Group Unprotect Algorithm This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 29 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Storage Temperature -65 to +125 °C Plastic Packages -65 to +125 °C Ambient Temperature With Power Applied -55 to +125 °C 200 mA VCC -0.5 to 4.0 V VIO -0.5 to 5.5 V -0.5 to +11.5 V 0.5 to VCC + 0.5 V Output Short Circuit Current1 P Voltage with Respect to Ground P A9, OE#, ACC and RESET# 2 P P All other pins 3 P P Notes: 1. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. 2. Minimum DC input voltage on A9, OE#, RESET# and WP#/ACC pins is –0.5V. During voltage transitions, A9, OE#, RESET# and WP#/ACC pins may undershoot Vss to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below. Maximum DC input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns. 3. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below. 4. Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. B B B B B B RECOMMENDED OPERATING RANGES1 P Operating Supply Voltage VCC B P Parameter Ambient Operating Temperature Commercial Devices Industrial Devices B Value Unit 0 to 70 -40 to 85 Full Voltage Range:2.7 to 3.6V Regulated Voltage Range:3.0 to 3.6V °C V 1.Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed. Maximum Negative Overshoot This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Maximum Positive Overshoot 30 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Waveform Waveform DC Characteristics Table 11. DC Characteristics Symbol ILI B Parameter Test Conditions Max Unit 0V≤ VIN ≤ VCC ±5 µA A9 = 11.5V 35 µA 0V≤ VOUT ≤ VCC ±5 µA 9 16 mA 20 30 mA 1 5.0 µA 1 5.0 mA 1 5.0 uA Input Leakage Current B B ILIT A9, ACC Input Load Current ILO Output Leakage Current B B B B B B B CE# = VIL ; OE# = B B VIH ; f = 5MHZ B B CE# = VIL, OE# = B ICC2 Supply Current (Program or Erase) B B Supply Current (Standby - CMOS) ICC3 B ICC4 B B B B RESET# = VSS ± 0.3V Reset Current B B VIH , WE# = VIL CE# = BYTE# = RESET# = VCC ± 0.3V (Note 1) B Typ B B Supply Current (read) ICC1 Min VIH = VCC ± 0.3V B ICC5 B VIL = VSS ± 0.3V, Automatic Sleep Mode B B B B WP# = VIH B VIL B Input Low Voltage B Input High Voltage VIH B B Voltage for ACC Program Acceleration Voltage for Autoselect or Temporary Sector Unprotect Output Low Voltage VHH B B VID B B VOL B B B B B B V V 10.5 11.5 V 10.5 11.5 V 0.45 V B IOH = -2.0 mA Output High Voltage CMOS IOH = -100 µA, B B B VLKO 0.8 Vcc ± 0.3 IOL = 4.0 mA Output High Voltage TTL VOH -0.5 0.7 x VCC B B Supply voltage (Erase and Program lock-out) 0.85 x VCC VCC 0.4V 2.3 V V 2.5 Notes: 1. Maximum ICC specifications are tested with VCC = VCC max. B B This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 31 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 V EN29LV641H/L EN29LV640U Test Conditions 3.3 V 2.7 kΩ Device under Test CL 6.2 kΩ Note: Diodes are IN3064 or equivalent Test Specifications Test Conditions 70R Output Load 90 Unit 1 TTL Gate Output Load Capacitance, CL B 30 30 pF 5 5 ns 0.0-3.0 0.0-3.0 V 1.5 1.5 V 0.5VIO 0.5VIO V B Input Rise and Fall times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels . Key to Switching Waveforms This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 32 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U AC CHARACTERISTICS Table 13. Read-only Operations Characteristics Parameter Symbols Standard Description tAVAV tRC Read Cycle Time B B B tAVQV B B tACC B B 70R 90 Unit Min 70 90 ns Max 70 90 ns Max 70 90 ns Output Enable to Output Delay Max 30 35 ns CE# = VIL OE# = VIL B Address to Output Delay B B tELQV B tCE B B Chip Enable To Output Delay B Speed Options Test Setup JEDEC B B B B OE# = VIL B B B B B tGLQV tOE tEHQZ tDF Chip Enable to Output High Z Max 20 20 ns tGHQZ tDF Output Enable to Output High Z Max 20 20 ns tAXQX tOH Output Hold Time from Addresses, CE# or OE#, whichever occurs first Min 0 0 ns Read Min 0 0 ns Toggle and Data# Polling Min 10 10 ns B B B B B B B B B B B B B B B B tOEH B B Output Enable Hold Time Figure 2. AC Waveforms for READ Operations tRC Addresses Stable Addresses tACC CE# tDF tOE OE# tOEH WE# tCE tOH Outputs Output Valid HIGH Z Reset# This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 33 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U AC CHARACTERISTICS Hardware Reset (RESET#) Table 12. Hardware Reset Operations Characteristics Parameter Description All Speed options Uni t tREADY RESET# Pin Low to Read or Write Embedded Algorithms Max 20 µs tREADY RESET# Pin Low to Read or Write Non Embedded Algorithms Max 500 nS RESET# Pulse Width Min 500 nS RESET# High Time Before Read Min 50 nS B B B B tRP B B tRH B B Figure 1. AC Waveforms for RESET# Reset# Timings CE# OE# tRH RESET# tRP tREADY Reset Timings NOT During Automatic Algorithms tREADY CE# OE# RESET# tRP tRH Reset Timings during Automatic Algorithms This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 34 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U AC CHARACTERISTICS Table 14. Write (Erase/Program) Operations Parameter Symbols Speed Options JEDEC Standard tAVAV tWC B B tWLAX B 90 ns Address Setup Time Min 0 0 ns tAH Address Hold Time Min 40 40 ns tDS Data Setup Time Min 40 40 ns Data Hold Time Min 0 0 ns Min 20 20 ns Min 0 0 ns CE# Setup Time Min 0 0 ns CE# Hold Time Min 0 0 ns Write Pulse Width Min 30 30 ns Write Pulse Width High Min 25 25 ns Programming Operation Typ 8 8 µs Accelerated Programming Operation Typ 5 5 µs Sector Erase Operation Typ 0.5 0.5 s Chip Erase Operation Typ 64 64 s tVHH VHH Rise and Fall Time Min 250 250 ns tVCS VCC Setup Time Min 50 50 µs B B B B B B B B tWHDX B tDH B B B B Output Enable Hold Time during Toggle and DATA# Polling Read Recovery Time before Write (OE# High to WE# Low) tOEH B tGHWL B tELWL B B tGHWL B B B B B tCH B B B tWLWH tWP tWHDL tWPH B B B B B B tWHWH1 B B tWHWH1 B B tWHWH2 B tWHWH1 B B B B B tWHWH2 B tWHWH3 B B tWHWH1 B B tCS B tWHEH Unit 70 B tDVWH 90 Min B tAS B 70R Write Cycle Time B tAVWL Description tWHWH3 B B B B B B B This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 35 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U AC CHARACTERISTICS Table 15. Write (Erase/Program) Operations Alternate CE# Controlled Writes Parameter Symbols Speed Options JEDEC Standard tAVAV tWC tAVEL tAS tELAX 70R 90 Unit Write Cycle Time Min 70 90 ns Address Setup Time Min 0 0 ns tAH Address Hold Time Min 40 40 ns tDVEH tDS Data Setup Time Min 40 40 ns tEHDX tDH Data Hold Time Min 0 0 ns tGHEL tGHEL Read Recovery Time before Write (OE# High to CE# Low) Min 0 0 ns WE# Setup Time Min 0 0 ns WE# Hold Time Min 0 0 ns CE# Pulse Width Min 35 45 ns CE# Pulse Width High Min 20 20 ns Programming Operation Typ 8 8 µs Accelerated Programming Operation Typ 5 5 µs Sector Erase Operation Typ 0.5 0.5 s B B B B B B B B B B B B B B tWS B tEHWH B B B B tWLEL B B B B B B B B tWH B B B tCP tEHEL tCPH B B B B tWHWH1 B B B B tWHWH1 B tWHWH1 B B B B B tWHWH1 B tWHWH2 B B tELEH B B Description tWHWH2 B B B This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 36 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U AC CHARACTERISTICS Figure 3. AC Waveforms for Chip/Sector Erase Operations Timings Erase Command Sequence (last 2 cycles) Addresses tWC tAS 0x2AA SA Read Status Data (last two cycles) tAH VA VA 0x555 for chip erase CE# TGHWL OE# tCH tWP WE# tCS tWPH tWHWH2 or tWHWH3 Data 0x55 tDS 0x30 tDH Status tBUSY DOUT tRB RY/BY# VCC tVCS Notes: 1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout =true data at read address. 2. Vcc is shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command sequence. B B B B B B This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 37 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Figure 4. Program Operation Timings Program Command Sequence (last 2 cycles) Addresses tWC tAS 0x555 PA Program Command Sequence (last 2 cycles) tAH PA PA CE# tGHWL OE# tCH tWP WE# tWPH tWHWH1 tCS Data PD OxA0 Status DOUT tDS tRB tBUSY tDH RY/BY# tVCS VCC Notes: 1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address. 2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence. B B B B B B Figure 5. Accelerated Program Timing Diagram VHH B B ACC 0 or 3 V 0 or 3 V tVHH B tVHH B B B CE# WE# tRSP B B AC CHARACTERISTICS This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 38 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Figure 6. AC Waveforms for /DATA Polling During Embedded Algorithm Operations tRC Addresses VA VA VA tACC tCH tCE CE# tOE OE# tOEH tDF WE# tOH Complement Complement DQ[7] DQ[6:0] Status Data Status Data True Valid Data True Valid Data TBUSY RY/BY# Notes: 1. VA = Valid Address for reading Data# Polling status data 2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle. Figure 7. AC Waveforms for Toggle Bit During Embedded Algorithm Operations tRC Addresses VA VA VA VA tACC tCH tCE CE# tOE OE# tOEH WE# tDF tOH Valid Status DQ6, DQ2 tBUSY (first read) Valid Status (second d) Valid Status Valid Data (stops toggling) RY/BY# This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 39 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Figure 8. Alternate CE# Controlled Write Operation Timings PA for Program SA for Sector Erase 0x555 for Chip Erase 0x555 for Program 0x2AA for Erase Addresses VA tAS tWC tAH WE# tWH tGHEL OE# tCP tCPH tWS tCWHWH1 / tCWHWH2 / tCWHWH3 CE# tDS tBUSY tDH Data Status DOUT PD for Program 0x30 for Sector Erase 0x10 for Chip Erase 0xA0 for Program RY/BY# tRH Reset# Notes: PA = address of the memory location to be programmed. PD = data to be programmed at byte address. VA = Valid Address for reading program or erase status Dout = array data read at VA Shown above are the last two cycles of the program or erase command sequence and the last status read cycle RESETt# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command sequence. B B B B Figure 9. DQ2 vs. DQ6 Enter Embedded Erase WE# Enter Erase Suspend Program Erase Suspend Erase Enter Suspend Read Erase Resume Enter Suspend Program Erase Suspend Read Erase DQ6 DQ2 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 40 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 Erase Complete EN29LV641H/L EN29LV640U AC CHARACTERISTICS Temporary Sector Group Unprotect Parameter Std Description tVIDR VID Rise and Fall Time VHH Rise and Fall Time RESET# Setup Time for Temporary Sector Unprotect B tVIHH B B B B B tRSP B B B B Speed Option 70R 90 Unit Min 500 Ns Min 500 Ns Min 4 µs Figure 10. Temporary Sector Group Unprotect Timing Diagram VID RESET# 0 or 3 V 0 or 3 V tVIDR tVIDR CE# WE# tRSP AC CHARACTERISTICS Figure 11. Sector Group Protect and Unprotect Timing Diagram VID RESET# Vcc 0V 0V tVIDR tVIDR SA, A6,A1,A0 Data 60h Valid Valid Valid 60h 40h Status Sector Protect/Unprotect Verify CE# >0.4µS WE# >1µS Protect: 150 uS Unprotect: 15 mS OE# Notes: Use standard microprocessor timings for this device for read and write cycles. For Sector Group Protect, use A6=0, A1=1, A0=0. For Sector Group Unprotect, use A6=1, A1=1, A0=0. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 41 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U ERASE AND PROGRAM PERFORMANCE Typ Limits Max Unit Sector Erase Time 0.5 10 Sec Chip Erase Time 64 Word Programming Time 8 300 µS Accelerated Word Program Time 5 120 µS Chip Programming Time 20 60 Sec Parameter Erase/Program Endurance Comments Excludes 00h programming prior to erasure Sec 100K Excludes system level overhead Minimum 100K cycles Cycles Note: Typical Conditions are room temperature, 3V and checkboard pattern programmed. LATCH UP CHARACTERISTICS Parameter Description Min Max Input voltage with respect to Vss on all pins except I/O pins (including A9, Reset and OE#) -1.0 V 12.0 V Input voltage with respect to Vss on all I/O Pins -1.0 V VCC + 1.0 V VCC Current -100 mA 100 mA B B B B Note: These are latch up characteristics and the device should never be put under these conditions. Refer to Absolute Maximum ratings for the actual operating limits. 48-PIN TSOP PACKAGE CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ Max Unit Input Capacitance VIN = 0 6 7.5 pF COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF CIN B B B B B B B B B B B B Note: Test conditions are Temperature = 25°C and f = 1.0 MHz. DATA RETENTION Parameter Description Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 42 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U FIGURE 12. TSOP 12mm x 20mm This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 43 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 44 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U FIGURE 13. 63-TFBGA 11mm x 12mm package outline This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 45 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27 EN29LV641H/L EN29LV640U Revisions History Revision No Description Date A Initial Release 1. VIO input should be tied to VCC only not supporting to 1.8V output 2. revise the package code for 63 balls TFBGA from “B” to “W” at 2005/02/21 B page 5 3. a typo at tOE specification at page 2 and page 33, it shall be 30 ns 2005/06/27 and 35ns for 70R ns and 90ns product respectively. 4. Icc3 stand by current only reserves the CMOS condition This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 46 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw Rev. B, Issue Date: 2005/06/27